1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
41 // A clone of X86 since we can't depend on something that is generated.
51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
56 #define MAP(from, to) MRM_##from = to,
67 D8 = 3, D9 = 4, DA = 5, DB = 6,
68 DC = 7, DD = 8, DE = 9, DF = 10,
71 A6 = 15, A7 = 16, TF = 17
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
92 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(c6) \
101 EXTENSION_TABLE(c7) \
102 EXTENSION_TABLE(d0) \
103 EXTENSION_TABLE(d1) \
104 EXTENSION_TABLE(d2) \
105 EXTENSION_TABLE(d3) \
106 EXTENSION_TABLE(f6) \
107 EXTENSION_TABLE(f7) \
108 EXTENSION_TABLE(fe) \
111 #define TWO_BYTE_EXTENSION_TABLES \
112 EXTENSION_TABLE(00) \
113 EXTENSION_TABLE(01) \
114 EXTENSION_TABLE(18) \
115 EXTENSION_TABLE(71) \
116 EXTENSION_TABLE(72) \
117 EXTENSION_TABLE(73) \
118 EXTENSION_TABLE(ae) \
119 EXTENSION_TABLE(ba) \
122 using namespace X86Disassembler;
124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
125 /// ModR/M byte for the instruction to be properly decoded. For example, a
126 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
129 /// @param form - The form of the instruction.
130 /// @return - true if the form implies that a ModR/M byte is required, false
132 static bool needsModRMForDecode(uint8_t form) {
133 if (form == X86Local::MRMDestReg ||
134 form == X86Local::MRMDestMem ||
135 form == X86Local::MRMSrcReg ||
136 form == X86Local::MRMSrcMem ||
137 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
145 /// the ModR/M byte to be 0b11.
147 /// @param form - The form of the instruction.
148 /// @return - true if the form implies that Mod must be 0b11, false
150 static bool isRegFormat(uint8_t form) {
151 if (form == X86Local::MRMDestReg ||
152 form == X86Local::MRMSrcReg ||
153 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160 /// Useful for switch statements and the like.
162 /// @param init - A reference to the BitsInit to be decoded.
163 /// @return - The field, with the first bit in the BitsInit as the lowest
165 static uint8_t byteFromBitsInit(BitsInit &init) {
166 int width = init.getNumBits();
168 assert(width <= 8 && "Field is too large for uint8_t!");
175 for (index = 0; index < width; index++) {
176 if (static_cast<BitInit*>(init.getBit(index))->getValue())
185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186 /// name of the field.
188 /// @param rec - The record from which to extract the value.
189 /// @param name - The name of the field in the record.
190 /// @return - The field, as translated by byteFromBitsInit().
191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192 BitsInit* bits = rec->getValueAsBitsInit(name);
193 return byteFromBitsInit(*bits);
196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197 const CodeGenInstruction &insn,
202 Name = Rec->getName();
203 Spec = &tables.specForUID(UID);
205 if (!Rec->isSubClassOf("X86Inst")) {
206 ShouldBeEmitted = false;
210 Prefix = byteFromRec(Rec, "Prefix");
211 Opcode = byteFromRec(Rec, "Opcode");
212 Form = byteFromRec(Rec, "FormBits");
213 SegOvr = byteFromRec(Rec, "SegOvrBits");
215 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
216 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
217 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
218 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
219 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
220 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
221 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
222 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
224 Name = Rec->getName();
225 AsmString = Rec->getValueAsString("AsmString");
227 Operands = &insn.Operands.OperandList;
229 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
230 (Name.find("CRC32") != Name.npos);
231 HasFROperands = hasFROperands();
232 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
234 // Check for 64-bit inst which does not require REX
237 // FIXME: Is there some better way to check for In64BitMode?
238 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
239 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
240 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
244 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
249 // FIXME: These instructions aren't marked as 64-bit in any way
250 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
251 Rec->getName() == "MASKMOVDQU64" ||
252 Rec->getName() == "POPFS64" ||
253 Rec->getName() == "POPGS64" ||
254 Rec->getName() == "PUSHFS64" ||
255 Rec->getName() == "PUSHGS64" ||
256 Rec->getName() == "REX64_PREFIX" ||
257 Rec->getName().find("VMREAD64") != Name.npos ||
258 Rec->getName().find("VMWRITE64") != Name.npos ||
259 Rec->getName().find("INVEPT64") != Name.npos ||
260 Rec->getName().find("INVVPID64") != Name.npos ||
261 Rec->getName().find("MOV64") != Name.npos ||
262 Rec->getName().find("PUSH64") != Name.npos ||
263 Rec->getName().find("POP64") != Name.npos;
265 ShouldBeEmitted = true;
268 void RecognizableInstr::processInstr(DisassemblerTables &tables,
269 const CodeGenInstruction &insn,
272 // Ignore "asm parser only" instructions.
273 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
276 RecognizableInstr recogInstr(tables, insn, uid);
278 recogInstr.emitInstructionSpecifier(tables);
280 if (recogInstr.shouldBeEmitted())
281 recogInstr.emitDecodePath(tables);
284 InstructionContext RecognizableInstr::insnContext() const {
285 InstructionContext insnContext;
287 if (HasVEX_4VPrefix || HasVEXPrefix) {
288 if (HasVEX_LPrefix && HasVEX_WPrefix)
289 llvm_unreachable("Don't support VEX.L and VEX.W together");
290 else if (HasOpSizePrefix && HasVEX_LPrefix)
291 insnContext = IC_VEX_L_OPSIZE;
292 else if (HasOpSizePrefix && HasVEX_WPrefix)
293 insnContext = IC_VEX_W_OPSIZE;
294 else if (HasOpSizePrefix)
295 insnContext = IC_VEX_OPSIZE;
296 else if (HasVEX_LPrefix && Prefix == X86Local::XS)
297 insnContext = IC_VEX_L_XS;
298 else if (HasVEX_LPrefix && Prefix == X86Local::XD)
299 insnContext = IC_VEX_L_XD;
300 else if (HasVEX_WPrefix && Prefix == X86Local::XS)
301 insnContext = IC_VEX_W_XS;
302 else if (HasVEX_WPrefix && Prefix == X86Local::XD)
303 insnContext = IC_VEX_W_XD;
304 else if (HasVEX_WPrefix)
305 insnContext = IC_VEX_W;
306 else if (HasVEX_LPrefix)
307 insnContext = IC_VEX_L;
308 else if (Prefix == X86Local::XD)
309 insnContext = IC_VEX_XD;
310 else if (Prefix == X86Local::XS)
311 insnContext = IC_VEX_XS;
313 insnContext = IC_VEX;
314 } else if (Is64Bit || HasREX_WPrefix) {
315 if (HasREX_WPrefix && HasOpSizePrefix)
316 insnContext = IC_64BIT_REXW_OPSIZE;
317 else if (HasOpSizePrefix &&
318 (Prefix == X86Local::XD || Prefix == X86Local::TF))
319 insnContext = IC_64BIT_XD_OPSIZE;
320 else if (HasOpSizePrefix && Prefix == X86Local::XS)
321 insnContext = IC_64BIT_XS_OPSIZE;
322 else if (HasOpSizePrefix)
323 insnContext = IC_64BIT_OPSIZE;
324 else if (HasREX_WPrefix && Prefix == X86Local::XS)
325 insnContext = IC_64BIT_REXW_XS;
326 else if (HasREX_WPrefix &&
327 (Prefix == X86Local::XD || Prefix == X86Local::TF))
328 insnContext = IC_64BIT_REXW_XD;
329 else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
330 insnContext = IC_64BIT_XD;
331 else if (Prefix == X86Local::XS)
332 insnContext = IC_64BIT_XS;
333 else if (HasREX_WPrefix)
334 insnContext = IC_64BIT_REXW;
336 insnContext = IC_64BIT;
338 if (HasOpSizePrefix &&
339 (Prefix == X86Local::XD || Prefix == X86Local::TF))
340 insnContext = IC_XD_OPSIZE;
341 else if (HasOpSizePrefix && Prefix == X86Local::XS)
342 insnContext = IC_XS_OPSIZE;
343 else if (HasOpSizePrefix)
344 insnContext = IC_OPSIZE;
345 else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
347 else if (Prefix == X86Local::XS || Prefix == X86Local::REP)
356 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
361 // Filter out intrinsics
363 if (!Rec->isSubClassOf("X86Inst"))
364 return FILTER_STRONG;
366 if (Form == X86Local::Pseudo ||
367 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
368 return FILTER_STRONG;
370 if (Form == X86Local::MRMInitReg)
371 return FILTER_STRONG;
374 // Filter out artificial instructions
376 if (Name.find("TAILJMP") != Name.npos ||
377 Name.find("_Int") != Name.npos ||
378 Name.find("_int") != Name.npos ||
379 Name.find("Int_") != Name.npos ||
380 Name.find("_NOREX") != Name.npos ||
381 Name.find("_TC") != Name.npos ||
382 Name.find("EH_RETURN") != Name.npos ||
383 Name.find("V_SET") != Name.npos ||
384 Name.find("LOCK_") != Name.npos ||
385 Name.find("WIN") != Name.npos ||
386 Name.find("_AVX") != Name.npos ||
387 Name.find("2SDL") != Name.npos)
388 return FILTER_STRONG;
390 // Filter out instructions with segment override prefixes.
391 // They're too messy to handle now and we'll special case them if needed.
394 return FILTER_STRONG;
396 // Filter out instructions that can't be printed.
398 if (AsmString.size() == 0)
399 return FILTER_STRONG;
401 // Filter out instructions with subreg operands.
403 if (AsmString.find("subreg") != AsmString.npos)
404 return FILTER_STRONG;
411 // Filter out instructions with a LOCK prefix;
412 // prefer forms that do not have the prefix
416 // Filter out alternate forms of AVX instructions
417 if (Name.find("_alt") != Name.npos ||
418 Name.find("XrYr") != Name.npos ||
419 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
420 Name.find("_64mr") != Name.npos ||
421 Name.find("Xrr") != Name.npos ||
422 Name.find("rr64") != Name.npos)
425 if (Name == "VMASKMOVDQU64" ||
426 Name == "VEXTRACTPSrr64" ||
427 Name == "VMOVQd64rr" ||
428 Name == "VMOVQs64rr")
433 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
435 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
438 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
440 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
442 if (Name.find("Fs") != Name.npos)
444 if (Name == "MOVLPDrr" ||
445 Name == "MOVLPSrr" ||
451 Name == "MOVSX16rm8" ||
452 Name == "MOVSX16rr8" ||
453 Name == "MOVZX16rm8" ||
454 Name == "MOVZX16rr8" ||
455 Name == "PUSH32i16" ||
456 Name == "PUSH64i16" ||
457 Name == "MOVPQI2QImr" ||
458 Name == "VMOVPQI2QImr" ||
463 Name == "MMX_MOVD64rrv164" ||
464 Name == "CRC32m16" ||
465 Name == "MOV64ri64i32" ||
469 if (HasFROperands && Name.find("MOV") != Name.npos &&
470 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
471 (Name.find("to") != Name.npos)))
474 return FILTER_NORMAL;
477 bool RecognizableInstr::hasFROperands() const {
478 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
479 unsigned numOperands = OperandList.size();
481 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
482 const std::string &recName = OperandList[operandIndex].Rec->getName();
484 if (recName.find("FR") != recName.npos)
490 bool RecognizableInstr::has256BitOperands() const {
491 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
492 unsigned numOperands = OperandList.size();
494 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
495 const std::string &recName = OperandList[operandIndex].Rec->getName();
497 if (!recName.compare("VR256") || !recName.compare("f256mem")) {
504 void RecognizableInstr::handleOperand(
506 unsigned &operandIndex,
507 unsigned &physicalOperandIndex,
508 unsigned &numPhysicalOperands,
509 unsigned *operandMapping,
510 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
512 if (physicalOperandIndex >= numPhysicalOperands)
515 assert(physicalOperandIndex < numPhysicalOperands);
518 while (operandMapping[operandIndex] != operandIndex) {
519 Spec->operands[operandIndex].encoding = ENCODING_DUP;
520 Spec->operands[operandIndex].type =
521 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
525 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
527 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
529 Spec->operands[operandIndex].type = typeFromString(typeName,
535 ++physicalOperandIndex;
538 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
541 if (!Rec->isSubClassOf("X86Inst"))
546 Spec->filtered = true;
549 ShouldBeEmitted = false;
555 Spec->insnContext = insnContext();
557 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
559 unsigned operandIndex;
560 unsigned numOperands = OperandList.size();
561 unsigned numPhysicalOperands = 0;
563 // operandMapping maps from operands in OperandList to their originals.
564 // If operandMapping[i] != i, then the entry is a duplicate.
565 unsigned operandMapping[X86_MAX_OPERANDS];
567 bool hasFROperands = false;
569 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
571 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
572 if (OperandList[operandIndex].Constraints.size()) {
573 const CGIOperandList::ConstraintInfo &Constraint =
574 OperandList[operandIndex].Constraints[0];
575 if (Constraint.isTied()) {
576 operandMapping[operandIndex] = Constraint.getTiedOperand();
578 ++numPhysicalOperands;
579 operandMapping[operandIndex] = operandIndex;
582 ++numPhysicalOperands;
583 operandMapping[operandIndex] = operandIndex;
586 const std::string &recName = OperandList[operandIndex].Rec->getName();
588 if (recName.find("FR") != recName.npos)
589 hasFROperands = true;
592 if (hasFROperands && Name.find("MOV") != Name.npos &&
593 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
594 (Name.find("to") != Name.npos)))
595 ShouldBeEmitted = false;
597 if (!ShouldBeEmitted)
600 #define HANDLE_OPERAND(class) \
601 handleOperand(false, \
603 physicalOperandIndex, \
604 numPhysicalOperands, \
606 class##EncodingFromString);
608 #define HANDLE_OPTIONAL(class) \
609 handleOperand(true, \
611 physicalOperandIndex, \
612 numPhysicalOperands, \
614 class##EncodingFromString);
616 // operandIndex should always be < numOperands
618 // physicalOperandIndex should always be < numPhysicalOperands
619 unsigned physicalOperandIndex = 0;
622 case X86Local::RawFrm:
623 // Operand 1 (optional) is an address or immediate.
624 // Operand 2 (optional) is an immediate.
625 assert(numPhysicalOperands <= 2 &&
626 "Unexpected number of operands for RawFrm");
627 HANDLE_OPTIONAL(relocation)
628 HANDLE_OPTIONAL(immediate)
630 case X86Local::AddRegFrm:
631 // Operand 1 is added to the opcode.
632 // Operand 2 (optional) is an address.
633 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
634 "Unexpected number of operands for AddRegFrm");
635 HANDLE_OPERAND(opcodeModifier)
636 HANDLE_OPTIONAL(relocation)
638 case X86Local::MRMDestReg:
639 // Operand 1 is a register operand in the R/M field.
640 // Operand 2 is a register operand in the Reg/Opcode field.
641 // - In AVX, there is a register operand in the VEX.vvvv field here -
642 // Operand 3 (optional) is an immediate.
644 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
645 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
647 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
648 "Unexpected number of operands for MRMDestRegFrm");
650 HANDLE_OPERAND(rmRegister)
653 // FIXME: In AVX, the register below becomes the one encoded
654 // in ModRMVEX and the one above the one in the VEX.VVVV field
655 HANDLE_OPERAND(vvvvRegister)
657 HANDLE_OPERAND(roRegister)
658 HANDLE_OPTIONAL(immediate)
660 case X86Local::MRMDestMem:
661 // Operand 1 is a memory operand (possibly SIB-extended)
662 // Operand 2 is a register operand in the Reg/Opcode field.
663 // - In AVX, there is a register operand in the VEX.vvvv field here -
664 // Operand 3 (optional) is an immediate.
666 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
667 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
669 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
670 "Unexpected number of operands for MRMDestMemFrm");
671 HANDLE_OPERAND(memory)
674 // FIXME: In AVX, the register below becomes the one encoded
675 // in ModRMVEX and the one above the one in the VEX.VVVV field
676 HANDLE_OPERAND(vvvvRegister)
678 HANDLE_OPERAND(roRegister)
679 HANDLE_OPTIONAL(immediate)
681 case X86Local::MRMSrcReg:
682 // Operand 1 is a register operand in the Reg/Opcode field.
683 // Operand 2 is a register operand in the R/M field.
684 // - In AVX, there is a register operand in the VEX.vvvv field here -
685 // Operand 3 (optional) is an immediate.
688 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
689 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
691 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
692 "Unexpected number of operands for MRMSrcRegFrm");
694 HANDLE_OPERAND(roRegister)
697 // FIXME: In AVX, the register below becomes the one encoded
698 // in ModRMVEX and the one above the one in the VEX.VVVV field
699 HANDLE_OPERAND(vvvvRegister)
701 HANDLE_OPERAND(rmRegister)
702 HANDLE_OPTIONAL(immediate)
704 case X86Local::MRMSrcMem:
705 // Operand 1 is a register operand in the Reg/Opcode field.
706 // Operand 2 is a memory operand (possibly SIB-extended)
707 // - In AVX, there is a register operand in the VEX.vvvv field here -
708 // Operand 3 (optional) is an immediate.
711 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
712 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
714 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
715 "Unexpected number of operands for MRMSrcMemFrm");
717 HANDLE_OPERAND(roRegister)
720 // FIXME: In AVX, the register below becomes the one encoded
721 // in ModRMVEX and the one above the one in the VEX.VVVV field
722 HANDLE_OPERAND(vvvvRegister)
724 HANDLE_OPERAND(memory)
725 HANDLE_OPTIONAL(immediate)
727 case X86Local::MRM0r:
728 case X86Local::MRM1r:
729 case X86Local::MRM2r:
730 case X86Local::MRM3r:
731 case X86Local::MRM4r:
732 case X86Local::MRM5r:
733 case X86Local::MRM6r:
734 case X86Local::MRM7r:
735 // Operand 1 is a register operand in the R/M field.
736 // Operand 2 (optional) is an immediate or relocation.
738 assert(numPhysicalOperands <= 3 &&
739 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
741 assert(numPhysicalOperands <= 2 &&
742 "Unexpected number of operands for MRMnRFrm");
744 HANDLE_OPERAND(vvvvRegister);
745 HANDLE_OPTIONAL(rmRegister)
746 HANDLE_OPTIONAL(relocation)
748 case X86Local::MRM0m:
749 case X86Local::MRM1m:
750 case X86Local::MRM2m:
751 case X86Local::MRM3m:
752 case X86Local::MRM4m:
753 case X86Local::MRM5m:
754 case X86Local::MRM6m:
755 case X86Local::MRM7m:
756 // Operand 1 is a memory operand (possibly SIB-extended)
757 // Operand 2 (optional) is an immediate or relocation.
758 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
759 "Unexpected number of operands for MRMnMFrm");
760 HANDLE_OPERAND(memory)
761 HANDLE_OPTIONAL(relocation)
763 case X86Local::RawFrmImm8:
764 // operand 1 is a 16-bit immediate
765 // operand 2 is an 8-bit immediate
766 assert(numPhysicalOperands == 2 &&
767 "Unexpected number of operands for X86Local::RawFrmImm8");
768 HANDLE_OPERAND(immediate)
769 HANDLE_OPERAND(immediate)
771 case X86Local::RawFrmImm16:
772 // operand 1 is a 16-bit immediate
773 // operand 2 is a 16-bit immediate
774 HANDLE_OPERAND(immediate)
775 HANDLE_OPERAND(immediate)
777 case X86Local::MRMInitReg:
782 #undef HANDLE_OPERAND
783 #undef HANDLE_OPTIONAL
786 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
787 // Special cases where the LLVM tables are not complete
789 #define MAP(from, to) \
790 case X86Local::MRM_##from: \
791 filter = new ExactFilter(0x##from); \
794 OpcodeType opcodeType = (OpcodeType)-1;
796 ModRMFilter* filter = NULL;
797 uint8_t opcodeToSet = 0;
800 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
804 opcodeType = TWOBYTE;
808 if (needsModRMForDecode(Form))
809 filter = new ModFilter(isRegFormat(Form));
811 filter = new DumbFilter();
813 #define EXTENSION_TABLE(n) case 0x##n:
814 TWO_BYTE_EXTENSION_TABLES
815 #undef EXTENSION_TABLE
818 llvm_unreachable("Unhandled two-byte extended opcode");
819 case X86Local::MRM0r:
820 case X86Local::MRM1r:
821 case X86Local::MRM2r:
822 case X86Local::MRM3r:
823 case X86Local::MRM4r:
824 case X86Local::MRM5r:
825 case X86Local::MRM6r:
826 case X86Local::MRM7r:
827 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
829 case X86Local::MRM0m:
830 case X86Local::MRM1m:
831 case X86Local::MRM2m:
832 case X86Local::MRM3m:
833 case X86Local::MRM4m:
834 case X86Local::MRM5m:
835 case X86Local::MRM6m:
836 case X86Local::MRM7m:
837 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
843 opcodeToSet = Opcode;
847 opcodeType = THREEBYTE_38;
848 if (needsModRMForDecode(Form))
849 filter = new ModFilter(isRegFormat(Form));
851 filter = new DumbFilter();
852 opcodeToSet = Opcode;
855 opcodeType = THREEBYTE_3A;
856 if (needsModRMForDecode(Form))
857 filter = new ModFilter(isRegFormat(Form));
859 filter = new DumbFilter();
860 opcodeToSet = Opcode;
863 opcodeType = THREEBYTE_A6;
864 if (needsModRMForDecode(Form))
865 filter = new ModFilter(isRegFormat(Form));
867 filter = new DumbFilter();
868 opcodeToSet = Opcode;
871 opcodeType = THREEBYTE_A7;
872 if (needsModRMForDecode(Form))
873 filter = new ModFilter(isRegFormat(Form));
875 filter = new DumbFilter();
876 opcodeToSet = Opcode;
886 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
887 opcodeType = ONEBYTE;
888 if (Form == X86Local::AddRegFrm) {
889 Spec->modifierType = MODIFIER_MODRM;
890 Spec->modifierBase = Opcode;
891 filter = new AddRegEscapeFilter(Opcode);
893 filter = new EscapeFilter(true, Opcode);
895 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
899 opcodeType = ONEBYTE;
901 #define EXTENSION_TABLE(n) case 0x##n:
902 ONE_BYTE_EXTENSION_TABLES
903 #undef EXTENSION_TABLE
906 llvm_unreachable("Fell through the cracks of a single-byte "
908 case X86Local::MRM0r:
909 case X86Local::MRM1r:
910 case X86Local::MRM2r:
911 case X86Local::MRM3r:
912 case X86Local::MRM4r:
913 case X86Local::MRM5r:
914 case X86Local::MRM6r:
915 case X86Local::MRM7r:
916 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
918 case X86Local::MRM0m:
919 case X86Local::MRM1m:
920 case X86Local::MRM2m:
921 case X86Local::MRM3m:
922 case X86Local::MRM4m:
923 case X86Local::MRM5m:
924 case X86Local::MRM6m:
925 case X86Local::MRM7m:
926 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
939 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
942 if (needsModRMForDecode(Form))
943 filter = new ModFilter(isRegFormat(Form));
945 filter = new DumbFilter();
948 opcodeToSet = Opcode;
951 assert(opcodeType != (OpcodeType)-1 &&
952 "Opcode type not set");
953 assert(filter && "Filter not set");
955 if (Form == X86Local::AddRegFrm) {
956 if(Spec->modifierType != MODIFIER_MODRM) {
957 assert(opcodeToSet < 0xf9 &&
958 "Not enough room for all ADDREG_FRM operands");
960 uint8_t currentOpcode;
962 for (currentOpcode = opcodeToSet;
963 currentOpcode < opcodeToSet + 8;
965 tables.setTableFields(opcodeType,
969 UID, Is32Bit, IgnoresVEX_L);
971 Spec->modifierType = MODIFIER_OPCODE;
972 Spec->modifierBase = opcodeToSet;
974 // modifierBase was set where MODIFIER_MODRM was set
975 tables.setTableFields(opcodeType,
979 UID, Is32Bit, IgnoresVEX_L);
982 tables.setTableFields(opcodeType,
986 UID, Is32Bit, IgnoresVEX_L);
988 Spec->modifierType = MODIFIER_NONE;
989 Spec->modifierBase = opcodeToSet;
997 #define TYPE(str, type) if (s == str) return type;
998 OperandType RecognizableInstr::typeFromString(const std::string &s,
1000 bool hasREX_WPrefix,
1001 bool hasOpSizePrefix) {
1003 // For SSE instructions, we ignore the OpSize prefix and force operand
1005 TYPE("GR16", TYPE_R16)
1006 TYPE("GR32", TYPE_R32)
1007 TYPE("GR64", TYPE_R64)
1009 if(hasREX_WPrefix) {
1010 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1012 TYPE("GR32", TYPE_R32)
1014 if(!hasOpSizePrefix) {
1015 // For instructions without an OpSize prefix, a declared 16-bit register or
1016 // immediate encoding is special.
1017 TYPE("GR16", TYPE_R16)
1018 TYPE("i16imm", TYPE_IMM16)
1020 TYPE("i16mem", TYPE_Mv)
1021 TYPE("i16imm", TYPE_IMMv)
1022 TYPE("i16i8imm", TYPE_IMMv)
1023 TYPE("GR16", TYPE_Rv)
1024 TYPE("i32mem", TYPE_Mv)
1025 TYPE("i32imm", TYPE_IMMv)
1026 TYPE("i32i8imm", TYPE_IMM32)
1027 TYPE("u32u8imm", TYPE_IMM32)
1028 TYPE("GR32", TYPE_Rv)
1029 TYPE("i64mem", TYPE_Mv)
1030 TYPE("i64i32imm", TYPE_IMM64)
1031 TYPE("i64i8imm", TYPE_IMM64)
1032 TYPE("GR64", TYPE_R64)
1033 TYPE("i8mem", TYPE_M8)
1034 TYPE("i8imm", TYPE_IMM8)
1035 TYPE("GR8", TYPE_R8)
1036 TYPE("VR128", TYPE_XMM128)
1037 TYPE("f128mem", TYPE_M128)
1038 TYPE("f256mem", TYPE_M256)
1039 TYPE("FR64", TYPE_XMM64)
1040 TYPE("f64mem", TYPE_M64FP)
1041 TYPE("sdmem", TYPE_M64FP)
1042 TYPE("FR32", TYPE_XMM32)
1043 TYPE("f32mem", TYPE_M32FP)
1044 TYPE("ssmem", TYPE_M32FP)
1045 TYPE("RST", TYPE_ST)
1046 TYPE("i128mem", TYPE_M128)
1047 TYPE("i256mem", TYPE_M256)
1048 TYPE("i64i32imm_pcrel", TYPE_REL64)
1049 TYPE("i16imm_pcrel", TYPE_REL16)
1050 TYPE("i32imm_pcrel", TYPE_REL32)
1051 TYPE("SSECC", TYPE_IMM3)
1052 TYPE("brtarget", TYPE_RELv)
1053 TYPE("uncondbrtarget", TYPE_RELv)
1054 TYPE("brtarget8", TYPE_REL8)
1055 TYPE("f80mem", TYPE_M80FP)
1056 TYPE("lea32mem", TYPE_LEA)
1057 TYPE("lea64_32mem", TYPE_LEA)
1058 TYPE("lea64mem", TYPE_LEA)
1059 TYPE("VR64", TYPE_MM64)
1060 TYPE("i64imm", TYPE_IMMv)
1061 TYPE("opaque32mem", TYPE_M1616)
1062 TYPE("opaque48mem", TYPE_M1632)
1063 TYPE("opaque80mem", TYPE_M1664)
1064 TYPE("opaque512mem", TYPE_M512)
1065 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1066 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1067 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1068 TYPE("offset8", TYPE_MOFFS8)
1069 TYPE("offset16", TYPE_MOFFS16)
1070 TYPE("offset32", TYPE_MOFFS32)
1071 TYPE("offset64", TYPE_MOFFS64)
1072 TYPE("VR256", TYPE_XMM256)
1073 TYPE("GR16_NOAX", TYPE_Rv)
1074 TYPE("GR32_NOAX", TYPE_Rv)
1075 TYPE("GR64_NOAX", TYPE_R64)
1076 errs() << "Unhandled type string " << s << "\n";
1077 llvm_unreachable("Unhandled type string");
1081 #define ENCODING(str, encoding) if (s == str) return encoding;
1082 OperandEncoding RecognizableInstr::immediateEncodingFromString
1083 (const std::string &s,
1084 bool hasOpSizePrefix) {
1085 if(!hasOpSizePrefix) {
1086 // For instructions without an OpSize prefix, a declared 16-bit register or
1087 // immediate encoding is special.
1088 ENCODING("i16imm", ENCODING_IW)
1090 ENCODING("i32i8imm", ENCODING_IB)
1091 ENCODING("u32u8imm", ENCODING_IB)
1092 ENCODING("SSECC", ENCODING_IB)
1093 ENCODING("i16imm", ENCODING_Iv)
1094 ENCODING("i16i8imm", ENCODING_IB)
1095 ENCODING("i32imm", ENCODING_Iv)
1096 ENCODING("i64i32imm", ENCODING_ID)
1097 ENCODING("i64i8imm", ENCODING_IB)
1098 ENCODING("i8imm", ENCODING_IB)
1099 // This is not a typo. Instructions like BLENDVPD put
1100 // register IDs in 8-bit immediates nowadays.
1101 ENCODING("VR256", ENCODING_IB)
1102 ENCODING("VR128", ENCODING_IB)
1103 errs() << "Unhandled immediate encoding " << s << "\n";
1104 llvm_unreachable("Unhandled immediate encoding");
1107 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1108 (const std::string &s,
1109 bool hasOpSizePrefix) {
1110 ENCODING("GR16", ENCODING_RM)
1111 ENCODING("GR32", ENCODING_RM)
1112 ENCODING("GR64", ENCODING_RM)
1113 ENCODING("GR8", ENCODING_RM)
1114 ENCODING("VR128", ENCODING_RM)
1115 ENCODING("FR64", ENCODING_RM)
1116 ENCODING("FR32", ENCODING_RM)
1117 ENCODING("VR64", ENCODING_RM)
1118 ENCODING("VR256", ENCODING_RM)
1119 errs() << "Unhandled R/M register encoding " << s << "\n";
1120 llvm_unreachable("Unhandled R/M register encoding");
1123 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1124 (const std::string &s,
1125 bool hasOpSizePrefix) {
1126 ENCODING("GR16", ENCODING_REG)
1127 ENCODING("GR32", ENCODING_REG)
1128 ENCODING("GR64", ENCODING_REG)
1129 ENCODING("GR8", ENCODING_REG)
1130 ENCODING("VR128", ENCODING_REG)
1131 ENCODING("FR64", ENCODING_REG)
1132 ENCODING("FR32", ENCODING_REG)
1133 ENCODING("VR64", ENCODING_REG)
1134 ENCODING("SEGMENT_REG", ENCODING_REG)
1135 ENCODING("DEBUG_REG", ENCODING_REG)
1136 ENCODING("CONTROL_REG", ENCODING_REG)
1137 ENCODING("VR256", ENCODING_REG)
1138 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1139 llvm_unreachable("Unhandled reg/opcode register encoding");
1142 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1143 (const std::string &s,
1144 bool hasOpSizePrefix) {
1145 ENCODING("FR32", ENCODING_VVVV)
1146 ENCODING("FR64", ENCODING_VVVV)
1147 ENCODING("VR128", ENCODING_VVVV)
1148 ENCODING("VR256", ENCODING_VVVV)
1149 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1150 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1153 OperandEncoding RecognizableInstr::memoryEncodingFromString
1154 (const std::string &s,
1155 bool hasOpSizePrefix) {
1156 ENCODING("i16mem", ENCODING_RM)
1157 ENCODING("i32mem", ENCODING_RM)
1158 ENCODING("i64mem", ENCODING_RM)
1159 ENCODING("i8mem", ENCODING_RM)
1160 ENCODING("ssmem", ENCODING_RM)
1161 ENCODING("sdmem", ENCODING_RM)
1162 ENCODING("f128mem", ENCODING_RM)
1163 ENCODING("f256mem", ENCODING_RM)
1164 ENCODING("f64mem", ENCODING_RM)
1165 ENCODING("f32mem", ENCODING_RM)
1166 ENCODING("i128mem", ENCODING_RM)
1167 ENCODING("i256mem", ENCODING_RM)
1168 ENCODING("f80mem", ENCODING_RM)
1169 ENCODING("lea32mem", ENCODING_RM)
1170 ENCODING("lea64_32mem", ENCODING_RM)
1171 ENCODING("lea64mem", ENCODING_RM)
1172 ENCODING("opaque32mem", ENCODING_RM)
1173 ENCODING("opaque48mem", ENCODING_RM)
1174 ENCODING("opaque80mem", ENCODING_RM)
1175 ENCODING("opaque512mem", ENCODING_RM)
1176 errs() << "Unhandled memory encoding " << s << "\n";
1177 llvm_unreachable("Unhandled memory encoding");
1180 OperandEncoding RecognizableInstr::relocationEncodingFromString
1181 (const std::string &s,
1182 bool hasOpSizePrefix) {
1183 if(!hasOpSizePrefix) {
1184 // For instructions without an OpSize prefix, a declared 16-bit register or
1185 // immediate encoding is special.
1186 ENCODING("i16imm", ENCODING_IW)
1188 ENCODING("i16imm", ENCODING_Iv)
1189 ENCODING("i16i8imm", ENCODING_IB)
1190 ENCODING("i32imm", ENCODING_Iv)
1191 ENCODING("i32i8imm", ENCODING_IB)
1192 ENCODING("i64i32imm", ENCODING_ID)
1193 ENCODING("i64i8imm", ENCODING_IB)
1194 ENCODING("i8imm", ENCODING_IB)
1195 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1196 ENCODING("i16imm_pcrel", ENCODING_IW)
1197 ENCODING("i32imm_pcrel", ENCODING_ID)
1198 ENCODING("brtarget", ENCODING_Iv)
1199 ENCODING("brtarget8", ENCODING_IB)
1200 ENCODING("i64imm", ENCODING_IO)
1201 ENCODING("offset8", ENCODING_Ia)
1202 ENCODING("offset16", ENCODING_Ia)
1203 ENCODING("offset32", ENCODING_Ia)
1204 ENCODING("offset64", ENCODING_Ia)
1205 errs() << "Unhandled relocation encoding " << s << "\n";
1206 llvm_unreachable("Unhandled relocation encoding");
1209 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1210 (const std::string &s,
1211 bool hasOpSizePrefix) {
1212 ENCODING("RST", ENCODING_I)
1213 ENCODING("GR32", ENCODING_Rv)
1214 ENCODING("GR64", ENCODING_RO)
1215 ENCODING("GR16", ENCODING_Rv)
1216 ENCODING("GR8", ENCODING_RB)
1217 ENCODING("GR16_NOAX", ENCODING_Rv)
1218 ENCODING("GR32_NOAX", ENCODING_Rv)
1219 ENCODING("GR64_NOAX", ENCODING_RO)
1220 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1221 llvm_unreachable("Unhandled opcode modifier encoding");