1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
39 // A clone of X86 since we can't depend on something that is generated.
49 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
50 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
51 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
52 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55 #define MAP(from, to) MRM_##from = to,
64 D8 = 3, D9 = 4, DA = 5, DB = 6,
65 DC = 7, DD = 8, DE = 9, DF = 10,
68 P_0F_AE = 16, P_0F_01 = 17
72 // If rows are added to the opcode extension tables, then corresponding entries
73 // must be added here.
75 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
76 // that byte to ONE_BYTE_EXTENSION_TABLES.
78 // If the row corresponds to two bytes where the first is 0f, add an entry for
79 // the second byte to TWO_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to some other set of bytes, you will need to modify
82 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
83 // to the X86 TD files, except in two cases: if the first two bytes of such a
84 // new combination are 0f 38 or 0f 3a, you just have to add maps called
85 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
86 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
87 // in RecognizableInstr::emitDecodePath().
89 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(d1) \
101 EXTENSION_TABLE(d2) \
102 EXTENSION_TABLE(d3) \
103 EXTENSION_TABLE(f6) \
104 EXTENSION_TABLE(f7) \
105 EXTENSION_TABLE(fe) \
108 #define TWO_BYTE_EXTENSION_TABLES \
109 EXTENSION_TABLE(00) \
110 EXTENSION_TABLE(01) \
111 EXTENSION_TABLE(18) \
112 EXTENSION_TABLE(71) \
113 EXTENSION_TABLE(72) \
114 EXTENSION_TABLE(73) \
115 EXTENSION_TABLE(ae) \
116 EXTENSION_TABLE(b9) \
117 EXTENSION_TABLE(ba) \
120 using namespace X86Disassembler;
122 /// needsModRMForDecode - Indicates whether a particular instruction requires a
123 /// ModR/M byte for the instruction to be properly decoded. For example, a
124 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127 /// @param form - The form of the instruction.
128 /// @return - true if the form implies that a ModR/M byte is required, false
130 static bool needsModRMForDecode(uint8_t form) {
131 if (form == X86Local::MRMDestReg ||
132 form == X86Local::MRMDestMem ||
133 form == X86Local::MRMSrcReg ||
134 form == X86Local::MRMSrcMem ||
135 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
136 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
142 /// isRegFormat - Indicates whether a particular form requires the Mod field of
143 /// the ModR/M byte to be 0b11.
145 /// @param form - The form of the instruction.
146 /// @return - true if the form implies that Mod must be 0b11, false
148 static bool isRegFormat(uint8_t form) {
149 if (form == X86Local::MRMDestReg ||
150 form == X86Local::MRMSrcReg ||
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
157 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
158 /// Useful for switch statements and the like.
160 /// @param init - A reference to the BitsInit to be decoded.
161 /// @return - The field, with the first bit in the BitsInit as the lowest
163 static uint8_t byteFromBitsInit(BitsInit &init) {
164 int width = init.getNumBits();
166 assert(width <= 8 && "Field is too large for uint8_t!");
173 for (index = 0; index < width; index++) {
174 if (static_cast<BitInit*>(init.getBit(index))->getValue())
183 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
184 /// name of the field.
186 /// @param rec - The record from which to extract the value.
187 /// @param name - The name of the field in the record.
188 /// @return - The field, as translated by byteFromBitsInit().
189 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
190 BitsInit* bits = rec->getValueAsBitsInit(name);
191 return byteFromBitsInit(*bits);
194 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
195 const CodeGenInstruction &insn,
200 Name = Rec->getName();
201 Spec = &tables.specForUID(UID);
203 if (!Rec->isSubClassOf("X86Inst")) {
204 ShouldBeEmitted = false;
208 Prefix = byteFromRec(Rec, "Prefix");
209 Opcode = byteFromRec(Rec, "Opcode");
210 Form = byteFromRec(Rec, "FormBits");
211 SegOvr = byteFromRec(Rec, "SegOvrBits");
213 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
214 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
215 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
216 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
217 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
219 Name = Rec->getName();
220 AsmString = Rec->getValueAsString("AsmString");
222 Operands = &insn.OperandList;
224 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);
225 HasFROperands = false;
227 ShouldBeEmitted = true;
230 void RecognizableInstr::processInstr(DisassemblerTables &tables,
231 const CodeGenInstruction &insn,
234 // Ignore "asm parser only" instructions.
235 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
238 RecognizableInstr recogInstr(tables, insn, uid);
240 recogInstr.emitInstructionSpecifier(tables);
242 if (recogInstr.shouldBeEmitted())
243 recogInstr.emitDecodePath(tables);
246 InstructionContext RecognizableInstr::insnContext() const {
247 InstructionContext insnContext;
249 if (Name.find("64") != Name.npos || HasREX_WPrefix) {
250 if (HasREX_WPrefix && HasOpSizePrefix)
251 insnContext = IC_64BIT_REXW_OPSIZE;
252 else if (HasOpSizePrefix)
253 insnContext = IC_64BIT_OPSIZE;
254 else if (HasREX_WPrefix && Prefix == X86Local::XS)
255 insnContext = IC_64BIT_REXW_XS;
256 else if (HasREX_WPrefix && Prefix == X86Local::XD)
257 insnContext = IC_64BIT_REXW_XD;
258 else if (Prefix == X86Local::XD)
259 insnContext = IC_64BIT_XD;
260 else if (Prefix == X86Local::XS)
261 insnContext = IC_64BIT_XS;
262 else if (HasREX_WPrefix)
263 insnContext = IC_64BIT_REXW;
265 insnContext = IC_64BIT;
268 insnContext = IC_OPSIZE;
269 else if (Prefix == X86Local::XD)
271 else if (Prefix == X86Local::XS)
280 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
281 // Filter out intrinsics
283 if (!Rec->isSubClassOf("X86Inst"))
284 return FILTER_STRONG;
286 if (Form == X86Local::Pseudo ||
288 return FILTER_STRONG;
290 if (Form == X86Local::MRMInitReg)
291 return FILTER_STRONG;
294 // Filter out instructions with a LOCK prefix;
295 // prefer forms that do not have the prefix
299 // Filter out artificial instructions
301 if (Name.find("TAILJMP") != Name.npos ||
302 Name.find("_Int") != Name.npos ||
303 Name.find("_int") != Name.npos ||
304 Name.find("Int_") != Name.npos ||
305 Name.find("_NOREX") != Name.npos ||
306 Name.find("_TC") != Name.npos ||
307 Name.find("EH_RETURN") != Name.npos ||
308 Name.find("V_SET") != Name.npos ||
309 Name.find("LOCK_") != Name.npos ||
310 Name.find("WIN") != Name.npos)
311 return FILTER_STRONG;
315 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
317 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
320 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
322 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
324 if (Name.find("Fs") != Name.npos)
326 if (Name == "MOVLPDrr" ||
327 Name == "MOVLPSrr" ||
333 Name == "MOVSX16rm8" ||
334 Name == "MOVSX16rr8" ||
335 Name == "MOVZX16rm8" ||
336 Name == "MOVZX16rr8" ||
337 Name == "PUSH32i16" ||
338 Name == "PUSH64i16" ||
339 Name == "MOVPQI2QImr" ||
344 Name == "MMX_MOVD64rrv164" ||
345 Name == "CRC32m16" ||
346 Name == "MOV64ri64i32" ||
350 // Filter out instructions with segment override prefixes.
351 // They're too messy to handle now and we'll special case them if needed.
354 return FILTER_STRONG;
356 // Filter out instructions that can't be printed.
358 if (AsmString.size() == 0)
359 return FILTER_STRONG;
361 // Filter out instructions with subreg operands.
363 if (AsmString.find("subreg") != AsmString.npos)
364 return FILTER_STRONG;
366 if (HasFROperands && Name.find("MOV") != Name.npos &&
367 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
368 (Name.find("to") != Name.npos)))
371 return FILTER_NORMAL;
374 void RecognizableInstr::handleOperand(
376 unsigned &operandIndex,
377 unsigned &physicalOperandIndex,
378 unsigned &numPhysicalOperands,
379 unsigned *operandMapping,
380 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
382 if (physicalOperandIndex >= numPhysicalOperands)
385 assert(physicalOperandIndex < numPhysicalOperands);
388 while (operandMapping[operandIndex] != operandIndex) {
389 Spec->operands[operandIndex].encoding = ENCODING_DUP;
390 Spec->operands[operandIndex].type =
391 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
395 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
397 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
399 Spec->operands[operandIndex].type = typeFromString(typeName,
405 ++physicalOperandIndex;
408 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
411 if (!Rec->isSubClassOf("X86Inst"))
416 Spec->filtered = true;
419 ShouldBeEmitted = false;
425 Spec->insnContext = insnContext();
427 const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
429 unsigned operandIndex;
430 unsigned numOperands = OperandList.size();
431 unsigned numPhysicalOperands = 0;
433 // operandMapping maps from operands in OperandList to their originals.
434 // If operandMapping[i] != i, then the entry is a duplicate.
435 unsigned operandMapping[X86_MAX_OPERANDS];
437 bool hasFROperands = false;
439 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
441 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
442 if (OperandList[operandIndex].Constraints.size()) {
443 const CodeGenInstruction::ConstraintInfo &Constraint =
444 OperandList[operandIndex].Constraints[0];
445 if (Constraint.isTied()) {
446 operandMapping[operandIndex] = Constraint.getTiedOperand();
448 ++numPhysicalOperands;
449 operandMapping[operandIndex] = operandIndex;
452 ++numPhysicalOperands;
453 operandMapping[operandIndex] = operandIndex;
456 const std::string &recName = OperandList[operandIndex].Rec->getName();
458 if (recName.find("FR") != recName.npos)
459 hasFROperands = true;
462 if (hasFROperands && Name.find("MOV") != Name.npos &&
463 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
464 (Name.find("to") != Name.npos)))
465 ShouldBeEmitted = false;
467 if (!ShouldBeEmitted)
470 #define HANDLE_OPERAND(class) \
471 handleOperand(false, \
473 physicalOperandIndex, \
474 numPhysicalOperands, \
476 class##EncodingFromString);
478 #define HANDLE_OPTIONAL(class) \
479 handleOperand(true, \
481 physicalOperandIndex, \
482 numPhysicalOperands, \
484 class##EncodingFromString);
486 // operandIndex should always be < numOperands
488 // physicalOperandIndex should always be < numPhysicalOperands
489 unsigned physicalOperandIndex = 0;
492 case X86Local::RawFrm:
493 // Operand 1 (optional) is an address or immediate.
494 // Operand 2 (optional) is an immediate.
495 assert(numPhysicalOperands <= 2 &&
496 "Unexpected number of operands for RawFrm");
497 HANDLE_OPTIONAL(relocation)
498 HANDLE_OPTIONAL(immediate)
500 case X86Local::AddRegFrm:
501 // Operand 1 is added to the opcode.
502 // Operand 2 (optional) is an address.
503 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
504 "Unexpected number of operands for AddRegFrm");
505 HANDLE_OPERAND(opcodeModifier)
506 HANDLE_OPTIONAL(relocation)
508 case X86Local::MRMDestReg:
509 // Operand 1 is a register operand in the R/M field.
510 // Operand 2 is a register operand in the Reg/Opcode field.
511 // Operand 3 (optional) is an immediate.
512 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
513 "Unexpected number of operands for MRMDestRegFrm");
514 HANDLE_OPERAND(rmRegister)
515 HANDLE_OPERAND(roRegister)
516 HANDLE_OPTIONAL(immediate)
518 case X86Local::MRMDestMem:
519 // Operand 1 is a memory operand (possibly SIB-extended)
520 // Operand 2 is a register operand in the Reg/Opcode field.
521 // Operand 3 (optional) is an immediate.
522 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
523 "Unexpected number of operands for MRMDestMemFrm");
524 HANDLE_OPERAND(memory)
525 HANDLE_OPERAND(roRegister)
526 HANDLE_OPTIONAL(immediate)
528 case X86Local::MRMSrcReg:
529 // Operand 1 is a register operand in the Reg/Opcode field.
530 // Operand 2 is a register operand in the R/M field.
531 // Operand 3 (optional) is an immediate.
532 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
533 "Unexpected number of operands for MRMSrcRegFrm");
534 HANDLE_OPERAND(roRegister)
535 HANDLE_OPERAND(rmRegister)
538 // FIXME: encoding of registers in AVX is in 1's complement form.
539 HANDLE_OPTIONAL(rmRegister)
541 HANDLE_OPTIONAL(immediate)
543 case X86Local::MRMSrcMem:
544 // Operand 1 is a register operand in the Reg/Opcode field.
545 // Operand 2 is a memory operand (possibly SIB-extended)
546 // Operand 3 (optional) is an immediate.
547 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
548 "Unexpected number of operands for MRMSrcMemFrm");
549 HANDLE_OPERAND(roRegister)
550 HANDLE_OPERAND(memory)
551 HANDLE_OPTIONAL(immediate)
553 case X86Local::MRM0r:
554 case X86Local::MRM1r:
555 case X86Local::MRM2r:
556 case X86Local::MRM3r:
557 case X86Local::MRM4r:
558 case X86Local::MRM5r:
559 case X86Local::MRM6r:
560 case X86Local::MRM7r:
561 // Operand 1 is a register operand in the R/M field.
562 // Operand 2 (optional) is an immediate or relocation.
563 assert(numPhysicalOperands <= 2 &&
564 "Unexpected number of operands for MRMnRFrm");
565 HANDLE_OPTIONAL(rmRegister)
566 HANDLE_OPTIONAL(relocation)
568 case X86Local::MRM0m:
569 case X86Local::MRM1m:
570 case X86Local::MRM2m:
571 case X86Local::MRM3m:
572 case X86Local::MRM4m:
573 case X86Local::MRM5m:
574 case X86Local::MRM6m:
575 case X86Local::MRM7m:
576 // Operand 1 is a memory operand (possibly SIB-extended)
577 // Operand 2 (optional) is an immediate or relocation.
578 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
579 "Unexpected number of operands for MRMnMFrm");
580 HANDLE_OPERAND(memory)
581 HANDLE_OPTIONAL(relocation)
583 case X86Local::MRMInitReg:
588 #undef HANDLE_OPERAND
589 #undef HANDLE_OPTIONAL
592 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
593 // Special cases where the LLVM tables are not complete
595 #define MAP(from, to) \
596 case X86Local::MRM_##from: \
597 filter = new ExactFilter(0x##from); \
600 OpcodeType opcodeType = (OpcodeType)-1;
602 ModRMFilter* filter = NULL;
603 uint8_t opcodeToSet = 0;
606 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
610 opcodeType = TWOBYTE;
614 if (needsModRMForDecode(Form))
615 filter = new ModFilter(isRegFormat(Form));
617 filter = new DumbFilter();
619 #define EXTENSION_TABLE(n) case 0x##n:
620 TWO_BYTE_EXTENSION_TABLES
621 #undef EXTENSION_TABLE
624 llvm_unreachable("Unhandled two-byte extended opcode");
625 case X86Local::MRM0r:
626 case X86Local::MRM1r:
627 case X86Local::MRM2r:
628 case X86Local::MRM3r:
629 case X86Local::MRM4r:
630 case X86Local::MRM5r:
631 case X86Local::MRM6r:
632 case X86Local::MRM7r:
633 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
635 case X86Local::MRM0m:
636 case X86Local::MRM1m:
637 case X86Local::MRM2m:
638 case X86Local::MRM3m:
639 case X86Local::MRM4m:
640 case X86Local::MRM5m:
641 case X86Local::MRM6m:
642 case X86Local::MRM7m:
643 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
649 opcodeToSet = Opcode;
652 opcodeType = THREEBYTE_38;
653 if (needsModRMForDecode(Form))
654 filter = new ModFilter(isRegFormat(Form));
656 filter = new DumbFilter();
657 opcodeToSet = Opcode;
660 opcodeType = THREEBYTE_3A;
661 if (needsModRMForDecode(Form))
662 filter = new ModFilter(isRegFormat(Form));
664 filter = new DumbFilter();
665 opcodeToSet = Opcode;
675 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
676 opcodeType = ONEBYTE;
677 if (Form == X86Local::AddRegFrm) {
678 Spec->modifierType = MODIFIER_MODRM;
679 Spec->modifierBase = Opcode;
680 filter = new AddRegEscapeFilter(Opcode);
682 filter = new EscapeFilter(true, Opcode);
684 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
687 opcodeType = ONEBYTE;
689 #define EXTENSION_TABLE(n) case 0x##n:
690 ONE_BYTE_EXTENSION_TABLES
691 #undef EXTENSION_TABLE
694 llvm_unreachable("Fell through the cracks of a single-byte "
696 case X86Local::MRM0r:
697 case X86Local::MRM1r:
698 case X86Local::MRM2r:
699 case X86Local::MRM3r:
700 case X86Local::MRM4r:
701 case X86Local::MRM5r:
702 case X86Local::MRM6r:
703 case X86Local::MRM7r:
704 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
706 case X86Local::MRM0m:
707 case X86Local::MRM1m:
708 case X86Local::MRM2m:
709 case X86Local::MRM3m:
710 case X86Local::MRM4m:
711 case X86Local::MRM5m:
712 case X86Local::MRM6m:
713 case X86Local::MRM7m:
714 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
727 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
730 if (needsModRMForDecode(Form))
731 filter = new ModFilter(isRegFormat(Form));
733 filter = new DumbFilter();
736 opcodeToSet = Opcode;
739 assert(opcodeType != (OpcodeType)-1 &&
740 "Opcode type not set");
741 assert(filter && "Filter not set");
743 if (Form == X86Local::AddRegFrm) {
744 if(Spec->modifierType != MODIFIER_MODRM) {
745 assert(opcodeToSet < 0xf9 &&
746 "Not enough room for all ADDREG_FRM operands");
748 uint8_t currentOpcode;
750 for (currentOpcode = opcodeToSet;
751 currentOpcode < opcodeToSet + 8;
753 tables.setTableFields(opcodeType,
759 Spec->modifierType = MODIFIER_OPCODE;
760 Spec->modifierBase = opcodeToSet;
762 // modifierBase was set where MODIFIER_MODRM was set
763 tables.setTableFields(opcodeType,
770 tables.setTableFields(opcodeType,
776 Spec->modifierType = MODIFIER_NONE;
777 Spec->modifierBase = opcodeToSet;
785 #define TYPE(str, type) if (s == str) return type;
786 OperandType RecognizableInstr::typeFromString(const std::string &s,
789 bool hasOpSizePrefix) {
791 // For SSE instructions, we ignore the OpSize prefix and force operand
793 TYPE("GR16", TYPE_R16)
794 TYPE("GR32", TYPE_R32)
795 TYPE("GR64", TYPE_R64)
798 // For instructions with a REX_W prefix, a declared 32-bit register encoding
800 TYPE("GR32", TYPE_R32)
802 if(!hasOpSizePrefix) {
803 // For instructions without an OpSize prefix, a declared 16-bit register or
804 // immediate encoding is special.
805 TYPE("GR16", TYPE_R16)
806 TYPE("i16imm", TYPE_IMM16)
808 TYPE("i16mem", TYPE_Mv)
809 TYPE("i16imm", TYPE_IMMv)
810 TYPE("i16i8imm", TYPE_IMMv)
811 TYPE("GR16", TYPE_Rv)
812 TYPE("i32mem", TYPE_Mv)
813 TYPE("i32imm", TYPE_IMMv)
814 TYPE("i32i8imm", TYPE_IMM32)
815 TYPE("GR32", TYPE_Rv)
816 TYPE("i64mem", TYPE_Mv)
817 TYPE("i64i32imm", TYPE_IMM64)
818 TYPE("i64i8imm", TYPE_IMM64)
819 TYPE("GR64", TYPE_R64)
820 TYPE("i8mem", TYPE_M8)
821 TYPE("i8imm", TYPE_IMM8)
823 TYPE("VR128", TYPE_XMM128)
824 TYPE("f128mem", TYPE_M128)
825 TYPE("FR64", TYPE_XMM64)
826 TYPE("f64mem", TYPE_M64FP)
827 TYPE("FR32", TYPE_XMM32)
828 TYPE("f32mem", TYPE_M32FP)
830 TYPE("i128mem", TYPE_M128)
831 TYPE("i64i32imm_pcrel", TYPE_REL64)
832 TYPE("i32imm_pcrel", TYPE_REL32)
833 TYPE("SSECC", TYPE_IMM3)
834 TYPE("brtarget", TYPE_RELv)
835 TYPE("brtarget8", TYPE_REL8)
836 TYPE("f80mem", TYPE_M80FP)
837 TYPE("lea32mem", TYPE_LEA)
838 TYPE("lea64_32mem", TYPE_LEA)
839 TYPE("lea64mem", TYPE_LEA)
840 TYPE("VR64", TYPE_MM64)
841 TYPE("i64imm", TYPE_IMMv)
842 TYPE("opaque32mem", TYPE_M1616)
843 TYPE("opaque48mem", TYPE_M1632)
844 TYPE("opaque80mem", TYPE_M1664)
845 TYPE("opaque512mem", TYPE_M512)
846 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
847 TYPE("DEBUG_REG", TYPE_DEBUGREG)
848 TYPE("CONTROL_REG", TYPE_CONTROLREG)
849 TYPE("offset8", TYPE_MOFFS8)
850 TYPE("offset16", TYPE_MOFFS16)
851 TYPE("offset32", TYPE_MOFFS32)
852 TYPE("offset64", TYPE_MOFFS64)
853 errs() << "Unhandled type string " << s << "\n";
854 llvm_unreachable("Unhandled type string");
858 #define ENCODING(str, encoding) if (s == str) return encoding;
859 OperandEncoding RecognizableInstr::immediateEncodingFromString
860 (const std::string &s,
861 bool hasOpSizePrefix) {
862 if(!hasOpSizePrefix) {
863 // For instructions without an OpSize prefix, a declared 16-bit register or
864 // immediate encoding is special.
865 ENCODING("i16imm", ENCODING_IW)
867 ENCODING("i32i8imm", ENCODING_IB)
868 ENCODING("SSECC", ENCODING_IB)
869 ENCODING("i16imm", ENCODING_Iv)
870 ENCODING("i16i8imm", ENCODING_IB)
871 ENCODING("i32imm", ENCODING_Iv)
872 ENCODING("i64i32imm", ENCODING_ID)
873 ENCODING("i64i8imm", ENCODING_IB)
874 ENCODING("i8imm", ENCODING_IB)
875 errs() << "Unhandled immediate encoding " << s << "\n";
876 llvm_unreachable("Unhandled immediate encoding");
879 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
880 (const std::string &s,
881 bool hasOpSizePrefix) {
882 ENCODING("GR16", ENCODING_RM)
883 ENCODING("GR32", ENCODING_RM)
884 ENCODING("GR64", ENCODING_RM)
885 ENCODING("GR8", ENCODING_RM)
886 ENCODING("VR128", ENCODING_RM)
887 ENCODING("FR64", ENCODING_RM)
888 ENCODING("FR32", ENCODING_RM)
889 ENCODING("VR64", ENCODING_RM)
890 errs() << "Unhandled R/M register encoding " << s << "\n";
891 llvm_unreachable("Unhandled R/M register encoding");
894 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
895 (const std::string &s,
896 bool hasOpSizePrefix) {
897 ENCODING("GR16", ENCODING_REG)
898 ENCODING("GR32", ENCODING_REG)
899 ENCODING("GR64", ENCODING_REG)
900 ENCODING("GR8", ENCODING_REG)
901 ENCODING("VR128", ENCODING_REG)
902 ENCODING("FR64", ENCODING_REG)
903 ENCODING("FR32", ENCODING_REG)
904 ENCODING("VR64", ENCODING_REG)
905 ENCODING("SEGMENT_REG", ENCODING_REG)
906 ENCODING("DEBUG_REG", ENCODING_REG)
907 ENCODING("CONTROL_REG", ENCODING_REG)
908 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
909 llvm_unreachable("Unhandled reg/opcode register encoding");
912 OperandEncoding RecognizableInstr::memoryEncodingFromString
913 (const std::string &s,
914 bool hasOpSizePrefix) {
915 ENCODING("i16mem", ENCODING_RM)
916 ENCODING("i32mem", ENCODING_RM)
917 ENCODING("i64mem", ENCODING_RM)
918 ENCODING("i8mem", ENCODING_RM)
919 ENCODING("f128mem", ENCODING_RM)
920 ENCODING("f64mem", ENCODING_RM)
921 ENCODING("f32mem", ENCODING_RM)
922 ENCODING("i128mem", ENCODING_RM)
923 ENCODING("f80mem", ENCODING_RM)
924 ENCODING("lea32mem", ENCODING_RM)
925 ENCODING("lea64_32mem", ENCODING_RM)
926 ENCODING("lea64mem", ENCODING_RM)
927 ENCODING("opaque32mem", ENCODING_RM)
928 ENCODING("opaque48mem", ENCODING_RM)
929 ENCODING("opaque80mem", ENCODING_RM)
930 ENCODING("opaque512mem", ENCODING_RM)
931 errs() << "Unhandled memory encoding " << s << "\n";
932 llvm_unreachable("Unhandled memory encoding");
935 OperandEncoding RecognizableInstr::relocationEncodingFromString
936 (const std::string &s,
937 bool hasOpSizePrefix) {
938 if(!hasOpSizePrefix) {
939 // For instructions without an OpSize prefix, a declared 16-bit register or
940 // immediate encoding is special.
941 ENCODING("i16imm", ENCODING_IW)
943 ENCODING("i16imm", ENCODING_Iv)
944 ENCODING("i16i8imm", ENCODING_IB)
945 ENCODING("i32imm", ENCODING_Iv)
946 ENCODING("i32i8imm", ENCODING_IB)
947 ENCODING("i64i32imm", ENCODING_ID)
948 ENCODING("i64i8imm", ENCODING_IB)
949 ENCODING("i8imm", ENCODING_IB)
950 ENCODING("i64i32imm_pcrel", ENCODING_ID)
951 ENCODING("i32imm_pcrel", ENCODING_ID)
952 ENCODING("brtarget", ENCODING_Iv)
953 ENCODING("brtarget8", ENCODING_IB)
954 ENCODING("i64imm", ENCODING_IO)
955 ENCODING("offset8", ENCODING_Ia)
956 ENCODING("offset16", ENCODING_Ia)
957 ENCODING("offset32", ENCODING_Ia)
958 ENCODING("offset64", ENCODING_Ia)
959 errs() << "Unhandled relocation encoding " << s << "\n";
960 llvm_unreachable("Unhandled relocation encoding");
963 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
964 (const std::string &s,
965 bool hasOpSizePrefix) {
966 ENCODING("RST", ENCODING_I)
967 ENCODING("GR32", ENCODING_Rv)
968 ENCODING("GR64", ENCODING_RO)
969 ENCODING("GR16", ENCODING_Rv)
970 ENCODING("GR8", ENCODING_RB)
971 errs() << "Unhandled opcode modifier encoding " << s << "\n";
972 llvm_unreachable("Unhandled opcode modifier encoding");