1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
66 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
67 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
68 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
69 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
72 #define MAP(from, to) MRM_##from = to,
81 D8 = 3, D9 = 4, DA = 5, DB = 6,
82 DC = 7, DD = 8, DE = 9, DF = 10,
85 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
86 XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25
90 // If rows are added to the opcode extension tables, then corresponding entries
91 // must be added here.
93 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
94 // that byte to ONE_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to two bytes where the first is 0f, add an entry for
97 // the second byte to TWO_BYTE_EXTENSION_TABLES.
99 // If the row corresponds to some other set of bytes, you will need to modify
100 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
101 // to the X86 TD files, except in two cases: if the first two bytes of such a
102 // new combination are 0f 38 or 0f 3a, you just have to add maps called
103 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
104 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
105 // in RecognizableInstr::emitDecodePath().
107 #define ONE_BYTE_EXTENSION_TABLES \
108 EXTENSION_TABLE(80) \
109 EXTENSION_TABLE(81) \
110 EXTENSION_TABLE(82) \
111 EXTENSION_TABLE(83) \
112 EXTENSION_TABLE(8f) \
113 EXTENSION_TABLE(c0) \
114 EXTENSION_TABLE(c1) \
115 EXTENSION_TABLE(c6) \
116 EXTENSION_TABLE(c7) \
117 EXTENSION_TABLE(d0) \
118 EXTENSION_TABLE(d1) \
119 EXTENSION_TABLE(d2) \
120 EXTENSION_TABLE(d3) \
121 EXTENSION_TABLE(f6) \
122 EXTENSION_TABLE(f7) \
123 EXTENSION_TABLE(fe) \
126 #define TWO_BYTE_EXTENSION_TABLES \
127 EXTENSION_TABLE(00) \
128 EXTENSION_TABLE(01) \
129 EXTENSION_TABLE(0d) \
130 EXTENSION_TABLE(18) \
131 EXTENSION_TABLE(71) \
132 EXTENSION_TABLE(72) \
133 EXTENSION_TABLE(73) \
134 EXTENSION_TABLE(ae) \
135 EXTENSION_TABLE(ba) \
138 #define THREE_BYTE_38_EXTENSION_TABLES \
141 #define XOP9_MAP_EXTENSION_TABLES \
142 EXTENSION_TABLE(01) \
145 using namespace X86Disassembler;
147 /// needsModRMForDecode - Indicates whether a particular instruction requires a
148 /// ModR/M byte for the instruction to be properly decoded. For example, a
149 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
152 /// @param form - The form of the instruction.
153 /// @return - true if the form implies that a ModR/M byte is required, false
155 static bool needsModRMForDecode(uint8_t form) {
156 if (form == X86Local::MRMDestReg ||
157 form == X86Local::MRMDestMem ||
158 form == X86Local::MRMSrcReg ||
159 form == X86Local::MRMSrcMem ||
160 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
161 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
167 /// isRegFormat - Indicates whether a particular form requires the Mod field of
168 /// the ModR/M byte to be 0b11.
170 /// @param form - The form of the instruction.
171 /// @return - true if the form implies that Mod must be 0b11, false
173 static bool isRegFormat(uint8_t form) {
174 if (form == X86Local::MRMDestReg ||
175 form == X86Local::MRMSrcReg ||
176 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
182 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
183 /// Useful for switch statements and the like.
185 /// @param init - A reference to the BitsInit to be decoded.
186 /// @return - The field, with the first bit in the BitsInit as the lowest
188 static uint8_t byteFromBitsInit(BitsInit &init) {
189 int width = init.getNumBits();
191 assert(width <= 8 && "Field is too large for uint8_t!");
198 for (index = 0; index < width; index++) {
199 if (static_cast<BitInit*>(init.getBit(index))->getValue())
208 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
209 /// name of the field.
211 /// @param rec - The record from which to extract the value.
212 /// @param name - The name of the field in the record.
213 /// @return - The field, as translated by byteFromBitsInit().
214 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
215 BitsInit* bits = rec->getValueAsBitsInit(name);
216 return byteFromBitsInit(*bits);
219 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
220 const CodeGenInstruction &insn,
225 Name = Rec->getName();
226 Spec = &tables.specForUID(UID);
228 if (!Rec->isSubClassOf("X86Inst")) {
229 ShouldBeEmitted = false;
233 Prefix = byteFromRec(Rec, "Prefix");
234 Opcode = byteFromRec(Rec, "Opcode");
235 Form = byteFromRec(Rec, "FormBits");
237 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
238 HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
239 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
240 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
241 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
242 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
243 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
244 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
245 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
246 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
247 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
248 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
249 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
250 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
251 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
252 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
253 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
254 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
256 Name = Rec->getName();
257 AsmString = Rec->getValueAsString("AsmString");
259 Operands = &insn.Operands.OperandList;
261 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
263 // Check for 64-bit inst which does not require REX
266 // FIXME: Is there some better way to check for In64BitMode?
267 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
268 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
269 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
270 Predicates[i]->getName().find("In32Bit") != Name.npos) {
274 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
280 ShouldBeEmitted = true;
283 void RecognizableInstr::processInstr(DisassemblerTables &tables,
284 const CodeGenInstruction &insn,
287 // Ignore "asm parser only" instructions.
288 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
291 RecognizableInstr recogInstr(tables, insn, uid);
293 recogInstr.emitInstructionSpecifier();
295 if (recogInstr.shouldBeEmitted())
296 recogInstr.emitDecodePath(tables);
299 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
300 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
301 (HasEVEX_KZ ? n##_KZ : \
302 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
304 InstructionContext RecognizableInstr::insnContext() const {
305 InstructionContext insnContext;
308 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
309 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
310 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
313 if (HasVEX_LPrefix && HasVEX_WPrefix) {
314 if (HasOpSizePrefix || Prefix == X86Local::PD)
315 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
316 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
317 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
318 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
319 Prefix == X86Local::TAXD)
320 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
322 insnContext = EVEX_KB(IC_EVEX_L_W);
323 } else if (HasVEX_LPrefix) {
325 if (HasOpSizePrefix || Prefix == X86Local::PD ||
326 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
327 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
328 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
329 insnContext = EVEX_KB(IC_EVEX_L_XS);
330 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
331 Prefix == X86Local::TAXD)
332 insnContext = EVEX_KB(IC_EVEX_L_XD);
334 insnContext = EVEX_KB(IC_EVEX_L);
336 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
338 if (HasOpSizePrefix || Prefix == X86Local::PD ||
339 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
340 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
341 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
343 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
344 Prefix == X86Local::TAXD)
345 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
347 insnContext = EVEX_KB(IC_EVEX_L2_W);
348 } else if (HasEVEX_L2Prefix) {
350 if (HasOpSizePrefix || Prefix == X86Local::PD ||
351 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
352 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
353 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
354 Prefix == X86Local::TAXD)
355 insnContext = EVEX_KB(IC_EVEX_L2_XD);
356 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
357 insnContext = EVEX_KB(IC_EVEX_L2_XS);
359 insnContext = EVEX_KB(IC_EVEX_L2);
361 else if (HasVEX_WPrefix) {
363 if (HasOpSizePrefix || Prefix == X86Local::PD ||
364 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
365 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
366 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
367 insnContext = EVEX_KB(IC_EVEX_W_XS);
368 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
369 Prefix == X86Local::TAXD)
370 insnContext = EVEX_KB(IC_EVEX_W_XD);
372 insnContext = EVEX_KB(IC_EVEX_W);
375 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
376 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
377 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
378 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
379 Prefix == X86Local::TAXD)
380 insnContext = EVEX_KB(IC_EVEX_XD);
381 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
382 insnContext = EVEX_KB(IC_EVEX_XS);
384 insnContext = EVEX_KB(IC_EVEX);
386 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
387 if (HasVEX_LPrefix && HasVEX_WPrefix) {
388 if (HasOpSizePrefix || Prefix == X86Local::PD ||
389 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
390 insnContext = IC_VEX_L_W_OPSIZE;
391 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
392 insnContext = IC_VEX_L_W_XS;
393 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
394 Prefix == X86Local::TAXD)
395 insnContext = IC_VEX_L_W_XD;
397 insnContext = IC_VEX_L_W;
398 } else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
399 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
401 insnContext = IC_VEX_L_OPSIZE;
402 else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
403 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
405 insnContext = IC_VEX_W_OPSIZE;
406 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
407 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
408 insnContext = IC_VEX_OPSIZE;
409 else if (HasVEX_LPrefix &&
410 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
411 insnContext = IC_VEX_L_XS;
412 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
413 Prefix == X86Local::T8XD ||
414 Prefix == X86Local::TAXD))
415 insnContext = IC_VEX_L_XD;
416 else if (HasVEX_WPrefix &&
417 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
418 insnContext = IC_VEX_W_XS;
419 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
420 Prefix == X86Local::T8XD ||
421 Prefix == X86Local::TAXD))
422 insnContext = IC_VEX_W_XD;
423 else if (HasVEX_WPrefix)
424 insnContext = IC_VEX_W;
425 else if (HasVEX_LPrefix)
426 insnContext = IC_VEX_L;
427 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
428 Prefix == X86Local::TAXD)
429 insnContext = IC_VEX_XD;
430 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
431 insnContext = IC_VEX_XS;
433 insnContext = IC_VEX;
434 } else if (Is64Bit || HasREX_WPrefix) {
435 if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
436 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
437 insnContext = IC_64BIT_REXW_OPSIZE;
438 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
439 Prefix == X86Local::T8XD ||
440 Prefix == X86Local::TAXD))
441 insnContext = IC_64BIT_XD_OPSIZE;
442 else if (HasOpSizePrefix &&
443 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
444 insnContext = IC_64BIT_XS_OPSIZE;
445 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
446 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
447 insnContext = IC_64BIT_OPSIZE;
448 else if (HasAdSizePrefix)
449 insnContext = IC_64BIT_ADSIZE;
450 else if (HasREX_WPrefix &&
451 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
452 insnContext = IC_64BIT_REXW_XS;
453 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
454 Prefix == X86Local::T8XD ||
455 Prefix == X86Local::TAXD))
456 insnContext = IC_64BIT_REXW_XD;
457 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
458 Prefix == X86Local::TAXD)
459 insnContext = IC_64BIT_XD;
460 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
461 insnContext = IC_64BIT_XS;
462 else if (HasREX_WPrefix)
463 insnContext = IC_64BIT_REXW;
465 insnContext = IC_64BIT;
467 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
468 Prefix == X86Local::T8XD ||
469 Prefix == X86Local::TAXD))
470 insnContext = IC_XD_OPSIZE;
471 else if (HasOpSizePrefix &&
472 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
473 insnContext = IC_XS_OPSIZE;
474 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
475 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
476 insnContext = IC_OPSIZE;
477 else if (HasAdSizePrefix)
478 insnContext = IC_ADSIZE;
479 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
480 Prefix == X86Local::TAXD)
482 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
483 Prefix == X86Local::REP)
492 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
497 // Filter out intrinsics
499 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
501 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
502 return FILTER_STRONG;
505 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
506 // printed as a separate "instruction".
514 // Filter out instructions with a LOCK prefix;
515 // prefer forms that do not have the prefix
521 if (Name == "VMASKMOVDQU64")
524 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
525 // For now, just prefer the REP versions.
526 if (Name == "XACQUIRE_PREFIX" ||
527 Name == "XRELEASE_PREFIX")
530 return FILTER_NORMAL;
533 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
534 unsigned &physicalOperandIndex,
535 unsigned &numPhysicalOperands,
536 const unsigned *operandMapping,
537 OperandEncoding (*encodingFromString)
539 bool hasOpSizePrefix)) {
541 if (physicalOperandIndex >= numPhysicalOperands)
544 assert(physicalOperandIndex < numPhysicalOperands);
547 while (operandMapping[operandIndex] != operandIndex) {
548 Spec->operands[operandIndex].encoding = ENCODING_DUP;
549 Spec->operands[operandIndex].type =
550 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
554 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
556 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
558 Spec->operands[operandIndex].type = typeFromString(typeName,
564 ++physicalOperandIndex;
567 void RecognizableInstr::emitInstructionSpecifier() {
570 if (!ShouldBeEmitted)
575 Spec->filtered = true;
578 ShouldBeEmitted = false;
584 Spec->insnContext = insnContext();
586 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
588 unsigned numOperands = OperandList.size();
589 unsigned numPhysicalOperands = 0;
591 // operandMapping maps from operands in OperandList to their originals.
592 // If operandMapping[i] != i, then the entry is a duplicate.
593 unsigned operandMapping[X86_MAX_OPERANDS];
594 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
596 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
597 if (OperandList[operandIndex].Constraints.size()) {
598 const CGIOperandList::ConstraintInfo &Constraint =
599 OperandList[operandIndex].Constraints[0];
600 if (Constraint.isTied()) {
601 operandMapping[operandIndex] = operandIndex;
602 operandMapping[Constraint.getTiedOperand()] = operandIndex;
604 ++numPhysicalOperands;
605 operandMapping[operandIndex] = operandIndex;
608 ++numPhysicalOperands;
609 operandMapping[operandIndex] = operandIndex;
613 #define HANDLE_OPERAND(class) \
614 handleOperand(false, \
616 physicalOperandIndex, \
617 numPhysicalOperands, \
619 class##EncodingFromString);
621 #define HANDLE_OPTIONAL(class) \
622 handleOperand(true, \
624 physicalOperandIndex, \
625 numPhysicalOperands, \
627 class##EncodingFromString);
629 // operandIndex should always be < numOperands
630 unsigned operandIndex = 0;
631 // physicalOperandIndex should always be < numPhysicalOperands
632 unsigned physicalOperandIndex = 0;
635 default: llvm_unreachable("Unhandled form");
636 case X86Local::RawFrmSrc:
637 HANDLE_OPERAND(relocation);
639 case X86Local::RawFrmDst:
640 HANDLE_OPERAND(relocation);
642 case X86Local::RawFrmDstSrc:
643 HANDLE_OPERAND(relocation);
644 HANDLE_OPERAND(relocation);
646 case X86Local::RawFrm:
647 // Operand 1 (optional) is an address or immediate.
648 // Operand 2 (optional) is an immediate.
649 assert(numPhysicalOperands <= 2 &&
650 "Unexpected number of operands for RawFrm");
651 HANDLE_OPTIONAL(relocation)
652 HANDLE_OPTIONAL(immediate)
654 case X86Local::RawFrmMemOffs:
655 // Operand 1 is an address.
656 HANDLE_OPERAND(relocation);
658 case X86Local::AddRegFrm:
659 // Operand 1 is added to the opcode.
660 // Operand 2 (optional) is an address.
661 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
662 "Unexpected number of operands for AddRegFrm");
663 HANDLE_OPERAND(opcodeModifier)
664 HANDLE_OPTIONAL(relocation)
666 case X86Local::MRMDestReg:
667 // Operand 1 is a register operand in the R/M field.
668 // Operand 2 is a register operand in the Reg/Opcode field.
669 // - In AVX, there is a register operand in the VEX.vvvv field here -
670 // Operand 3 (optional) is an immediate.
672 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
673 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
675 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
676 "Unexpected number of operands for MRMDestRegFrm");
678 HANDLE_OPERAND(rmRegister)
681 // FIXME: In AVX, the register below becomes the one encoded
682 // in ModRMVEX and the one above the one in the VEX.VVVV field
683 HANDLE_OPERAND(vvvvRegister)
685 HANDLE_OPERAND(roRegister)
686 HANDLE_OPTIONAL(immediate)
688 case X86Local::MRMDestMem:
689 // Operand 1 is a memory operand (possibly SIB-extended)
690 // Operand 2 is a register operand in the Reg/Opcode field.
691 // - In AVX, there is a register operand in the VEX.vvvv field here -
692 // Operand 3 (optional) is an immediate.
694 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
695 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
697 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
698 "Unexpected number of operands for MRMDestMemFrm");
699 HANDLE_OPERAND(memory)
702 HANDLE_OPERAND(writemaskRegister)
705 // FIXME: In AVX, the register below becomes the one encoded
706 // in ModRMVEX and the one above the one in the VEX.VVVV field
707 HANDLE_OPERAND(vvvvRegister)
709 HANDLE_OPERAND(roRegister)
710 HANDLE_OPTIONAL(immediate)
712 case X86Local::MRMSrcReg:
713 // Operand 1 is a register operand in the Reg/Opcode field.
714 // Operand 2 is a register operand in the R/M field.
715 // - In AVX, there is a register operand in the VEX.vvvv field here -
716 // Operand 3 (optional) is an immediate.
717 // Operand 4 (optional) is an immediate.
719 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
720 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
721 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
723 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
724 "Unexpected number of operands for MRMSrcRegFrm");
726 HANDLE_OPERAND(roRegister)
729 HANDLE_OPERAND(writemaskRegister)
732 // FIXME: In AVX, the register below becomes the one encoded
733 // in ModRMVEX and the one above the one in the VEX.VVVV field
734 HANDLE_OPERAND(vvvvRegister)
737 HANDLE_OPERAND(immediate)
739 HANDLE_OPERAND(rmRegister)
741 if (HasVEX_4VOp3Prefix)
742 HANDLE_OPERAND(vvvvRegister)
744 if (!HasMemOp4Prefix)
745 HANDLE_OPTIONAL(immediate)
746 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
747 HANDLE_OPTIONAL(immediate)
749 case X86Local::MRMSrcMem:
750 // Operand 1 is a register operand in the Reg/Opcode field.
751 // Operand 2 is a memory operand (possibly SIB-extended)
752 // - In AVX, there is a register operand in the VEX.vvvv field here -
753 // Operand 3 (optional) is an immediate.
755 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
756 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
757 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
759 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
760 "Unexpected number of operands for MRMSrcMemFrm");
762 HANDLE_OPERAND(roRegister)
765 HANDLE_OPERAND(writemaskRegister)
768 // FIXME: In AVX, the register below becomes the one encoded
769 // in ModRMVEX and the one above the one in the VEX.VVVV field
770 HANDLE_OPERAND(vvvvRegister)
773 HANDLE_OPERAND(immediate)
775 HANDLE_OPERAND(memory)
777 if (HasVEX_4VOp3Prefix)
778 HANDLE_OPERAND(vvvvRegister)
780 if (!HasMemOp4Prefix)
781 HANDLE_OPTIONAL(immediate)
782 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
784 case X86Local::MRM0r:
785 case X86Local::MRM1r:
786 case X86Local::MRM2r:
787 case X86Local::MRM3r:
788 case X86Local::MRM4r:
789 case X86Local::MRM5r:
790 case X86Local::MRM6r:
791 case X86Local::MRM7r:
793 // Operand 1 is a register operand in the R/M field.
794 // Operand 2 (optional) is an immediate or relocation.
795 // Operand 3 (optional) is an immediate.
796 unsigned kOp = (HasEVEX_K) ? 1:0;
797 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
798 if (numPhysicalOperands > 3 + kOp + Op4v)
799 llvm_unreachable("Unexpected number of operands for MRMnr");
802 HANDLE_OPERAND(vvvvRegister)
805 HANDLE_OPERAND(writemaskRegister)
806 HANDLE_OPTIONAL(rmRegister)
807 HANDLE_OPTIONAL(relocation)
808 HANDLE_OPTIONAL(immediate)
810 case X86Local::MRM0m:
811 case X86Local::MRM1m:
812 case X86Local::MRM2m:
813 case X86Local::MRM3m:
814 case X86Local::MRM4m:
815 case X86Local::MRM5m:
816 case X86Local::MRM6m:
817 case X86Local::MRM7m:
819 // Operand 1 is a memory operand (possibly SIB-extended)
820 // Operand 2 (optional) is an immediate or relocation.
821 unsigned kOp = (HasEVEX_K) ? 1:0;
822 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
823 if (numPhysicalOperands < 1 + kOp + Op4v ||
824 numPhysicalOperands > 2 + kOp + Op4v)
825 llvm_unreachable("Unexpected number of operands for MRMnm");
828 HANDLE_OPERAND(vvvvRegister)
830 HANDLE_OPERAND(writemaskRegister)
831 HANDLE_OPERAND(memory)
832 HANDLE_OPTIONAL(relocation)
834 case X86Local::RawFrmImm8:
835 // operand 1 is a 16-bit immediate
836 // operand 2 is an 8-bit immediate
837 assert(numPhysicalOperands == 2 &&
838 "Unexpected number of operands for X86Local::RawFrmImm8");
839 HANDLE_OPERAND(immediate)
840 HANDLE_OPERAND(immediate)
842 case X86Local::RawFrmImm16:
843 // operand 1 is a 16-bit immediate
844 // operand 2 is a 16-bit immediate
845 HANDLE_OPERAND(immediate)
846 HANDLE_OPERAND(immediate)
848 case X86Local::MRM_F8:
849 if (Opcode == 0xc6) {
850 assert(numPhysicalOperands == 1 &&
851 "Unexpected number of operands for X86Local::MRM_F8");
852 HANDLE_OPERAND(immediate)
853 } else if (Opcode == 0xc7) {
854 assert(numPhysicalOperands == 1 &&
855 "Unexpected number of operands for X86Local::MRM_F8");
856 HANDLE_OPERAND(relocation)
859 case X86Local::MRM_C1:
860 case X86Local::MRM_C2:
861 case X86Local::MRM_C3:
862 case X86Local::MRM_C4:
863 case X86Local::MRM_C8:
864 case X86Local::MRM_C9:
865 case X86Local::MRM_CA:
866 case X86Local::MRM_CB:
867 case X86Local::MRM_E8:
868 case X86Local::MRM_F0:
869 case X86Local::MRM_F9:
870 case X86Local::MRM_D0:
871 case X86Local::MRM_D1:
872 case X86Local::MRM_D4:
873 case X86Local::MRM_D5:
874 case X86Local::MRM_D6:
875 case X86Local::MRM_D8:
876 case X86Local::MRM_D9:
877 case X86Local::MRM_DA:
878 case X86Local::MRM_DB:
879 case X86Local::MRM_DC:
880 case X86Local::MRM_DD:
881 case X86Local::MRM_DE:
882 case X86Local::MRM_DF:
887 #undef HANDLE_OPERAND
888 #undef HANDLE_OPTIONAL
891 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
892 // Special cases where the LLVM tables are not complete
894 #define MAP(from, to) \
895 case X86Local::MRM_##from: \
896 filter = new ExactFilter(0x##from); \
899 OpcodeType opcodeType = (OpcodeType)-1;
901 ModRMFilter* filter = NULL;
902 uint8_t opcodeToSet = 0;
905 default: llvm_unreachable("Invalid prefix!");
906 // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
911 opcodeType = TWOBYTE;
915 if (needsModRMForDecode(Form))
916 filter = new ModFilter(isRegFormat(Form));
918 filter = new DumbFilter();
920 #define EXTENSION_TABLE(n) case 0x##n:
921 TWO_BYTE_EXTENSION_TABLES
922 #undef EXTENSION_TABLE
925 llvm_unreachable("Unhandled two-byte extended opcode");
926 case X86Local::MRM0r:
927 case X86Local::MRM1r:
928 case X86Local::MRM2r:
929 case X86Local::MRM3r:
930 case X86Local::MRM4r:
931 case X86Local::MRM5r:
932 case X86Local::MRM6r:
933 case X86Local::MRM7r:
934 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
936 case X86Local::MRM0m:
937 case X86Local::MRM1m:
938 case X86Local::MRM2m:
939 case X86Local::MRM3m:
940 case X86Local::MRM4m:
941 case X86Local::MRM5m:
942 case X86Local::MRM6m:
943 case X86Local::MRM7m:
944 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
950 opcodeToSet = Opcode;
956 opcodeType = THREEBYTE_38;
959 if (needsModRMForDecode(Form))
960 filter = new ModFilter(isRegFormat(Form));
962 filter = new DumbFilter();
964 #define EXTENSION_TABLE(n) case 0x##n:
965 THREE_BYTE_38_EXTENSION_TABLES
966 #undef EXTENSION_TABLE
969 llvm_unreachable("Unhandled two-byte extended opcode");
970 case X86Local::MRM0r:
971 case X86Local::MRM1r:
972 case X86Local::MRM2r:
973 case X86Local::MRM3r:
974 case X86Local::MRM4r:
975 case X86Local::MRM5r:
976 case X86Local::MRM6r:
977 case X86Local::MRM7r:
978 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
980 case X86Local::MRM0m:
981 case X86Local::MRM1m:
982 case X86Local::MRM2m:
983 case X86Local::MRM3m:
984 case X86Local::MRM4m:
985 case X86Local::MRM5m:
986 case X86Local::MRM6m:
987 case X86Local::MRM7m:
988 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
994 opcodeToSet = Opcode;
999 opcodeType = THREEBYTE_3A;
1000 if (needsModRMForDecode(Form))
1001 filter = new ModFilter(isRegFormat(Form));
1003 filter = new DumbFilter();
1004 opcodeToSet = Opcode;
1007 opcodeType = THREEBYTE_A6;
1008 if (needsModRMForDecode(Form))
1009 filter = new ModFilter(isRegFormat(Form));
1011 filter = new DumbFilter();
1012 opcodeToSet = Opcode;
1015 opcodeType = THREEBYTE_A7;
1016 if (needsModRMForDecode(Form))
1017 filter = new ModFilter(isRegFormat(Form));
1019 filter = new DumbFilter();
1020 opcodeToSet = Opcode;
1022 case X86Local::XOP8:
1023 opcodeType = XOP8_MAP;
1024 if (needsModRMForDecode(Form))
1025 filter = new ModFilter(isRegFormat(Form));
1027 filter = new DumbFilter();
1028 opcodeToSet = Opcode;
1030 case X86Local::XOP9:
1031 opcodeType = XOP9_MAP;
1034 if (needsModRMForDecode(Form))
1035 filter = new ModFilter(isRegFormat(Form));
1037 filter = new DumbFilter();
1039 #define EXTENSION_TABLE(n) case 0x##n:
1040 XOP9_MAP_EXTENSION_TABLES
1041 #undef EXTENSION_TABLE
1044 llvm_unreachable("Unhandled XOP9 extended opcode");
1045 case X86Local::MRM0r:
1046 case X86Local::MRM1r:
1047 case X86Local::MRM2r:
1048 case X86Local::MRM3r:
1049 case X86Local::MRM4r:
1050 case X86Local::MRM5r:
1051 case X86Local::MRM6r:
1052 case X86Local::MRM7r:
1053 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1055 case X86Local::MRM0m:
1056 case X86Local::MRM1m:
1057 case X86Local::MRM2m:
1058 case X86Local::MRM3m:
1059 case X86Local::MRM4m:
1060 case X86Local::MRM5m:
1061 case X86Local::MRM6m:
1062 case X86Local::MRM7m:
1063 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1068 } // switch (Opcode)
1069 opcodeToSet = Opcode;
1071 case X86Local::XOPA:
1072 opcodeType = XOPA_MAP;
1073 if (needsModRMForDecode(Form))
1074 filter = new ModFilter(isRegFormat(Form));
1076 filter = new DumbFilter();
1077 opcodeToSet = Opcode;
1087 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1088 assert(Form == X86Local::RawFrm);
1089 opcodeType = ONEBYTE;
1090 filter = new ExactFilter(Opcode);
1091 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1095 opcodeType = ONEBYTE;
1097 #define EXTENSION_TABLE(n) case 0x##n:
1098 ONE_BYTE_EXTENSION_TABLES
1099 #undef EXTENSION_TABLE
1102 llvm_unreachable("Fell through the cracks of a single-byte "
1104 case X86Local::MRM0r:
1105 case X86Local::MRM1r:
1106 case X86Local::MRM2r:
1107 case X86Local::MRM3r:
1108 case X86Local::MRM4r:
1109 case X86Local::MRM5r:
1110 case X86Local::MRM6r:
1111 case X86Local::MRM7r:
1112 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1114 case X86Local::MRM0m:
1115 case X86Local::MRM1m:
1116 case X86Local::MRM2m:
1117 case X86Local::MRM3m:
1118 case X86Local::MRM4m:
1119 case X86Local::MRM5m:
1120 case X86Local::MRM6m:
1121 case X86Local::MRM7m:
1122 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1137 llvm_unreachable("Unhandled escape opcode form");
1138 case X86Local::MRM0r:
1139 case X86Local::MRM1r:
1140 case X86Local::MRM2r:
1141 case X86Local::MRM3r:
1142 case X86Local::MRM4r:
1143 case X86Local::MRM5r:
1144 case X86Local::MRM6r:
1145 case X86Local::MRM7r:
1146 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1148 case X86Local::MRM0m:
1149 case X86Local::MRM1m:
1150 case X86Local::MRM2m:
1151 case X86Local::MRM3m:
1152 case X86Local::MRM4m:
1153 case X86Local::MRM5m:
1154 case X86Local::MRM6m:
1155 case X86Local::MRM7m:
1156 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1161 if (needsModRMForDecode(Form))
1162 filter = new ModFilter(isRegFormat(Form));
1164 filter = new DumbFilter();
1166 } // switch (Opcode)
1167 opcodeToSet = Opcode;
1168 } // switch (Prefix)
1170 assert(opcodeType != (OpcodeType)-1 &&
1171 "Opcode type not set");
1172 assert(filter && "Filter not set");
1174 if (Form == X86Local::AddRegFrm) {
1175 assert(((opcodeToSet & 7) == 0) &&
1176 "ADDREG_FRM opcode not aligned");
1178 uint8_t currentOpcode;
1180 for (currentOpcode = opcodeToSet;
1181 currentOpcode < opcodeToSet + 8;
1183 tables.setTableFields(opcodeType,
1187 UID, Is32Bit, IgnoresVEX_L);
1189 tables.setTableFields(opcodeType,
1193 UID, Is32Bit, IgnoresVEX_L);
1201 #define TYPE(str, type) if (s == str) return type;
1202 OperandType RecognizableInstr::typeFromString(const std::string &s,
1203 bool hasREX_WPrefix,
1204 bool hasOpSizePrefix,
1205 bool hasOpSize16Prefix) {
1206 if(hasREX_WPrefix) {
1207 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1209 TYPE("GR32", TYPE_R32)
1211 if(hasOpSizePrefix) {
1212 // For instructions with an OpSize prefix, a declared 16-bit register or
1213 // immediate encoding is special.
1214 TYPE("GR16", TYPE_Rv)
1215 TYPE("i16imm", TYPE_IMMv)
1217 if(hasOpSize16Prefix) {
1218 // For instructions with an OpSize16 prefix, a declared 32-bit register or
1219 // immediate encoding is special.
1220 TYPE("GR32", TYPE_Rv)
1222 TYPE("i16mem", TYPE_Mv)
1223 TYPE("i16imm", TYPE_IMM16)
1224 TYPE("i16i8imm", TYPE_IMMv)
1225 TYPE("GR16", TYPE_R16)
1226 TYPE("i32mem", TYPE_Mv)
1227 TYPE("i32imm", TYPE_IMMv)
1228 TYPE("i32i8imm", TYPE_IMM32)
1229 TYPE("u32u8imm", TYPE_IMM32)
1230 TYPE("GR32", TYPE_R32)
1231 TYPE("GR32orGR64", TYPE_R32)
1232 TYPE("i64mem", TYPE_Mv)
1233 TYPE("i64i32imm", TYPE_IMM64)
1234 TYPE("i64i8imm", TYPE_IMM64)
1235 TYPE("GR64", TYPE_R64)
1236 TYPE("i8mem", TYPE_M8)
1237 TYPE("i8imm", TYPE_IMM8)
1238 TYPE("GR8", TYPE_R8)
1239 TYPE("VR128", TYPE_XMM128)
1240 TYPE("VR128X", TYPE_XMM128)
1241 TYPE("f128mem", TYPE_M128)
1242 TYPE("f256mem", TYPE_M256)
1243 TYPE("f512mem", TYPE_M512)
1244 TYPE("FR64", TYPE_XMM64)
1245 TYPE("FR64X", TYPE_XMM64)
1246 TYPE("f64mem", TYPE_M64FP)
1247 TYPE("sdmem", TYPE_M64FP)
1248 TYPE("FR32", TYPE_XMM32)
1249 TYPE("FR32X", TYPE_XMM32)
1250 TYPE("f32mem", TYPE_M32FP)
1251 TYPE("ssmem", TYPE_M32FP)
1252 TYPE("RST", TYPE_ST)
1253 TYPE("i128mem", TYPE_M128)
1254 TYPE("i256mem", TYPE_M256)
1255 TYPE("i512mem", TYPE_M512)
1256 TYPE("i64i32imm_pcrel", TYPE_REL64)
1257 TYPE("i16imm_pcrel", TYPE_REL16)
1258 TYPE("i32imm_pcrel", TYPE_REL32)
1259 TYPE("SSECC", TYPE_IMM3)
1260 TYPE("AVXCC", TYPE_IMM5)
1261 TYPE("AVX512RC", TYPE_IMM32)
1262 TYPE("brtarget", TYPE_RELv)
1263 TYPE("uncondbrtarget", TYPE_RELv)
1264 TYPE("brtarget8", TYPE_REL8)
1265 TYPE("f80mem", TYPE_M80FP)
1266 TYPE("lea32mem", TYPE_LEA)
1267 TYPE("lea64_32mem", TYPE_LEA)
1268 TYPE("lea64mem", TYPE_LEA)
1269 TYPE("VR64", TYPE_MM64)
1270 TYPE("i64imm", TYPE_IMMv)
1271 TYPE("opaque32mem", TYPE_M1616)
1272 TYPE("opaque48mem", TYPE_M1632)
1273 TYPE("opaque80mem", TYPE_M1664)
1274 TYPE("opaque512mem", TYPE_M512)
1275 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1276 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1277 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1278 TYPE("srcidx8", TYPE_SRCIDX8)
1279 TYPE("srcidx16", TYPE_SRCIDX16)
1280 TYPE("srcidx32", TYPE_SRCIDX32)
1281 TYPE("srcidx64", TYPE_SRCIDX64)
1282 TYPE("dstidx8", TYPE_DSTIDX8)
1283 TYPE("dstidx16", TYPE_DSTIDX16)
1284 TYPE("dstidx32", TYPE_DSTIDX32)
1285 TYPE("dstidx64", TYPE_DSTIDX64)
1286 TYPE("offset8", TYPE_MOFFS8)
1287 TYPE("offset16", TYPE_MOFFS16)
1288 TYPE("offset32", TYPE_MOFFS32)
1289 TYPE("offset64", TYPE_MOFFS64)
1290 TYPE("VR256", TYPE_XMM256)
1291 TYPE("VR256X", TYPE_XMM256)
1292 TYPE("VR512", TYPE_XMM512)
1293 TYPE("VK1", TYPE_VK1)
1294 TYPE("VK1WM", TYPE_VK1)
1295 TYPE("VK8", TYPE_VK8)
1296 TYPE("VK8WM", TYPE_VK8)
1297 TYPE("VK16", TYPE_VK16)
1298 TYPE("VK16WM", TYPE_VK16)
1299 TYPE("GR16_NOAX", TYPE_Rv)
1300 TYPE("GR32_NOAX", TYPE_Rv)
1301 TYPE("GR64_NOAX", TYPE_R64)
1302 TYPE("vx32mem", TYPE_M32)
1303 TYPE("vy32mem", TYPE_M32)
1304 TYPE("vz32mem", TYPE_M32)
1305 TYPE("vx64mem", TYPE_M64)
1306 TYPE("vy64mem", TYPE_M64)
1307 TYPE("vy64xmem", TYPE_M64)
1308 TYPE("vz64mem", TYPE_M64)
1309 errs() << "Unhandled type string " << s << "\n";
1310 llvm_unreachable("Unhandled type string");
1314 #define ENCODING(str, encoding) if (s == str) return encoding;
1315 OperandEncoding RecognizableInstr::immediateEncodingFromString
1316 (const std::string &s,
1317 bool hasOpSizePrefix) {
1318 if(!hasOpSizePrefix) {
1319 // For instructions without an OpSize prefix, a declared 16-bit register or
1320 // immediate encoding is special.
1321 ENCODING("i16imm", ENCODING_IW)
1323 ENCODING("i32i8imm", ENCODING_IB)
1324 ENCODING("u32u8imm", ENCODING_IB)
1325 ENCODING("SSECC", ENCODING_IB)
1326 ENCODING("AVXCC", ENCODING_IB)
1327 ENCODING("AVX512RC", ENCODING_IB)
1328 ENCODING("i16imm", ENCODING_Iv)
1329 ENCODING("i16i8imm", ENCODING_IB)
1330 ENCODING("i32imm", ENCODING_Iv)
1331 ENCODING("i64i32imm", ENCODING_ID)
1332 ENCODING("i64i8imm", ENCODING_IB)
1333 ENCODING("i8imm", ENCODING_IB)
1334 // This is not a typo. Instructions like BLENDVPD put
1335 // register IDs in 8-bit immediates nowadays.
1336 ENCODING("FR32", ENCODING_IB)
1337 ENCODING("FR64", ENCODING_IB)
1338 ENCODING("VR128", ENCODING_IB)
1339 ENCODING("VR256", ENCODING_IB)
1340 ENCODING("FR32X", ENCODING_IB)
1341 ENCODING("FR64X", ENCODING_IB)
1342 ENCODING("VR128X", ENCODING_IB)
1343 ENCODING("VR256X", ENCODING_IB)
1344 ENCODING("VR512", ENCODING_IB)
1345 errs() << "Unhandled immediate encoding " << s << "\n";
1346 llvm_unreachable("Unhandled immediate encoding");
1349 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1350 (const std::string &s,
1351 bool hasOpSizePrefix) {
1352 ENCODING("RST", ENCODING_FP)
1353 ENCODING("GR16", ENCODING_RM)
1354 ENCODING("GR32", ENCODING_RM)
1355 ENCODING("GR32orGR64", ENCODING_RM)
1356 ENCODING("GR64", ENCODING_RM)
1357 ENCODING("GR8", ENCODING_RM)
1358 ENCODING("VR128", ENCODING_RM)
1359 ENCODING("VR128X", ENCODING_RM)
1360 ENCODING("FR64", ENCODING_RM)
1361 ENCODING("FR32", ENCODING_RM)
1362 ENCODING("FR64X", ENCODING_RM)
1363 ENCODING("FR32X", ENCODING_RM)
1364 ENCODING("VR64", ENCODING_RM)
1365 ENCODING("VR256", ENCODING_RM)
1366 ENCODING("VR256X", ENCODING_RM)
1367 ENCODING("VR512", ENCODING_RM)
1368 ENCODING("VK1", ENCODING_RM)
1369 ENCODING("VK8", ENCODING_RM)
1370 ENCODING("VK16", ENCODING_RM)
1371 errs() << "Unhandled R/M register encoding " << s << "\n";
1372 llvm_unreachable("Unhandled R/M register encoding");
1375 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1376 (const std::string &s,
1377 bool hasOpSizePrefix) {
1378 ENCODING("GR16", ENCODING_REG)
1379 ENCODING("GR32", ENCODING_REG)
1380 ENCODING("GR32orGR64", ENCODING_REG)
1381 ENCODING("GR64", ENCODING_REG)
1382 ENCODING("GR8", ENCODING_REG)
1383 ENCODING("VR128", ENCODING_REG)
1384 ENCODING("FR64", ENCODING_REG)
1385 ENCODING("FR32", ENCODING_REG)
1386 ENCODING("VR64", ENCODING_REG)
1387 ENCODING("SEGMENT_REG", ENCODING_REG)
1388 ENCODING("DEBUG_REG", ENCODING_REG)
1389 ENCODING("CONTROL_REG", ENCODING_REG)
1390 ENCODING("VR256", ENCODING_REG)
1391 ENCODING("VR256X", ENCODING_REG)
1392 ENCODING("VR128X", ENCODING_REG)
1393 ENCODING("FR64X", ENCODING_REG)
1394 ENCODING("FR32X", ENCODING_REG)
1395 ENCODING("VR512", ENCODING_REG)
1396 ENCODING("VK1", ENCODING_REG)
1397 ENCODING("VK8", ENCODING_REG)
1398 ENCODING("VK16", ENCODING_REG)
1399 ENCODING("VK1WM", ENCODING_REG)
1400 ENCODING("VK8WM", ENCODING_REG)
1401 ENCODING("VK16WM", ENCODING_REG)
1402 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1403 llvm_unreachable("Unhandled reg/opcode register encoding");
1406 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1407 (const std::string &s,
1408 bool hasOpSizePrefix) {
1409 ENCODING("GR32", ENCODING_VVVV)
1410 ENCODING("GR64", ENCODING_VVVV)
1411 ENCODING("FR32", ENCODING_VVVV)
1412 ENCODING("FR64", ENCODING_VVVV)
1413 ENCODING("VR128", ENCODING_VVVV)
1414 ENCODING("VR256", ENCODING_VVVV)
1415 ENCODING("FR32X", ENCODING_VVVV)
1416 ENCODING("FR64X", ENCODING_VVVV)
1417 ENCODING("VR128X", ENCODING_VVVV)
1418 ENCODING("VR256X", ENCODING_VVVV)
1419 ENCODING("VR512", ENCODING_VVVV)
1420 ENCODING("VK1", ENCODING_VVVV)
1421 ENCODING("VK8", ENCODING_VVVV)
1422 ENCODING("VK16", ENCODING_VVVV)
1423 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1424 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1427 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1428 (const std::string &s,
1429 bool hasOpSizePrefix) {
1430 ENCODING("VK1WM", ENCODING_WRITEMASK)
1431 ENCODING("VK8WM", ENCODING_WRITEMASK)
1432 ENCODING("VK16WM", ENCODING_WRITEMASK)
1433 errs() << "Unhandled mask register encoding " << s << "\n";
1434 llvm_unreachable("Unhandled mask register encoding");
1437 OperandEncoding RecognizableInstr::memoryEncodingFromString
1438 (const std::string &s,
1439 bool hasOpSizePrefix) {
1440 ENCODING("i16mem", ENCODING_RM)
1441 ENCODING("i32mem", ENCODING_RM)
1442 ENCODING("i64mem", ENCODING_RM)
1443 ENCODING("i8mem", ENCODING_RM)
1444 ENCODING("ssmem", ENCODING_RM)
1445 ENCODING("sdmem", ENCODING_RM)
1446 ENCODING("f128mem", ENCODING_RM)
1447 ENCODING("f256mem", ENCODING_RM)
1448 ENCODING("f512mem", ENCODING_RM)
1449 ENCODING("f64mem", ENCODING_RM)
1450 ENCODING("f32mem", ENCODING_RM)
1451 ENCODING("i128mem", ENCODING_RM)
1452 ENCODING("i256mem", ENCODING_RM)
1453 ENCODING("i512mem", ENCODING_RM)
1454 ENCODING("f80mem", ENCODING_RM)
1455 ENCODING("lea32mem", ENCODING_RM)
1456 ENCODING("lea64_32mem", ENCODING_RM)
1457 ENCODING("lea64mem", ENCODING_RM)
1458 ENCODING("opaque32mem", ENCODING_RM)
1459 ENCODING("opaque48mem", ENCODING_RM)
1460 ENCODING("opaque80mem", ENCODING_RM)
1461 ENCODING("opaque512mem", ENCODING_RM)
1462 ENCODING("vx32mem", ENCODING_RM)
1463 ENCODING("vy32mem", ENCODING_RM)
1464 ENCODING("vz32mem", ENCODING_RM)
1465 ENCODING("vx64mem", ENCODING_RM)
1466 ENCODING("vy64mem", ENCODING_RM)
1467 ENCODING("vy64xmem", ENCODING_RM)
1468 ENCODING("vz64mem", ENCODING_RM)
1469 errs() << "Unhandled memory encoding " << s << "\n";
1470 llvm_unreachable("Unhandled memory encoding");
1473 OperandEncoding RecognizableInstr::relocationEncodingFromString
1474 (const std::string &s,
1475 bool hasOpSizePrefix) {
1476 if(!hasOpSizePrefix) {
1477 // For instructions without an OpSize prefix, a declared 16-bit register or
1478 // immediate encoding is special.
1479 ENCODING("i16imm", ENCODING_IW)
1481 ENCODING("i16imm", ENCODING_Iv)
1482 ENCODING("i16i8imm", ENCODING_IB)
1483 ENCODING("i32imm", ENCODING_Iv)
1484 ENCODING("i32i8imm", ENCODING_IB)
1485 ENCODING("i64i32imm", ENCODING_ID)
1486 ENCODING("i64i8imm", ENCODING_IB)
1487 ENCODING("i8imm", ENCODING_IB)
1488 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1489 ENCODING("i16imm_pcrel", ENCODING_IW)
1490 ENCODING("i32imm_pcrel", ENCODING_ID)
1491 ENCODING("brtarget", ENCODING_Iv)
1492 ENCODING("brtarget8", ENCODING_IB)
1493 ENCODING("i64imm", ENCODING_IO)
1494 ENCODING("offset8", ENCODING_Ia)
1495 ENCODING("offset16", ENCODING_Ia)
1496 ENCODING("offset32", ENCODING_Ia)
1497 ENCODING("offset64", ENCODING_Ia)
1498 ENCODING("srcidx8", ENCODING_SI)
1499 ENCODING("srcidx16", ENCODING_SI)
1500 ENCODING("srcidx32", ENCODING_SI)
1501 ENCODING("srcidx64", ENCODING_SI)
1502 ENCODING("dstidx8", ENCODING_DI)
1503 ENCODING("dstidx16", ENCODING_DI)
1504 ENCODING("dstidx32", ENCODING_DI)
1505 ENCODING("dstidx64", ENCODING_DI)
1506 errs() << "Unhandled relocation encoding " << s << "\n";
1507 llvm_unreachable("Unhandled relocation encoding");
1510 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1511 (const std::string &s,
1512 bool hasOpSizePrefix) {
1513 ENCODING("GR32", ENCODING_Rv)
1514 ENCODING("GR64", ENCODING_RO)
1515 ENCODING("GR16", ENCODING_Rv)
1516 ENCODING("GR8", ENCODING_RB)
1517 ENCODING("GR16_NOAX", ENCODING_Rv)
1518 ENCODING("GR32_NOAX", ENCODING_Rv)
1519 ENCODING("GR64_NOAX", ENCODING_RO)
1520 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1521 llvm_unreachable("Unhandled opcode modifier encoding");