1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
41 // A clone of X86 since we can't depend on something that is generated.
51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
56 #define MAP(from, to) MRM_##from = to,
67 D8 = 3, D9 = 4, DA = 5, DB = 6,
68 DC = 7, DD = 8, DE = 9, DF = 10,
71 A6 = 15, A7 = 16, TF = 17
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
92 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(c6) \
101 EXTENSION_TABLE(c7) \
102 EXTENSION_TABLE(d0) \
103 EXTENSION_TABLE(d1) \
104 EXTENSION_TABLE(d2) \
105 EXTENSION_TABLE(d3) \
106 EXTENSION_TABLE(f6) \
107 EXTENSION_TABLE(f7) \
108 EXTENSION_TABLE(fe) \
111 #define TWO_BYTE_EXTENSION_TABLES \
112 EXTENSION_TABLE(00) \
113 EXTENSION_TABLE(01) \
114 EXTENSION_TABLE(18) \
115 EXTENSION_TABLE(71) \
116 EXTENSION_TABLE(72) \
117 EXTENSION_TABLE(73) \
118 EXTENSION_TABLE(ae) \
119 EXTENSION_TABLE(ba) \
122 using namespace X86Disassembler;
124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
125 /// ModR/M byte for the instruction to be properly decoded. For example, a
126 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
129 /// @param form - The form of the instruction.
130 /// @return - true if the form implies that a ModR/M byte is required, false
132 static bool needsModRMForDecode(uint8_t form) {
133 if (form == X86Local::MRMDestReg ||
134 form == X86Local::MRMDestMem ||
135 form == X86Local::MRMSrcReg ||
136 form == X86Local::MRMSrcMem ||
137 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
145 /// the ModR/M byte to be 0b11.
147 /// @param form - The form of the instruction.
148 /// @return - true if the form implies that Mod must be 0b11, false
150 static bool isRegFormat(uint8_t form) {
151 if (form == X86Local::MRMDestReg ||
152 form == X86Local::MRMSrcReg ||
153 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160 /// Useful for switch statements and the like.
162 /// @param init - A reference to the BitsInit to be decoded.
163 /// @return - The field, with the first bit in the BitsInit as the lowest
165 static uint8_t byteFromBitsInit(BitsInit &init) {
166 int width = init.getNumBits();
168 assert(width <= 8 && "Field is too large for uint8_t!");
175 for (index = 0; index < width; index++) {
176 if (static_cast<BitInit*>(init.getBit(index))->getValue())
185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186 /// name of the field.
188 /// @param rec - The record from which to extract the value.
189 /// @param name - The name of the field in the record.
190 /// @return - The field, as translated by byteFromBitsInit().
191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192 BitsInit* bits = rec->getValueAsBitsInit(name);
193 return byteFromBitsInit(*bits);
196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197 const CodeGenInstruction &insn,
202 Name = Rec->getName();
203 Spec = &tables.specForUID(UID);
205 if (!Rec->isSubClassOf("X86Inst")) {
206 ShouldBeEmitted = false;
210 Prefix = byteFromRec(Rec, "Prefix");
211 Opcode = byteFromRec(Rec, "Opcode");
212 Form = byteFromRec(Rec, "FormBits");
213 SegOvr = byteFromRec(Rec, "SegOvrBits");
215 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
216 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
217 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
218 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
219 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
220 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
221 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
222 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
224 Name = Rec->getName();
225 AsmString = Rec->getValueAsString("AsmString");
227 Operands = &insn.Operands.OperandList;
229 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
230 (Name.find("CRC32") != Name.npos);
231 HasFROperands = hasFROperands();
232 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
234 // Check for 64-bit inst which does not require REX
237 // FIXME: Is there some better way to check for In64BitMode?
238 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
239 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
240 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
244 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
249 // FIXME: These instructions aren't marked as 64-bit in any way
250 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
251 Rec->getName() == "MASKMOVDQU64" ||
252 Rec->getName() == "POPFS64" ||
253 Rec->getName() == "POPGS64" ||
254 Rec->getName() == "PUSHFS64" ||
255 Rec->getName() == "PUSHGS64" ||
256 Rec->getName() == "REX64_PREFIX" ||
257 Rec->getName().find("VMREAD64") != Name.npos ||
258 Rec->getName().find("VMWRITE64") != Name.npos ||
259 Rec->getName().find("INVEPT64") != Name.npos ||
260 Rec->getName().find("INVVPID64") != Name.npos ||
261 Rec->getName().find("MOV64") != Name.npos ||
262 Rec->getName().find("PUSH64") != Name.npos ||
263 Rec->getName().find("POP64") != Name.npos;
265 ShouldBeEmitted = true;
268 void RecognizableInstr::processInstr(DisassemblerTables &tables,
269 const CodeGenInstruction &insn,
272 // Ignore "asm parser only" instructions.
273 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
276 RecognizableInstr recogInstr(tables, insn, uid);
278 recogInstr.emitInstructionSpecifier(tables);
280 if (recogInstr.shouldBeEmitted())
281 recogInstr.emitDecodePath(tables);
284 InstructionContext RecognizableInstr::insnContext() const {
285 InstructionContext insnContext;
287 if (HasVEX_4VPrefix || HasVEXPrefix) {
288 if (HasVEX_LPrefix && HasVEX_WPrefix)
289 llvm_unreachable("Don't support VEX.L and VEX.W together");
290 else if (HasOpSizePrefix && HasVEX_LPrefix)
291 insnContext = IC_VEX_L_OPSIZE;
292 else if (HasOpSizePrefix && HasVEX_WPrefix)
293 insnContext = IC_VEX_W_OPSIZE;
294 else if (HasOpSizePrefix)
295 insnContext = IC_VEX_OPSIZE;
296 else if (HasVEX_LPrefix && Prefix == X86Local::XS)
297 insnContext = IC_VEX_L_XS;
298 else if (HasVEX_LPrefix && Prefix == X86Local::XD)
299 insnContext = IC_VEX_L_XD;
300 else if (HasVEX_WPrefix && Prefix == X86Local::XS)
301 insnContext = IC_VEX_W_XS;
302 else if (HasVEX_WPrefix && Prefix == X86Local::XD)
303 insnContext = IC_VEX_W_XD;
304 else if (HasVEX_WPrefix)
305 insnContext = IC_VEX_W;
306 else if (HasVEX_LPrefix)
307 insnContext = IC_VEX_L;
308 else if (Prefix == X86Local::XD)
309 insnContext = IC_VEX_XD;
310 else if (Prefix == X86Local::XS)
311 insnContext = IC_VEX_XS;
313 insnContext = IC_VEX;
314 } else if (Is64Bit || HasREX_WPrefix) {
315 if (HasREX_WPrefix && HasOpSizePrefix)
316 insnContext = IC_64BIT_REXW_OPSIZE;
317 else if (HasOpSizePrefix && (Prefix == X86Local::XD || Prefix == X86Local::TF))
318 insnContext = IC_64BIT_XD_OPSIZE;
319 else if (HasOpSizePrefix)
320 insnContext = IC_64BIT_OPSIZE;
321 else if (HasREX_WPrefix && Prefix == X86Local::XS)
322 insnContext = IC_64BIT_REXW_XS;
323 else if (HasREX_WPrefix && (Prefix == X86Local::XD || Prefix == X86Local::TF))
324 insnContext = IC_64BIT_REXW_XD;
325 else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
326 insnContext = IC_64BIT_XD;
327 else if (Prefix == X86Local::XS)
328 insnContext = IC_64BIT_XS;
329 else if (HasREX_WPrefix)
330 insnContext = IC_64BIT_REXW;
332 insnContext = IC_64BIT;
334 if (HasOpSizePrefix &&
335 (Prefix == X86Local::XD || Prefix == X86Local::TF))
336 insnContext = IC_XD_OPSIZE;
337 else if (HasOpSizePrefix)
338 insnContext = IC_OPSIZE;
339 else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
341 else if (Prefix == X86Local::XS || Prefix == X86Local::REP)
350 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
355 // Filter out intrinsics
357 if (!Rec->isSubClassOf("X86Inst"))
358 return FILTER_STRONG;
360 if (Form == X86Local::Pseudo ||
361 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
362 return FILTER_STRONG;
364 if (Form == X86Local::MRMInitReg)
365 return FILTER_STRONG;
368 // Filter out artificial instructions
370 if (Name.find("TAILJMP") != Name.npos ||
371 Name.find("_Int") != Name.npos ||
372 Name.find("_int") != Name.npos ||
373 Name.find("Int_") != Name.npos ||
374 Name.find("_NOREX") != Name.npos ||
375 Name.find("_TC") != Name.npos ||
376 Name.find("EH_RETURN") != Name.npos ||
377 Name.find("V_SET") != Name.npos ||
378 Name.find("LOCK_") != Name.npos ||
379 Name.find("WIN") != Name.npos ||
380 Name.find("_AVX") != Name.npos ||
381 Name.find("2SDL") != Name.npos)
382 return FILTER_STRONG;
384 // Filter out instructions with segment override prefixes.
385 // They're too messy to handle now and we'll special case them if needed.
388 return FILTER_STRONG;
390 // Filter out instructions that can't be printed.
392 if (AsmString.size() == 0)
393 return FILTER_STRONG;
395 // Filter out instructions with subreg operands.
397 if (AsmString.find("subreg") != AsmString.npos)
398 return FILTER_STRONG;
405 // Filter out instructions with a LOCK prefix;
406 // prefer forms that do not have the prefix
410 // Filter out alternate forms of AVX instructions
411 if (Name.find("_alt") != Name.npos ||
412 Name.find("XrYr") != Name.npos ||
413 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
414 Name.find("_64mr") != Name.npos ||
415 Name.find("Xrr") != Name.npos ||
416 Name.find("rr64") != Name.npos)
419 if (Name == "VMASKMOVDQU64" ||
420 Name == "VEXTRACTPSrr64" ||
421 Name == "VMOVQd64rr" ||
422 Name == "VMOVQs64rr")
427 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
429 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
432 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
434 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
436 if (Name.find("Fs") != Name.npos)
438 if (Name == "MOVLPDrr" ||
439 Name == "MOVLPSrr" ||
445 Name == "MOVSX16rm8" ||
446 Name == "MOVSX16rr8" ||
447 Name == "MOVZX16rm8" ||
448 Name == "MOVZX16rr8" ||
449 Name == "PUSH32i16" ||
450 Name == "PUSH64i16" ||
451 Name == "MOVPQI2QImr" ||
452 Name == "VMOVPQI2QImr" ||
457 Name == "MMX_MOVD64rrv164" ||
458 Name == "CRC32m16" ||
459 Name == "MOV64ri64i32" ||
463 if (HasFROperands && Name.find("MOV") != Name.npos &&
464 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
465 (Name.find("to") != Name.npos)))
468 return FILTER_NORMAL;
471 bool RecognizableInstr::hasFROperands() const {
472 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
473 unsigned numOperands = OperandList.size();
475 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
476 const std::string &recName = OperandList[operandIndex].Rec->getName();
478 if (recName.find("FR") != recName.npos)
484 bool RecognizableInstr::has256BitOperands() const {
485 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
486 unsigned numOperands = OperandList.size();
488 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
489 const std::string &recName = OperandList[operandIndex].Rec->getName();
491 if (!recName.compare("VR256") || !recName.compare("f256mem")) {
498 void RecognizableInstr::handleOperand(
500 unsigned &operandIndex,
501 unsigned &physicalOperandIndex,
502 unsigned &numPhysicalOperands,
503 unsigned *operandMapping,
504 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
506 if (physicalOperandIndex >= numPhysicalOperands)
509 assert(physicalOperandIndex < numPhysicalOperands);
512 while (operandMapping[operandIndex] != operandIndex) {
513 Spec->operands[operandIndex].encoding = ENCODING_DUP;
514 Spec->operands[operandIndex].type =
515 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
519 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
521 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
523 Spec->operands[operandIndex].type = typeFromString(typeName,
529 ++physicalOperandIndex;
532 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
535 if (!Rec->isSubClassOf("X86Inst"))
540 Spec->filtered = true;
543 ShouldBeEmitted = false;
549 Spec->insnContext = insnContext();
551 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
553 unsigned operandIndex;
554 unsigned numOperands = OperandList.size();
555 unsigned numPhysicalOperands = 0;
557 // operandMapping maps from operands in OperandList to their originals.
558 // If operandMapping[i] != i, then the entry is a duplicate.
559 unsigned operandMapping[X86_MAX_OPERANDS];
561 bool hasFROperands = false;
563 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
565 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
566 if (OperandList[operandIndex].Constraints.size()) {
567 const CGIOperandList::ConstraintInfo &Constraint =
568 OperandList[operandIndex].Constraints[0];
569 if (Constraint.isTied()) {
570 operandMapping[operandIndex] = Constraint.getTiedOperand();
572 ++numPhysicalOperands;
573 operandMapping[operandIndex] = operandIndex;
576 ++numPhysicalOperands;
577 operandMapping[operandIndex] = operandIndex;
580 const std::string &recName = OperandList[operandIndex].Rec->getName();
582 if (recName.find("FR") != recName.npos)
583 hasFROperands = true;
586 if (hasFROperands && Name.find("MOV") != Name.npos &&
587 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
588 (Name.find("to") != Name.npos)))
589 ShouldBeEmitted = false;
591 if (!ShouldBeEmitted)
594 #define HANDLE_OPERAND(class) \
595 handleOperand(false, \
597 physicalOperandIndex, \
598 numPhysicalOperands, \
600 class##EncodingFromString);
602 #define HANDLE_OPTIONAL(class) \
603 handleOperand(true, \
605 physicalOperandIndex, \
606 numPhysicalOperands, \
608 class##EncodingFromString);
610 // operandIndex should always be < numOperands
612 // physicalOperandIndex should always be < numPhysicalOperands
613 unsigned physicalOperandIndex = 0;
616 case X86Local::RawFrm:
617 // Operand 1 (optional) is an address or immediate.
618 // Operand 2 (optional) is an immediate.
619 assert(numPhysicalOperands <= 2 &&
620 "Unexpected number of operands for RawFrm");
621 HANDLE_OPTIONAL(relocation)
622 HANDLE_OPTIONAL(immediate)
624 case X86Local::AddRegFrm:
625 // Operand 1 is added to the opcode.
626 // Operand 2 (optional) is an address.
627 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
628 "Unexpected number of operands for AddRegFrm");
629 HANDLE_OPERAND(opcodeModifier)
630 HANDLE_OPTIONAL(relocation)
632 case X86Local::MRMDestReg:
633 // Operand 1 is a register operand in the R/M field.
634 // Operand 2 is a register operand in the Reg/Opcode field.
635 // - In AVX, there is a register operand in the VEX.vvvv field here -
636 // Operand 3 (optional) is an immediate.
638 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
639 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
641 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
642 "Unexpected number of operands for MRMDestRegFrm");
644 HANDLE_OPERAND(rmRegister)
647 // FIXME: In AVX, the register below becomes the one encoded
648 // in ModRMVEX and the one above the one in the VEX.VVVV field
649 HANDLE_OPERAND(vvvvRegister)
651 HANDLE_OPERAND(roRegister)
652 HANDLE_OPTIONAL(immediate)
654 case X86Local::MRMDestMem:
655 // Operand 1 is a memory operand (possibly SIB-extended)
656 // Operand 2 is a register operand in the Reg/Opcode field.
657 // - In AVX, there is a register operand in the VEX.vvvv field here -
658 // Operand 3 (optional) is an immediate.
660 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
661 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
663 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
664 "Unexpected number of operands for MRMDestMemFrm");
665 HANDLE_OPERAND(memory)
668 // FIXME: In AVX, the register below becomes the one encoded
669 // in ModRMVEX and the one above the one in the VEX.VVVV field
670 HANDLE_OPERAND(vvvvRegister)
672 HANDLE_OPERAND(roRegister)
673 HANDLE_OPTIONAL(immediate)
675 case X86Local::MRMSrcReg:
676 // Operand 1 is a register operand in the Reg/Opcode field.
677 // Operand 2 is a register operand in the R/M field.
678 // - In AVX, there is a register operand in the VEX.vvvv field here -
679 // Operand 3 (optional) is an immediate.
682 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
683 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
685 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
686 "Unexpected number of operands for MRMSrcRegFrm");
688 HANDLE_OPERAND(roRegister)
691 // FIXME: In AVX, the register below becomes the one encoded
692 // in ModRMVEX and the one above the one in the VEX.VVVV field
693 HANDLE_OPERAND(vvvvRegister)
695 HANDLE_OPERAND(rmRegister)
696 HANDLE_OPTIONAL(immediate)
698 case X86Local::MRMSrcMem:
699 // Operand 1 is a register operand in the Reg/Opcode field.
700 // Operand 2 is a memory operand (possibly SIB-extended)
701 // - In AVX, there is a register operand in the VEX.vvvv field here -
702 // Operand 3 (optional) is an immediate.
705 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
706 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
708 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
709 "Unexpected number of operands for MRMSrcMemFrm");
711 HANDLE_OPERAND(roRegister)
714 // FIXME: In AVX, the register below becomes the one encoded
715 // in ModRMVEX and the one above the one in the VEX.VVVV field
716 HANDLE_OPERAND(vvvvRegister)
718 HANDLE_OPERAND(memory)
719 HANDLE_OPTIONAL(immediate)
721 case X86Local::MRM0r:
722 case X86Local::MRM1r:
723 case X86Local::MRM2r:
724 case X86Local::MRM3r:
725 case X86Local::MRM4r:
726 case X86Local::MRM5r:
727 case X86Local::MRM6r:
728 case X86Local::MRM7r:
729 // Operand 1 is a register operand in the R/M field.
730 // Operand 2 (optional) is an immediate or relocation.
732 assert(numPhysicalOperands <= 3 &&
733 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
735 assert(numPhysicalOperands <= 2 &&
736 "Unexpected number of operands for MRMnRFrm");
738 HANDLE_OPERAND(vvvvRegister);
739 HANDLE_OPTIONAL(rmRegister)
740 HANDLE_OPTIONAL(relocation)
742 case X86Local::MRM0m:
743 case X86Local::MRM1m:
744 case X86Local::MRM2m:
745 case X86Local::MRM3m:
746 case X86Local::MRM4m:
747 case X86Local::MRM5m:
748 case X86Local::MRM6m:
749 case X86Local::MRM7m:
750 // Operand 1 is a memory operand (possibly SIB-extended)
751 // Operand 2 (optional) is an immediate or relocation.
752 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
753 "Unexpected number of operands for MRMnMFrm");
754 HANDLE_OPERAND(memory)
755 HANDLE_OPTIONAL(relocation)
757 case X86Local::RawFrmImm8:
758 // operand 1 is a 16-bit immediate
759 // operand 2 is an 8-bit immediate
760 assert(numPhysicalOperands == 2 &&
761 "Unexpected number of operands for X86Local::RawFrmImm8");
762 HANDLE_OPERAND(immediate)
763 HANDLE_OPERAND(immediate)
765 case X86Local::RawFrmImm16:
766 // operand 1 is a 16-bit immediate
767 // operand 2 is a 16-bit immediate
768 HANDLE_OPERAND(immediate)
769 HANDLE_OPERAND(immediate)
771 case X86Local::MRMInitReg:
776 #undef HANDLE_OPERAND
777 #undef HANDLE_OPTIONAL
780 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
781 // Special cases where the LLVM tables are not complete
783 #define MAP(from, to) \
784 case X86Local::MRM_##from: \
785 filter = new ExactFilter(0x##from); \
788 OpcodeType opcodeType = (OpcodeType)-1;
790 ModRMFilter* filter = NULL;
791 uint8_t opcodeToSet = 0;
794 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
798 opcodeType = TWOBYTE;
802 if (needsModRMForDecode(Form))
803 filter = new ModFilter(isRegFormat(Form));
805 filter = new DumbFilter();
807 #define EXTENSION_TABLE(n) case 0x##n:
808 TWO_BYTE_EXTENSION_TABLES
809 #undef EXTENSION_TABLE
812 llvm_unreachable("Unhandled two-byte extended opcode");
813 case X86Local::MRM0r:
814 case X86Local::MRM1r:
815 case X86Local::MRM2r:
816 case X86Local::MRM3r:
817 case X86Local::MRM4r:
818 case X86Local::MRM5r:
819 case X86Local::MRM6r:
820 case X86Local::MRM7r:
821 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
823 case X86Local::MRM0m:
824 case X86Local::MRM1m:
825 case X86Local::MRM2m:
826 case X86Local::MRM3m:
827 case X86Local::MRM4m:
828 case X86Local::MRM5m:
829 case X86Local::MRM6m:
830 case X86Local::MRM7m:
831 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
837 opcodeToSet = Opcode;
841 opcodeType = THREEBYTE_38;
842 if (needsModRMForDecode(Form))
843 filter = new ModFilter(isRegFormat(Form));
845 filter = new DumbFilter();
846 opcodeToSet = Opcode;
849 opcodeType = THREEBYTE_3A;
850 if (needsModRMForDecode(Form))
851 filter = new ModFilter(isRegFormat(Form));
853 filter = new DumbFilter();
854 opcodeToSet = Opcode;
857 opcodeType = THREEBYTE_A6;
858 if (needsModRMForDecode(Form))
859 filter = new ModFilter(isRegFormat(Form));
861 filter = new DumbFilter();
862 opcodeToSet = Opcode;
865 opcodeType = THREEBYTE_A7;
866 if (needsModRMForDecode(Form))
867 filter = new ModFilter(isRegFormat(Form));
869 filter = new DumbFilter();
870 opcodeToSet = Opcode;
880 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
881 opcodeType = ONEBYTE;
882 if (Form == X86Local::AddRegFrm) {
883 Spec->modifierType = MODIFIER_MODRM;
884 Spec->modifierBase = Opcode;
885 filter = new AddRegEscapeFilter(Opcode);
887 filter = new EscapeFilter(true, Opcode);
889 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
893 opcodeType = ONEBYTE;
895 #define EXTENSION_TABLE(n) case 0x##n:
896 ONE_BYTE_EXTENSION_TABLES
897 #undef EXTENSION_TABLE
900 llvm_unreachable("Fell through the cracks of a single-byte "
902 case X86Local::MRM0r:
903 case X86Local::MRM1r:
904 case X86Local::MRM2r:
905 case X86Local::MRM3r:
906 case X86Local::MRM4r:
907 case X86Local::MRM5r:
908 case X86Local::MRM6r:
909 case X86Local::MRM7r:
910 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
912 case X86Local::MRM0m:
913 case X86Local::MRM1m:
914 case X86Local::MRM2m:
915 case X86Local::MRM3m:
916 case X86Local::MRM4m:
917 case X86Local::MRM5m:
918 case X86Local::MRM6m:
919 case X86Local::MRM7m:
920 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
933 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
936 if (needsModRMForDecode(Form))
937 filter = new ModFilter(isRegFormat(Form));
939 filter = new DumbFilter();
942 opcodeToSet = Opcode;
945 assert(opcodeType != (OpcodeType)-1 &&
946 "Opcode type not set");
947 assert(filter && "Filter not set");
949 if (Form == X86Local::AddRegFrm) {
950 if(Spec->modifierType != MODIFIER_MODRM) {
951 assert(opcodeToSet < 0xf9 &&
952 "Not enough room for all ADDREG_FRM operands");
954 uint8_t currentOpcode;
956 for (currentOpcode = opcodeToSet;
957 currentOpcode < opcodeToSet + 8;
959 tables.setTableFields(opcodeType,
963 UID, Is32Bit, IgnoresVEX_L);
965 Spec->modifierType = MODIFIER_OPCODE;
966 Spec->modifierBase = opcodeToSet;
968 // modifierBase was set where MODIFIER_MODRM was set
969 tables.setTableFields(opcodeType,
973 UID, Is32Bit, IgnoresVEX_L);
976 tables.setTableFields(opcodeType,
980 UID, Is32Bit, IgnoresVEX_L);
982 Spec->modifierType = MODIFIER_NONE;
983 Spec->modifierBase = opcodeToSet;
991 #define TYPE(str, type) if (s == str) return type;
992 OperandType RecognizableInstr::typeFromString(const std::string &s,
995 bool hasOpSizePrefix) {
997 // For SSE instructions, we ignore the OpSize prefix and force operand
999 TYPE("GR16", TYPE_R16)
1000 TYPE("GR32", TYPE_R32)
1001 TYPE("GR64", TYPE_R64)
1003 if(hasREX_WPrefix) {
1004 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1006 TYPE("GR32", TYPE_R32)
1008 if(!hasOpSizePrefix) {
1009 // For instructions without an OpSize prefix, a declared 16-bit register or
1010 // immediate encoding is special.
1011 TYPE("GR16", TYPE_R16)
1012 TYPE("i16imm", TYPE_IMM16)
1014 TYPE("i16mem", TYPE_Mv)
1015 TYPE("i16imm", TYPE_IMMv)
1016 TYPE("i16i8imm", TYPE_IMMv)
1017 TYPE("GR16", TYPE_Rv)
1018 TYPE("i32mem", TYPE_Mv)
1019 TYPE("i32imm", TYPE_IMMv)
1020 TYPE("i32i8imm", TYPE_IMM32)
1021 TYPE("u32u8imm", TYPE_IMM32)
1022 TYPE("GR32", TYPE_Rv)
1023 TYPE("i64mem", TYPE_Mv)
1024 TYPE("i64i32imm", TYPE_IMM64)
1025 TYPE("i64i8imm", TYPE_IMM64)
1026 TYPE("GR64", TYPE_R64)
1027 TYPE("i8mem", TYPE_M8)
1028 TYPE("i8imm", TYPE_IMM8)
1029 TYPE("GR8", TYPE_R8)
1030 TYPE("VR128", TYPE_XMM128)
1031 TYPE("f128mem", TYPE_M128)
1032 TYPE("f256mem", TYPE_M256)
1033 TYPE("FR64", TYPE_XMM64)
1034 TYPE("f64mem", TYPE_M64FP)
1035 TYPE("sdmem", TYPE_M64FP)
1036 TYPE("FR32", TYPE_XMM32)
1037 TYPE("f32mem", TYPE_M32FP)
1038 TYPE("ssmem", TYPE_M32FP)
1039 TYPE("RST", TYPE_ST)
1040 TYPE("i128mem", TYPE_M128)
1041 TYPE("i256mem", TYPE_M256)
1042 TYPE("i64i32imm_pcrel", TYPE_REL64)
1043 TYPE("i16imm_pcrel", TYPE_REL16)
1044 TYPE("i32imm_pcrel", TYPE_REL32)
1045 TYPE("SSECC", TYPE_IMM3)
1046 TYPE("brtarget", TYPE_RELv)
1047 TYPE("uncondbrtarget", TYPE_RELv)
1048 TYPE("brtarget8", TYPE_REL8)
1049 TYPE("f80mem", TYPE_M80FP)
1050 TYPE("lea32mem", TYPE_LEA)
1051 TYPE("lea64_32mem", TYPE_LEA)
1052 TYPE("lea64mem", TYPE_LEA)
1053 TYPE("VR64", TYPE_MM64)
1054 TYPE("i64imm", TYPE_IMMv)
1055 TYPE("opaque32mem", TYPE_M1616)
1056 TYPE("opaque48mem", TYPE_M1632)
1057 TYPE("opaque80mem", TYPE_M1664)
1058 TYPE("opaque512mem", TYPE_M512)
1059 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1060 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1061 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1062 TYPE("offset8", TYPE_MOFFS8)
1063 TYPE("offset16", TYPE_MOFFS16)
1064 TYPE("offset32", TYPE_MOFFS32)
1065 TYPE("offset64", TYPE_MOFFS64)
1066 TYPE("VR256", TYPE_XMM256)
1067 errs() << "Unhandled type string " << s << "\n";
1068 llvm_unreachable("Unhandled type string");
1072 #define ENCODING(str, encoding) if (s == str) return encoding;
1073 OperandEncoding RecognizableInstr::immediateEncodingFromString
1074 (const std::string &s,
1075 bool hasOpSizePrefix) {
1076 if(!hasOpSizePrefix) {
1077 // For instructions without an OpSize prefix, a declared 16-bit register or
1078 // immediate encoding is special.
1079 ENCODING("i16imm", ENCODING_IW)
1081 ENCODING("i32i8imm", ENCODING_IB)
1082 ENCODING("u32u8imm", ENCODING_IB)
1083 ENCODING("SSECC", ENCODING_IB)
1084 ENCODING("i16imm", ENCODING_Iv)
1085 ENCODING("i16i8imm", ENCODING_IB)
1086 ENCODING("i32imm", ENCODING_Iv)
1087 ENCODING("i64i32imm", ENCODING_ID)
1088 ENCODING("i64i8imm", ENCODING_IB)
1089 ENCODING("i8imm", ENCODING_IB)
1090 // This is not a typo. Instructions like BLENDVPD put
1091 // register IDs in 8-bit immediates nowadays.
1092 ENCODING("VR256", ENCODING_IB)
1093 ENCODING("VR128", ENCODING_IB)
1094 errs() << "Unhandled immediate encoding " << s << "\n";
1095 llvm_unreachable("Unhandled immediate encoding");
1098 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1099 (const std::string &s,
1100 bool hasOpSizePrefix) {
1101 ENCODING("GR16", ENCODING_RM)
1102 ENCODING("GR32", ENCODING_RM)
1103 ENCODING("GR64", ENCODING_RM)
1104 ENCODING("GR8", ENCODING_RM)
1105 ENCODING("VR128", ENCODING_RM)
1106 ENCODING("FR64", ENCODING_RM)
1107 ENCODING("FR32", ENCODING_RM)
1108 ENCODING("VR64", ENCODING_RM)
1109 ENCODING("VR256", ENCODING_RM)
1110 errs() << "Unhandled R/M register encoding " << s << "\n";
1111 llvm_unreachable("Unhandled R/M register encoding");
1114 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1115 (const std::string &s,
1116 bool hasOpSizePrefix) {
1117 ENCODING("GR16", ENCODING_REG)
1118 ENCODING("GR32", ENCODING_REG)
1119 ENCODING("GR64", ENCODING_REG)
1120 ENCODING("GR8", ENCODING_REG)
1121 ENCODING("VR128", ENCODING_REG)
1122 ENCODING("FR64", ENCODING_REG)
1123 ENCODING("FR32", ENCODING_REG)
1124 ENCODING("VR64", ENCODING_REG)
1125 ENCODING("SEGMENT_REG", ENCODING_REG)
1126 ENCODING("DEBUG_REG", ENCODING_REG)
1127 ENCODING("CONTROL_REG", ENCODING_REG)
1128 ENCODING("VR256", ENCODING_REG)
1129 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1130 llvm_unreachable("Unhandled reg/opcode register encoding");
1133 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1134 (const std::string &s,
1135 bool hasOpSizePrefix) {
1136 ENCODING("FR32", ENCODING_VVVV)
1137 ENCODING("FR64", ENCODING_VVVV)
1138 ENCODING("VR128", ENCODING_VVVV)
1139 ENCODING("VR256", ENCODING_VVVV)
1140 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1141 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1144 OperandEncoding RecognizableInstr::memoryEncodingFromString
1145 (const std::string &s,
1146 bool hasOpSizePrefix) {
1147 ENCODING("i16mem", ENCODING_RM)
1148 ENCODING("i32mem", ENCODING_RM)
1149 ENCODING("i64mem", ENCODING_RM)
1150 ENCODING("i8mem", ENCODING_RM)
1151 ENCODING("ssmem", ENCODING_RM)
1152 ENCODING("sdmem", ENCODING_RM)
1153 ENCODING("f128mem", ENCODING_RM)
1154 ENCODING("f256mem", ENCODING_RM)
1155 ENCODING("f64mem", ENCODING_RM)
1156 ENCODING("f32mem", ENCODING_RM)
1157 ENCODING("i128mem", ENCODING_RM)
1158 ENCODING("i256mem", ENCODING_RM)
1159 ENCODING("f80mem", ENCODING_RM)
1160 ENCODING("lea32mem", ENCODING_RM)
1161 ENCODING("lea64_32mem", ENCODING_RM)
1162 ENCODING("lea64mem", ENCODING_RM)
1163 ENCODING("opaque32mem", ENCODING_RM)
1164 ENCODING("opaque48mem", ENCODING_RM)
1165 ENCODING("opaque80mem", ENCODING_RM)
1166 ENCODING("opaque512mem", ENCODING_RM)
1167 errs() << "Unhandled memory encoding " << s << "\n";
1168 llvm_unreachable("Unhandled memory encoding");
1171 OperandEncoding RecognizableInstr::relocationEncodingFromString
1172 (const std::string &s,
1173 bool hasOpSizePrefix) {
1174 if(!hasOpSizePrefix) {
1175 // For instructions without an OpSize prefix, a declared 16-bit register or
1176 // immediate encoding is special.
1177 ENCODING("i16imm", ENCODING_IW)
1179 ENCODING("i16imm", ENCODING_Iv)
1180 ENCODING("i16i8imm", ENCODING_IB)
1181 ENCODING("i32imm", ENCODING_Iv)
1182 ENCODING("i32i8imm", ENCODING_IB)
1183 ENCODING("i64i32imm", ENCODING_ID)
1184 ENCODING("i64i8imm", ENCODING_IB)
1185 ENCODING("i8imm", ENCODING_IB)
1186 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1187 ENCODING("i16imm_pcrel", ENCODING_IW)
1188 ENCODING("i32imm_pcrel", ENCODING_ID)
1189 ENCODING("brtarget", ENCODING_Iv)
1190 ENCODING("brtarget8", ENCODING_IB)
1191 ENCODING("i64imm", ENCODING_IO)
1192 ENCODING("offset8", ENCODING_Ia)
1193 ENCODING("offset16", ENCODING_Ia)
1194 ENCODING("offset32", ENCODING_Ia)
1195 ENCODING("offset64", ENCODING_Ia)
1196 errs() << "Unhandled relocation encoding " << s << "\n";
1197 llvm_unreachable("Unhandled relocation encoding");
1200 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1201 (const std::string &s,
1202 bool hasOpSizePrefix) {
1203 ENCODING("RST", ENCODING_I)
1204 ENCODING("GR32", ENCODING_Rv)
1205 ENCODING("GR64", ENCODING_RO)
1206 ENCODING("GR16", ENCODING_Rv)
1207 ENCODING("GR8", ENCODING_RB)
1208 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1209 llvm_unreachable("Unhandled opcode modifier encoding");