1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
54 // A clone of X86 since we can't depend on something that is generated.
70 MRMXr = 14, MRMXm = 15,
71 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
72 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
73 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
74 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
75 #define MAP(from, to) MRM_##from = to,
82 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6,
83 D8 = 7, D9 = 8, DA = 9, DB = 10,
84 DC = 11, DD = 12, DE = 13, DF = 14
88 PS = 1, PD = 2, XS = 3, XD = 4
92 VEX = 1, XOP = 2, EVEX = 3
96 OpSize16 = 1, OpSize32 = 2
100 using namespace X86Disassembler;
102 /// isRegFormat - Indicates whether a particular form requires the Mod field of
103 /// the ModR/M byte to be 0b11.
105 /// @param form - The form of the instruction.
106 /// @return - true if the form implies that Mod must be 0b11, false
108 static bool isRegFormat(uint8_t form) {
109 return (form == X86Local::MRMDestReg ||
110 form == X86Local::MRMSrcReg ||
111 form == X86Local::MRMXr ||
112 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
115 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
116 /// Useful for switch statements and the like.
118 /// @param init - A reference to the BitsInit to be decoded.
119 /// @return - The field, with the first bit in the BitsInit as the lowest
121 static uint8_t byteFromBitsInit(BitsInit &init) {
122 int width = init.getNumBits();
124 assert(width <= 8 && "Field is too large for uint8_t!");
131 for (index = 0; index < width; index++) {
132 if (static_cast<BitInit*>(init.getBit(index))->getValue())
141 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
142 /// name of the field.
144 /// @param rec - The record from which to extract the value.
145 /// @param name - The name of the field in the record.
146 /// @return - The field, as translated by byteFromBitsInit().
147 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
148 BitsInit* bits = rec->getValueAsBitsInit(name);
149 return byteFromBitsInit(*bits);
152 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
153 const CodeGenInstruction &insn,
158 Name = Rec->getName();
159 Spec = &tables.specForUID(UID);
161 if (!Rec->isSubClassOf("X86Inst")) {
162 ShouldBeEmitted = false;
166 OpPrefix = byteFromRec(Rec->getValueAsDef("OpPrefix"), "Value");
167 OpMap = byteFromRec(Rec->getValueAsDef("OpMap"), "Value");
168 Opcode = byteFromRec(Rec, "Opcode");
169 Form = byteFromRec(Rec, "FormBits");
170 Encoding = byteFromRec(Rec->getValueAsDef("OpEnc"), "Value");
172 OpSize = byteFromRec(Rec->getValueAsDef("OpSize"), "Value");
173 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
174 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
175 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
176 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
177 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
178 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
179 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
180 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
181 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
182 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
183 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
184 HasREPPrefix = Rec->getValueAsBit("hasREPPrefix");
185 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
186 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
188 Name = Rec->getName();
189 AsmString = Rec->getValueAsString("AsmString");
191 Operands = &insn.Operands.OperandList;
193 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
195 // Check for 64-bit inst which does not require REX
198 // FIXME: Is there some better way to check for In64BitMode?
199 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
200 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
201 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
202 Predicates[i]->getName().find("In32Bit") != Name.npos) {
206 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
212 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
213 ShouldBeEmitted = false;
217 // Special case since there is no attribute class for 64-bit and VEX
218 if (Name == "VMASKMOVDQU64") {
219 ShouldBeEmitted = false;
223 ShouldBeEmitted = true;
226 void RecognizableInstr::processInstr(DisassemblerTables &tables,
227 const CodeGenInstruction &insn,
230 // Ignore "asm parser only" instructions.
231 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
234 RecognizableInstr recogInstr(tables, insn, uid);
236 if (recogInstr.shouldBeEmitted()) {
237 recogInstr.emitInstructionSpecifier();
238 recogInstr.emitDecodePath(tables);
242 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
243 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
244 (HasEVEX_KZ ? n##_KZ : \
245 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
247 InstructionContext RecognizableInstr::insnContext() const {
248 InstructionContext insnContext;
250 if (Encoding == X86Local::EVEX) {
251 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
252 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
253 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
256 if (HasVEX_LPrefix && HasVEX_WPrefix) {
257 if (OpPrefix == X86Local::PD)
258 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
259 else if (OpPrefix == X86Local::XS)
260 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
261 else if (OpPrefix == X86Local::XD)
262 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
263 else if (OpPrefix == X86Local::PS)
264 insnContext = EVEX_KB(IC_EVEX_L_W);
266 errs() << "Instruction does not use a prefix: " << Name << "\n";
267 llvm_unreachable("Invalid prefix");
269 } else if (HasVEX_LPrefix) {
271 if (OpPrefix == X86Local::PD)
272 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
273 else if (OpPrefix == X86Local::XS)
274 insnContext = EVEX_KB(IC_EVEX_L_XS);
275 else if (OpPrefix == X86Local::XD)
276 insnContext = EVEX_KB(IC_EVEX_L_XD);
277 else if (OpPrefix == X86Local::PS)
278 insnContext = EVEX_KB(IC_EVEX_L);
280 errs() << "Instruction does not use a prefix: " << Name << "\n";
281 llvm_unreachable("Invalid prefix");
284 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
286 if (OpPrefix == X86Local::PD)
287 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
288 else if (OpPrefix == X86Local::XS)
289 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
290 else if (OpPrefix == X86Local::XD)
291 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
292 else if (OpPrefix == X86Local::PS)
293 insnContext = EVEX_KB(IC_EVEX_L2_W);
295 errs() << "Instruction does not use a prefix: " << Name << "\n";
296 llvm_unreachable("Invalid prefix");
298 } else if (HasEVEX_L2Prefix) {
300 if (OpPrefix == X86Local::PD)
301 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
302 else if (OpPrefix == X86Local::XD)
303 insnContext = EVEX_KB(IC_EVEX_L2_XD);
304 else if (OpPrefix == X86Local::XS)
305 insnContext = EVEX_KB(IC_EVEX_L2_XS);
306 else if (OpPrefix == X86Local::PS)
307 insnContext = EVEX_KB(IC_EVEX_L2);
309 errs() << "Instruction does not use a prefix: " << Name << "\n";
310 llvm_unreachable("Invalid prefix");
313 else if (HasVEX_WPrefix) {
315 if (OpPrefix == X86Local::PD)
316 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
317 else if (OpPrefix == X86Local::XS)
318 insnContext = EVEX_KB(IC_EVEX_W_XS);
319 else if (OpPrefix == X86Local::XD)
320 insnContext = EVEX_KB(IC_EVEX_W_XD);
321 else if (OpPrefix == X86Local::PS)
322 insnContext = EVEX_KB(IC_EVEX_W);
324 errs() << "Instruction does not use a prefix: " << Name << "\n";
325 llvm_unreachable("Invalid prefix");
329 else if (OpPrefix == X86Local::PD)
330 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
331 else if (OpPrefix == X86Local::XD)
332 insnContext = EVEX_KB(IC_EVEX_XD);
333 else if (OpPrefix == X86Local::XS)
334 insnContext = EVEX_KB(IC_EVEX_XS);
336 insnContext = EVEX_KB(IC_EVEX);
338 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
339 if (HasVEX_LPrefix && HasVEX_WPrefix) {
340 if (OpPrefix == X86Local::PD)
341 insnContext = IC_VEX_L_W_OPSIZE;
342 else if (OpPrefix == X86Local::XS)
343 insnContext = IC_VEX_L_W_XS;
344 else if (OpPrefix == X86Local::XD)
345 insnContext = IC_VEX_L_W_XD;
346 else if (OpPrefix == X86Local::PS)
347 insnContext = IC_VEX_L_W;
349 errs() << "Instruction does not use a prefix: " << Name << "\n";
350 llvm_unreachable("Invalid prefix");
352 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
353 insnContext = IC_VEX_L_OPSIZE;
354 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
355 insnContext = IC_VEX_W_OPSIZE;
356 else if (OpPrefix == X86Local::PD)
357 insnContext = IC_VEX_OPSIZE;
358 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
359 insnContext = IC_VEX_L_XS;
360 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
361 insnContext = IC_VEX_L_XD;
362 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
363 insnContext = IC_VEX_W_XS;
364 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
365 insnContext = IC_VEX_W_XD;
366 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
367 insnContext = IC_VEX_W;
368 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
369 insnContext = IC_VEX_L;
370 else if (OpPrefix == X86Local::XD)
371 insnContext = IC_VEX_XD;
372 else if (OpPrefix == X86Local::XS)
373 insnContext = IC_VEX_XS;
374 else if (OpPrefix == X86Local::PS)
375 insnContext = IC_VEX;
377 errs() << "Instruction does not use a prefix: " << Name << "\n";
378 llvm_unreachable("Invalid prefix");
380 } else if (Is64Bit || HasREX_WPrefix) {
381 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
382 insnContext = IC_64BIT_REXW_OPSIZE;
383 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
384 insnContext = IC_64BIT_XD_OPSIZE;
385 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
386 insnContext = IC_64BIT_XS_OPSIZE;
387 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
388 insnContext = IC_64BIT_OPSIZE;
389 else if (HasAdSizePrefix)
390 insnContext = IC_64BIT_ADSIZE;
391 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
392 insnContext = IC_64BIT_REXW_XS;
393 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
394 insnContext = IC_64BIT_REXW_XD;
395 else if (OpPrefix == X86Local::XD)
396 insnContext = IC_64BIT_XD;
397 else if (OpPrefix == X86Local::XS)
398 insnContext = IC_64BIT_XS;
399 else if (HasREX_WPrefix)
400 insnContext = IC_64BIT_REXW;
402 insnContext = IC_64BIT;
404 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
405 insnContext = IC_XD_OPSIZE;
406 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
407 insnContext = IC_XS_OPSIZE;
408 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
409 insnContext = IC_OPSIZE;
410 else if (HasAdSizePrefix)
411 insnContext = IC_ADSIZE;
412 else if (OpPrefix == X86Local::XD)
414 else if (OpPrefix == X86Local::XS || HasREPPrefix)
423 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
424 unsigned &physicalOperandIndex,
425 unsigned &numPhysicalOperands,
426 const unsigned *operandMapping,
427 OperandEncoding (*encodingFromString)
431 if (physicalOperandIndex >= numPhysicalOperands)
434 assert(physicalOperandIndex < numPhysicalOperands);
437 while (operandMapping[operandIndex] != operandIndex) {
438 Spec->operands[operandIndex].encoding = ENCODING_DUP;
439 Spec->operands[operandIndex].type =
440 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
444 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
446 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
448 Spec->operands[operandIndex].type = typeFromString(typeName,
449 HasREX_WPrefix, OpSize);
452 ++physicalOperandIndex;
455 void RecognizableInstr::emitInstructionSpecifier() {
458 Spec->insnContext = insnContext();
460 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
462 unsigned numOperands = OperandList.size();
463 unsigned numPhysicalOperands = 0;
465 // operandMapping maps from operands in OperandList to their originals.
466 // If operandMapping[i] != i, then the entry is a duplicate.
467 unsigned operandMapping[X86_MAX_OPERANDS];
468 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
470 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
471 if (OperandList[operandIndex].Constraints.size()) {
472 const CGIOperandList::ConstraintInfo &Constraint =
473 OperandList[operandIndex].Constraints[0];
474 if (Constraint.isTied()) {
475 operandMapping[operandIndex] = operandIndex;
476 operandMapping[Constraint.getTiedOperand()] = operandIndex;
478 ++numPhysicalOperands;
479 operandMapping[operandIndex] = operandIndex;
482 ++numPhysicalOperands;
483 operandMapping[operandIndex] = operandIndex;
487 #define HANDLE_OPERAND(class) \
488 handleOperand(false, \
490 physicalOperandIndex, \
491 numPhysicalOperands, \
493 class##EncodingFromString);
495 #define HANDLE_OPTIONAL(class) \
496 handleOperand(true, \
498 physicalOperandIndex, \
499 numPhysicalOperands, \
501 class##EncodingFromString);
503 // operandIndex should always be < numOperands
504 unsigned operandIndex = 0;
505 // physicalOperandIndex should always be < numPhysicalOperands
506 unsigned physicalOperandIndex = 0;
509 default: llvm_unreachable("Unhandled form");
510 case X86Local::RawFrmSrc:
511 HANDLE_OPERAND(relocation);
513 case X86Local::RawFrmDst:
514 HANDLE_OPERAND(relocation);
516 case X86Local::RawFrmDstSrc:
517 HANDLE_OPERAND(relocation);
518 HANDLE_OPERAND(relocation);
520 case X86Local::RawFrm:
521 // Operand 1 (optional) is an address or immediate.
522 // Operand 2 (optional) is an immediate.
523 assert(numPhysicalOperands <= 2 &&
524 "Unexpected number of operands for RawFrm");
525 HANDLE_OPTIONAL(relocation)
526 HANDLE_OPTIONAL(immediate)
528 case X86Local::RawFrmMemOffs:
529 // Operand 1 is an address.
530 HANDLE_OPERAND(relocation);
532 case X86Local::AddRegFrm:
533 // Operand 1 is added to the opcode.
534 // Operand 2 (optional) is an address.
535 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
536 "Unexpected number of operands for AddRegFrm");
537 HANDLE_OPERAND(opcodeModifier)
538 HANDLE_OPTIONAL(relocation)
540 case X86Local::MRMDestReg:
541 // Operand 1 is a register operand in the R/M field.
542 // Operand 2 is a register operand in the Reg/Opcode field.
543 // - In AVX, there is a register operand in the VEX.vvvv field here -
544 // Operand 3 (optional) is an immediate.
546 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
547 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
549 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
550 "Unexpected number of operands for MRMDestRegFrm");
552 HANDLE_OPERAND(rmRegister)
555 // FIXME: In AVX, the register below becomes the one encoded
556 // in ModRMVEX and the one above the one in the VEX.VVVV field
557 HANDLE_OPERAND(vvvvRegister)
559 HANDLE_OPERAND(roRegister)
560 HANDLE_OPTIONAL(immediate)
562 case X86Local::MRMDestMem:
563 // Operand 1 is a memory operand (possibly SIB-extended)
564 // Operand 2 is a register operand in the Reg/Opcode field.
565 // - In AVX, there is a register operand in the VEX.vvvv field here -
566 // Operand 3 (optional) is an immediate.
568 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
569 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
571 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
572 "Unexpected number of operands for MRMDestMemFrm");
573 HANDLE_OPERAND(memory)
576 HANDLE_OPERAND(writemaskRegister)
579 // FIXME: In AVX, the register below becomes the one encoded
580 // in ModRMVEX and the one above the one in the VEX.VVVV field
581 HANDLE_OPERAND(vvvvRegister)
583 HANDLE_OPERAND(roRegister)
584 HANDLE_OPTIONAL(immediate)
586 case X86Local::MRMSrcReg:
587 // Operand 1 is a register operand in the Reg/Opcode field.
588 // Operand 2 is a register operand in the R/M field.
589 // - In AVX, there is a register operand in the VEX.vvvv field here -
590 // Operand 3 (optional) is an immediate.
591 // Operand 4 (optional) is an immediate.
593 if (HasVEX_4V || HasVEX_4VOp3)
594 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
595 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
597 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
598 "Unexpected number of operands for MRMSrcRegFrm");
600 HANDLE_OPERAND(roRegister)
603 HANDLE_OPERAND(writemaskRegister)
606 // FIXME: In AVX, the register below becomes the one encoded
607 // in ModRMVEX and the one above the one in the VEX.VVVV field
608 HANDLE_OPERAND(vvvvRegister)
611 HANDLE_OPERAND(immediate)
613 HANDLE_OPERAND(rmRegister)
616 HANDLE_OPERAND(vvvvRegister)
618 if (!HasMemOp4Prefix)
619 HANDLE_OPTIONAL(immediate)
620 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
621 HANDLE_OPTIONAL(immediate)
623 case X86Local::MRMSrcMem:
624 // Operand 1 is a register operand in the Reg/Opcode field.
625 // Operand 2 is a memory operand (possibly SIB-extended)
626 // - In AVX, there is a register operand in the VEX.vvvv field here -
627 // Operand 3 (optional) is an immediate.
629 if (HasVEX_4V || HasVEX_4VOp3)
630 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
631 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
633 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
634 "Unexpected number of operands for MRMSrcMemFrm");
636 HANDLE_OPERAND(roRegister)
639 HANDLE_OPERAND(writemaskRegister)
642 // FIXME: In AVX, the register below becomes the one encoded
643 // in ModRMVEX and the one above the one in the VEX.VVVV field
644 HANDLE_OPERAND(vvvvRegister)
647 HANDLE_OPERAND(immediate)
649 HANDLE_OPERAND(memory)
652 HANDLE_OPERAND(vvvvRegister)
654 if (!HasMemOp4Prefix)
655 HANDLE_OPTIONAL(immediate)
656 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
658 case X86Local::MRMXr:
659 case X86Local::MRM0r:
660 case X86Local::MRM1r:
661 case X86Local::MRM2r:
662 case X86Local::MRM3r:
663 case X86Local::MRM4r:
664 case X86Local::MRM5r:
665 case X86Local::MRM6r:
666 case X86Local::MRM7r:
668 // Operand 1 is a register operand in the R/M field.
669 // Operand 2 (optional) is an immediate or relocation.
670 // Operand 3 (optional) is an immediate.
671 unsigned kOp = (HasEVEX_K) ? 1:0;
672 unsigned Op4v = (HasVEX_4V) ? 1:0;
673 if (numPhysicalOperands > 3 + kOp + Op4v)
674 llvm_unreachable("Unexpected number of operands for MRMnr");
677 HANDLE_OPERAND(vvvvRegister)
680 HANDLE_OPERAND(writemaskRegister)
681 HANDLE_OPTIONAL(rmRegister)
682 HANDLE_OPTIONAL(relocation)
683 HANDLE_OPTIONAL(immediate)
685 case X86Local::MRMXm:
686 case X86Local::MRM0m:
687 case X86Local::MRM1m:
688 case X86Local::MRM2m:
689 case X86Local::MRM3m:
690 case X86Local::MRM4m:
691 case X86Local::MRM5m:
692 case X86Local::MRM6m:
693 case X86Local::MRM7m:
695 // Operand 1 is a memory operand (possibly SIB-extended)
696 // Operand 2 (optional) is an immediate or relocation.
697 unsigned kOp = (HasEVEX_K) ? 1:0;
698 unsigned Op4v = (HasVEX_4V) ? 1:0;
699 if (numPhysicalOperands < 1 + kOp + Op4v ||
700 numPhysicalOperands > 2 + kOp + Op4v)
701 llvm_unreachable("Unexpected number of operands for MRMnm");
704 HANDLE_OPERAND(vvvvRegister)
706 HANDLE_OPERAND(writemaskRegister)
707 HANDLE_OPERAND(memory)
708 HANDLE_OPTIONAL(relocation)
710 case X86Local::RawFrmImm8:
711 // operand 1 is a 16-bit immediate
712 // operand 2 is an 8-bit immediate
713 assert(numPhysicalOperands == 2 &&
714 "Unexpected number of operands for X86Local::RawFrmImm8");
715 HANDLE_OPERAND(immediate)
716 HANDLE_OPERAND(immediate)
718 case X86Local::RawFrmImm16:
719 // operand 1 is a 16-bit immediate
720 // operand 2 is a 16-bit immediate
721 HANDLE_OPERAND(immediate)
722 HANDLE_OPERAND(immediate)
724 case X86Local::MRM_F8:
725 if (Opcode == 0xc6) {
726 assert(numPhysicalOperands == 1 &&
727 "Unexpected number of operands for X86Local::MRM_F8");
728 HANDLE_OPERAND(immediate)
729 } else if (Opcode == 0xc7) {
730 assert(numPhysicalOperands == 1 &&
731 "Unexpected number of operands for X86Local::MRM_F8");
732 HANDLE_OPERAND(relocation)
735 case X86Local::MRM_C0:
736 case X86Local::MRM_C1:
737 case X86Local::MRM_C2:
738 case X86Local::MRM_C3:
739 case X86Local::MRM_C4:
740 case X86Local::MRM_C8:
741 case X86Local::MRM_C9:
742 case X86Local::MRM_CA:
743 case X86Local::MRM_CB:
744 case X86Local::MRM_E8:
745 case X86Local::MRM_F0:
746 case X86Local::MRM_F9:
747 case X86Local::MRM_D0:
748 case X86Local::MRM_D1:
749 case X86Local::MRM_D4:
750 case X86Local::MRM_D5:
751 case X86Local::MRM_D6:
752 case X86Local::MRM_D8:
753 case X86Local::MRM_D9:
754 case X86Local::MRM_DA:
755 case X86Local::MRM_DB:
756 case X86Local::MRM_DC:
757 case X86Local::MRM_DD:
758 case X86Local::MRM_DE:
759 case X86Local::MRM_DF:
760 case X86Local::MRM_E0:
765 #undef HANDLE_OPERAND
766 #undef HANDLE_OPTIONAL
769 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
770 // Special cases where the LLVM tables are not complete
772 #define MAP(from, to) \
773 case X86Local::MRM_##from: \
774 filter = new ExactFilter(0x##from); \
777 OpcodeType opcodeType = (OpcodeType)-1;
779 ModRMFilter* filter = NULL;
780 uint8_t opcodeToSet = 0;
783 default: llvm_unreachable("Invalid map!");
792 default: llvm_unreachable("Unexpected map!");
793 case X86Local::OB: opcodeType = ONEBYTE; break;
794 case X86Local::TB: opcodeType = TWOBYTE; break;
795 case X86Local::T8: opcodeType = THREEBYTE_38; break;
796 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
797 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
798 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
799 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
804 filter = new DumbFilter();
806 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
807 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
808 case X86Local::MRMXr: case X86Local::MRMXm:
809 filter = new ModFilter(isRegFormat(Form));
811 case X86Local::MRM0r: case X86Local::MRM1r:
812 case X86Local::MRM2r: case X86Local::MRM3r:
813 case X86Local::MRM4r: case X86Local::MRM5r:
814 case X86Local::MRM6r: case X86Local::MRM7r:
815 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
817 case X86Local::MRM0m: case X86Local::MRM1m:
818 case X86Local::MRM2m: case X86Local::MRM3m:
819 case X86Local::MRM4m: case X86Local::MRM5m:
820 case X86Local::MRM6m: case X86Local::MRM7m:
821 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
826 opcodeToSet = Opcode;
836 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
837 assert(Form == X86Local::RawFrm);
838 opcodeType = ONEBYTE;
839 filter = new ExactFilter(Opcode);
840 opcodeToSet = 0xd8 + (OpMap - X86Local::D8);
844 assert(opcodeType != (OpcodeType)-1 &&
845 "Opcode type not set");
846 assert(filter && "Filter not set");
848 if (Form == X86Local::AddRegFrm) {
849 assert(((opcodeToSet & 7) == 0) &&
850 "ADDREG_FRM opcode not aligned");
852 uint8_t currentOpcode;
854 for (currentOpcode = opcodeToSet;
855 currentOpcode < opcodeToSet + 8;
857 tables.setTableFields(opcodeType,
861 UID, Is32Bit, IgnoresVEX_L);
863 tables.setTableFields(opcodeType,
867 UID, Is32Bit, IgnoresVEX_L);
875 #define TYPE(str, type) if (s == str) return type;
876 OperandType RecognizableInstr::typeFromString(const std::string &s,
880 // For instructions with a REX_W prefix, a declared 32-bit register encoding
882 TYPE("GR32", TYPE_R32)
884 if(OpSize == X86Local::OpSize16) {
885 // For OpSize16 instructions, a declared 16-bit register or
886 // immediate encoding is special.
887 TYPE("GR16", TYPE_Rv)
888 TYPE("i16imm", TYPE_IMMv)
889 } else if(OpSize == X86Local::OpSize32) {
890 // For OpSize32 instructions, a declared 32-bit register or
891 // immediate encoding is special.
892 TYPE("GR32", TYPE_Rv)
894 TYPE("i16mem", TYPE_Mv)
895 TYPE("i16imm", TYPE_IMM16)
896 TYPE("i16i8imm", TYPE_IMMv)
897 TYPE("GR16", TYPE_R16)
898 TYPE("i32mem", TYPE_Mv)
899 TYPE("i32imm", TYPE_IMMv)
900 TYPE("i32i8imm", TYPE_IMM32)
901 TYPE("u32u8imm", TYPE_IMM32)
902 TYPE("GR32", TYPE_R32)
903 TYPE("GR32orGR64", TYPE_R32)
904 TYPE("i64mem", TYPE_Mv)
905 TYPE("i64i32imm", TYPE_IMM64)
906 TYPE("i64i8imm", TYPE_IMM64)
907 TYPE("GR64", TYPE_R64)
908 TYPE("i8mem", TYPE_M8)
909 TYPE("i8imm", TYPE_IMM8)
911 TYPE("VR128", TYPE_XMM128)
912 TYPE("VR128X", TYPE_XMM128)
913 TYPE("f128mem", TYPE_M128)
914 TYPE("f256mem", TYPE_M256)
915 TYPE("f512mem", TYPE_M512)
916 TYPE("FR64", TYPE_XMM64)
917 TYPE("FR64X", TYPE_XMM64)
918 TYPE("f64mem", TYPE_M64FP)
919 TYPE("sdmem", TYPE_M64FP)
920 TYPE("FR32", TYPE_XMM32)
921 TYPE("FR32X", TYPE_XMM32)
922 TYPE("f32mem", TYPE_M32FP)
923 TYPE("ssmem", TYPE_M32FP)
925 TYPE("i128mem", TYPE_M128)
926 TYPE("i256mem", TYPE_M256)
927 TYPE("i512mem", TYPE_M512)
928 TYPE("i64i32imm_pcrel", TYPE_REL64)
929 TYPE("i16imm_pcrel", TYPE_REL16)
930 TYPE("i32imm_pcrel", TYPE_REL32)
931 TYPE("SSECC", TYPE_IMM3)
932 TYPE("AVXCC", TYPE_IMM5)
933 TYPE("AVX512RC", TYPE_IMM32)
934 TYPE("brtarget", TYPE_RELv)
935 TYPE("uncondbrtarget", TYPE_RELv)
936 TYPE("brtarget8", TYPE_REL8)
937 TYPE("f80mem", TYPE_M80FP)
938 TYPE("lea32mem", TYPE_LEA)
939 TYPE("lea64_32mem", TYPE_LEA)
940 TYPE("lea64mem", TYPE_LEA)
941 TYPE("VR64", TYPE_MM64)
942 TYPE("i64imm", TYPE_IMMv)
943 TYPE("opaque32mem", TYPE_M1616)
944 TYPE("opaque48mem", TYPE_M1632)
945 TYPE("opaque80mem", TYPE_M1664)
946 TYPE("opaque512mem", TYPE_M512)
947 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
948 TYPE("DEBUG_REG", TYPE_DEBUGREG)
949 TYPE("CONTROL_REG", TYPE_CONTROLREG)
950 TYPE("srcidx8", TYPE_SRCIDX8)
951 TYPE("srcidx16", TYPE_SRCIDX16)
952 TYPE("srcidx32", TYPE_SRCIDX32)
953 TYPE("srcidx64", TYPE_SRCIDX64)
954 TYPE("dstidx8", TYPE_DSTIDX8)
955 TYPE("dstidx16", TYPE_DSTIDX16)
956 TYPE("dstidx32", TYPE_DSTIDX32)
957 TYPE("dstidx64", TYPE_DSTIDX64)
958 TYPE("offset8", TYPE_MOFFS8)
959 TYPE("offset16", TYPE_MOFFS16)
960 TYPE("offset32", TYPE_MOFFS32)
961 TYPE("offset64", TYPE_MOFFS64)
962 TYPE("VR256", TYPE_XMM256)
963 TYPE("VR256X", TYPE_XMM256)
964 TYPE("VR512", TYPE_XMM512)
965 TYPE("VK1", TYPE_VK1)
966 TYPE("VK1WM", TYPE_VK1)
967 TYPE("VK8", TYPE_VK8)
968 TYPE("VK8WM", TYPE_VK8)
969 TYPE("VK16", TYPE_VK16)
970 TYPE("VK16WM", TYPE_VK16)
971 TYPE("GR16_NOAX", TYPE_Rv)
972 TYPE("GR32_NOAX", TYPE_Rv)
973 TYPE("GR64_NOAX", TYPE_R64)
974 TYPE("vx32mem", TYPE_M32)
975 TYPE("vy32mem", TYPE_M32)
976 TYPE("vz32mem", TYPE_M32)
977 TYPE("vx64mem", TYPE_M64)
978 TYPE("vy64mem", TYPE_M64)
979 TYPE("vy64xmem", TYPE_M64)
980 TYPE("vz64mem", TYPE_M64)
981 errs() << "Unhandled type string " << s << "\n";
982 llvm_unreachable("Unhandled type string");
986 #define ENCODING(str, encoding) if (s == str) return encoding;
988 RecognizableInstr::immediateEncodingFromString(const std::string &s,
990 if(OpSize != X86Local::OpSize16) {
991 // For instructions without an OpSize prefix, a declared 16-bit register or
992 // immediate encoding is special.
993 ENCODING("i16imm", ENCODING_IW)
995 ENCODING("i32i8imm", ENCODING_IB)
996 ENCODING("u32u8imm", ENCODING_IB)
997 ENCODING("SSECC", ENCODING_IB)
998 ENCODING("AVXCC", ENCODING_IB)
999 ENCODING("AVX512RC", ENCODING_IB)
1000 ENCODING("i16imm", ENCODING_Iv)
1001 ENCODING("i16i8imm", ENCODING_IB)
1002 ENCODING("i32imm", ENCODING_Iv)
1003 ENCODING("i64i32imm", ENCODING_ID)
1004 ENCODING("i64i8imm", ENCODING_IB)
1005 ENCODING("i8imm", ENCODING_IB)
1006 // This is not a typo. Instructions like BLENDVPD put
1007 // register IDs in 8-bit immediates nowadays.
1008 ENCODING("FR32", ENCODING_IB)
1009 ENCODING("FR64", ENCODING_IB)
1010 ENCODING("VR128", ENCODING_IB)
1011 ENCODING("VR256", ENCODING_IB)
1012 ENCODING("FR32X", ENCODING_IB)
1013 ENCODING("FR64X", ENCODING_IB)
1014 ENCODING("VR128X", ENCODING_IB)
1015 ENCODING("VR256X", ENCODING_IB)
1016 ENCODING("VR512", ENCODING_IB)
1017 errs() << "Unhandled immediate encoding " << s << "\n";
1018 llvm_unreachable("Unhandled immediate encoding");
1022 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1024 ENCODING("RST", ENCODING_FP)
1025 ENCODING("GR16", ENCODING_RM)
1026 ENCODING("GR32", ENCODING_RM)
1027 ENCODING("GR32orGR64", ENCODING_RM)
1028 ENCODING("GR64", ENCODING_RM)
1029 ENCODING("GR8", ENCODING_RM)
1030 ENCODING("VR128", ENCODING_RM)
1031 ENCODING("VR128X", ENCODING_RM)
1032 ENCODING("FR64", ENCODING_RM)
1033 ENCODING("FR32", ENCODING_RM)
1034 ENCODING("FR64X", ENCODING_RM)
1035 ENCODING("FR32X", ENCODING_RM)
1036 ENCODING("VR64", ENCODING_RM)
1037 ENCODING("VR256", ENCODING_RM)
1038 ENCODING("VR256X", ENCODING_RM)
1039 ENCODING("VR512", ENCODING_RM)
1040 ENCODING("VK1", ENCODING_RM)
1041 ENCODING("VK8", ENCODING_RM)
1042 ENCODING("VK16", ENCODING_RM)
1043 errs() << "Unhandled R/M register encoding " << s << "\n";
1044 llvm_unreachable("Unhandled R/M register encoding");
1048 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1050 ENCODING("GR16", ENCODING_REG)
1051 ENCODING("GR32", ENCODING_REG)
1052 ENCODING("GR32orGR64", ENCODING_REG)
1053 ENCODING("GR64", ENCODING_REG)
1054 ENCODING("GR8", ENCODING_REG)
1055 ENCODING("VR128", ENCODING_REG)
1056 ENCODING("FR64", ENCODING_REG)
1057 ENCODING("FR32", ENCODING_REG)
1058 ENCODING("VR64", ENCODING_REG)
1059 ENCODING("SEGMENT_REG", ENCODING_REG)
1060 ENCODING("DEBUG_REG", ENCODING_REG)
1061 ENCODING("CONTROL_REG", ENCODING_REG)
1062 ENCODING("VR256", ENCODING_REG)
1063 ENCODING("VR256X", ENCODING_REG)
1064 ENCODING("VR128X", ENCODING_REG)
1065 ENCODING("FR64X", ENCODING_REG)
1066 ENCODING("FR32X", ENCODING_REG)
1067 ENCODING("VR512", ENCODING_REG)
1068 ENCODING("VK1", ENCODING_REG)
1069 ENCODING("VK8", ENCODING_REG)
1070 ENCODING("VK16", ENCODING_REG)
1071 ENCODING("VK1WM", ENCODING_REG)
1072 ENCODING("VK8WM", ENCODING_REG)
1073 ENCODING("VK16WM", ENCODING_REG)
1074 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1075 llvm_unreachable("Unhandled reg/opcode register encoding");
1079 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1081 ENCODING("GR32", ENCODING_VVVV)
1082 ENCODING("GR64", ENCODING_VVVV)
1083 ENCODING("FR32", ENCODING_VVVV)
1084 ENCODING("FR64", ENCODING_VVVV)
1085 ENCODING("VR128", ENCODING_VVVV)
1086 ENCODING("VR256", ENCODING_VVVV)
1087 ENCODING("FR32X", ENCODING_VVVV)
1088 ENCODING("FR64X", ENCODING_VVVV)
1089 ENCODING("VR128X", ENCODING_VVVV)
1090 ENCODING("VR256X", ENCODING_VVVV)
1091 ENCODING("VR512", ENCODING_VVVV)
1092 ENCODING("VK1", ENCODING_VVVV)
1093 ENCODING("VK8", ENCODING_VVVV)
1094 ENCODING("VK16", ENCODING_VVVV)
1095 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1096 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1100 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1102 ENCODING("VK1WM", ENCODING_WRITEMASK)
1103 ENCODING("VK8WM", ENCODING_WRITEMASK)
1104 ENCODING("VK16WM", ENCODING_WRITEMASK)
1105 errs() << "Unhandled mask register encoding " << s << "\n";
1106 llvm_unreachable("Unhandled mask register encoding");
1110 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1112 ENCODING("i16mem", ENCODING_RM)
1113 ENCODING("i32mem", ENCODING_RM)
1114 ENCODING("i64mem", ENCODING_RM)
1115 ENCODING("i8mem", ENCODING_RM)
1116 ENCODING("ssmem", ENCODING_RM)
1117 ENCODING("sdmem", ENCODING_RM)
1118 ENCODING("f128mem", ENCODING_RM)
1119 ENCODING("f256mem", ENCODING_RM)
1120 ENCODING("f512mem", ENCODING_RM)
1121 ENCODING("f64mem", ENCODING_RM)
1122 ENCODING("f32mem", ENCODING_RM)
1123 ENCODING("i128mem", ENCODING_RM)
1124 ENCODING("i256mem", ENCODING_RM)
1125 ENCODING("i512mem", ENCODING_RM)
1126 ENCODING("f80mem", ENCODING_RM)
1127 ENCODING("lea32mem", ENCODING_RM)
1128 ENCODING("lea64_32mem", ENCODING_RM)
1129 ENCODING("lea64mem", ENCODING_RM)
1130 ENCODING("opaque32mem", ENCODING_RM)
1131 ENCODING("opaque48mem", ENCODING_RM)
1132 ENCODING("opaque80mem", ENCODING_RM)
1133 ENCODING("opaque512mem", ENCODING_RM)
1134 ENCODING("vx32mem", ENCODING_RM)
1135 ENCODING("vy32mem", ENCODING_RM)
1136 ENCODING("vz32mem", ENCODING_RM)
1137 ENCODING("vx64mem", ENCODING_RM)
1138 ENCODING("vy64mem", ENCODING_RM)
1139 ENCODING("vy64xmem", ENCODING_RM)
1140 ENCODING("vz64mem", ENCODING_RM)
1141 errs() << "Unhandled memory encoding " << s << "\n";
1142 llvm_unreachable("Unhandled memory encoding");
1146 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1148 if(OpSize != X86Local::OpSize16) {
1149 // For instructions without an OpSize prefix, a declared 16-bit register or
1150 // immediate encoding is special.
1151 ENCODING("i16imm", ENCODING_IW)
1153 ENCODING("i16imm", ENCODING_Iv)
1154 ENCODING("i16i8imm", ENCODING_IB)
1155 ENCODING("i32imm", ENCODING_Iv)
1156 ENCODING("i32i8imm", ENCODING_IB)
1157 ENCODING("i64i32imm", ENCODING_ID)
1158 ENCODING("i64i8imm", ENCODING_IB)
1159 ENCODING("i8imm", ENCODING_IB)
1160 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1161 ENCODING("i16imm_pcrel", ENCODING_IW)
1162 ENCODING("i32imm_pcrel", ENCODING_ID)
1163 ENCODING("brtarget", ENCODING_Iv)
1164 ENCODING("brtarget8", ENCODING_IB)
1165 ENCODING("i64imm", ENCODING_IO)
1166 ENCODING("offset8", ENCODING_Ia)
1167 ENCODING("offset16", ENCODING_Ia)
1168 ENCODING("offset32", ENCODING_Ia)
1169 ENCODING("offset64", ENCODING_Ia)
1170 ENCODING("srcidx8", ENCODING_SI)
1171 ENCODING("srcidx16", ENCODING_SI)
1172 ENCODING("srcidx32", ENCODING_SI)
1173 ENCODING("srcidx64", ENCODING_SI)
1174 ENCODING("dstidx8", ENCODING_DI)
1175 ENCODING("dstidx16", ENCODING_DI)
1176 ENCODING("dstidx32", ENCODING_DI)
1177 ENCODING("dstidx64", ENCODING_DI)
1178 errs() << "Unhandled relocation encoding " << s << "\n";
1179 llvm_unreachable("Unhandled relocation encoding");
1183 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1185 ENCODING("GR32", ENCODING_Rv)
1186 ENCODING("GR64", ENCODING_RO)
1187 ENCODING("GR16", ENCODING_Rv)
1188 ENCODING("GR8", ENCODING_RB)
1189 ENCODING("GR16_NOAX", ENCODING_Rv)
1190 ENCODING("GR32_NOAX", ENCODING_Rv)
1191 ENCODING("GR64_NOAX", ENCODING_RO)
1192 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1193 llvm_unreachable("Unhandled opcode modifier encoding");