1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
50 // A clone of X86 since we can't depend on something that is generated.
60 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
61 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
62 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
63 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
67 #define MAP(from, to) MRM_##from = to,
76 D8 = 3, D9 = 4, DA = 5, DB = 6,
77 DC = 7, DD = 8, DE = 9, DF = 10,
80 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
84 // If rows are added to the opcode extension tables, then corresponding entries
85 // must be added here.
87 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
88 // that byte to ONE_BYTE_EXTENSION_TABLES.
90 // If the row corresponds to two bytes where the first is 0f, add an entry for
91 // the second byte to TWO_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to some other set of bytes, you will need to modify
94 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
95 // to the X86 TD files, except in two cases: if the first two bytes of such a
96 // new combination are 0f 38 or 0f 3a, you just have to add maps called
97 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
98 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
99 // in RecognizableInstr::emitDecodePath().
101 #define ONE_BYTE_EXTENSION_TABLES \
102 EXTENSION_TABLE(80) \
103 EXTENSION_TABLE(81) \
104 EXTENSION_TABLE(82) \
105 EXTENSION_TABLE(83) \
106 EXTENSION_TABLE(8f) \
107 EXTENSION_TABLE(c0) \
108 EXTENSION_TABLE(c1) \
109 EXTENSION_TABLE(c6) \
110 EXTENSION_TABLE(c7) \
111 EXTENSION_TABLE(d0) \
112 EXTENSION_TABLE(d1) \
113 EXTENSION_TABLE(d2) \
114 EXTENSION_TABLE(d3) \
115 EXTENSION_TABLE(f6) \
116 EXTENSION_TABLE(f7) \
117 EXTENSION_TABLE(fe) \
120 #define TWO_BYTE_EXTENSION_TABLES \
121 EXTENSION_TABLE(00) \
122 EXTENSION_TABLE(01) \
123 EXTENSION_TABLE(18) \
124 EXTENSION_TABLE(71) \
125 EXTENSION_TABLE(72) \
126 EXTENSION_TABLE(73) \
127 EXTENSION_TABLE(ae) \
128 EXTENSION_TABLE(ba) \
131 #define THREE_BYTE_38_EXTENSION_TABLES \
134 using namespace X86Disassembler;
136 /// needsModRMForDecode - Indicates whether a particular instruction requires a
137 /// ModR/M byte for the instruction to be properly decoded. For example, a
138 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
141 /// @param form - The form of the instruction.
142 /// @return - true if the form implies that a ModR/M byte is required, false
144 static bool needsModRMForDecode(uint8_t form) {
145 if (form == X86Local::MRMDestReg ||
146 form == X86Local::MRMDestMem ||
147 form == X86Local::MRMSrcReg ||
148 form == X86Local::MRMSrcMem ||
149 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
150 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
156 /// isRegFormat - Indicates whether a particular form requires the Mod field of
157 /// the ModR/M byte to be 0b11.
159 /// @param form - The form of the instruction.
160 /// @return - true if the form implies that Mod must be 0b11, false
162 static bool isRegFormat(uint8_t form) {
163 if (form == X86Local::MRMDestReg ||
164 form == X86Local::MRMSrcReg ||
165 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
171 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
172 /// Useful for switch statements and the like.
174 /// @param init - A reference to the BitsInit to be decoded.
175 /// @return - The field, with the first bit in the BitsInit as the lowest
177 static uint8_t byteFromBitsInit(BitsInit &init) {
178 int width = init.getNumBits();
180 assert(width <= 8 && "Field is too large for uint8_t!");
187 for (index = 0; index < width; index++) {
188 if (static_cast<BitInit*>(init.getBit(index))->getValue())
197 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
198 /// name of the field.
200 /// @param rec - The record from which to extract the value.
201 /// @param name - The name of the field in the record.
202 /// @return - The field, as translated by byteFromBitsInit().
203 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
204 BitsInit* bits = rec->getValueAsBitsInit(name);
205 return byteFromBitsInit(*bits);
208 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
209 const CodeGenInstruction &insn,
214 Name = Rec->getName();
215 Spec = &tables.specForUID(UID);
217 if (!Rec->isSubClassOf("X86Inst")) {
218 ShouldBeEmitted = false;
222 Prefix = byteFromRec(Rec, "Prefix");
223 Opcode = byteFromRec(Rec, "Opcode");
224 Form = byteFromRec(Rec, "FormBits");
225 SegOvr = byteFromRec(Rec, "SegOvrBits");
227 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
228 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
229 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
230 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
231 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
232 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
233 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
234 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
235 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
236 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
237 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
239 Name = Rec->getName();
240 AsmString = Rec->getValueAsString("AsmString");
242 Operands = &insn.Operands.OperandList;
244 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
245 (Name.find("CRC32") != Name.npos);
246 HasFROperands = hasFROperands();
247 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
249 // Check for 64-bit inst which does not require REX
252 // FIXME: Is there some better way to check for In64BitMode?
253 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
254 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
255 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
259 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
264 // FIXME: These instructions aren't marked as 64-bit in any way
265 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
266 Rec->getName() == "MASKMOVDQU64" ||
267 Rec->getName() == "POPFS64" ||
268 Rec->getName() == "POPGS64" ||
269 Rec->getName() == "PUSHFS64" ||
270 Rec->getName() == "PUSHGS64" ||
271 Rec->getName() == "REX64_PREFIX" ||
272 Rec->getName().find("MOV64") != Name.npos ||
273 Rec->getName().find("PUSH64") != Name.npos ||
274 Rec->getName().find("POP64") != Name.npos;
276 ShouldBeEmitted = true;
279 void RecognizableInstr::processInstr(DisassemblerTables &tables,
280 const CodeGenInstruction &insn,
283 // Ignore "asm parser only" instructions.
284 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
287 RecognizableInstr recogInstr(tables, insn, uid);
289 recogInstr.emitInstructionSpecifier(tables);
291 if (recogInstr.shouldBeEmitted())
292 recogInstr.emitDecodePath(tables);
295 InstructionContext RecognizableInstr::insnContext() const {
296 InstructionContext insnContext;
298 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
299 if (HasVEX_LPrefix && HasVEX_WPrefix) {
301 insnContext = IC_VEX_L_W_OPSIZE;
303 llvm_unreachable("Don't support VEX.L and VEX.W together");
304 } else if (HasOpSizePrefix && HasVEX_LPrefix)
305 insnContext = IC_VEX_L_OPSIZE;
306 else if (HasOpSizePrefix && HasVEX_WPrefix)
307 insnContext = IC_VEX_W_OPSIZE;
308 else if (HasOpSizePrefix)
309 insnContext = IC_VEX_OPSIZE;
310 else if (HasVEX_LPrefix &&
311 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
312 insnContext = IC_VEX_L_XS;
313 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
314 Prefix == X86Local::T8XD ||
315 Prefix == X86Local::TAXD))
316 insnContext = IC_VEX_L_XD;
317 else if (HasVEX_WPrefix &&
318 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
319 insnContext = IC_VEX_W_XS;
320 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
321 Prefix == X86Local::T8XD ||
322 Prefix == X86Local::TAXD))
323 insnContext = IC_VEX_W_XD;
324 else if (HasVEX_WPrefix)
325 insnContext = IC_VEX_W;
326 else if (HasVEX_LPrefix)
327 insnContext = IC_VEX_L;
328 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329 Prefix == X86Local::TAXD)
330 insnContext = IC_VEX_XD;
331 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
332 insnContext = IC_VEX_XS;
334 insnContext = IC_VEX;
335 } else if (Is64Bit || HasREX_WPrefix) {
336 if (HasREX_WPrefix && HasOpSizePrefix)
337 insnContext = IC_64BIT_REXW_OPSIZE;
338 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
339 Prefix == X86Local::T8XD ||
340 Prefix == X86Local::TAXD))
341 insnContext = IC_64BIT_XD_OPSIZE;
342 else if (HasOpSizePrefix &&
343 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
344 insnContext = IC_64BIT_XS_OPSIZE;
345 else if (HasOpSizePrefix)
346 insnContext = IC_64BIT_OPSIZE;
347 else if (HasAdSizePrefix)
348 insnContext = IC_64BIT_ADSIZE;
349 else if (HasREX_WPrefix &&
350 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
351 insnContext = IC_64BIT_REXW_XS;
352 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
353 Prefix == X86Local::T8XD ||
354 Prefix == X86Local::TAXD))
355 insnContext = IC_64BIT_REXW_XD;
356 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357 Prefix == X86Local::TAXD)
358 insnContext = IC_64BIT_XD;
359 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360 insnContext = IC_64BIT_XS;
361 else if (HasREX_WPrefix)
362 insnContext = IC_64BIT_REXW;
364 insnContext = IC_64BIT;
366 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
367 Prefix == X86Local::T8XD ||
368 Prefix == X86Local::TAXD))
369 insnContext = IC_XD_OPSIZE;
370 else if (HasOpSizePrefix &&
371 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
372 insnContext = IC_XS_OPSIZE;
373 else if (HasOpSizePrefix)
374 insnContext = IC_OPSIZE;
375 else if (HasAdSizePrefix)
376 insnContext = IC_ADSIZE;
377 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
378 Prefix == X86Local::TAXD)
380 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
381 Prefix == X86Local::REP)
390 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
395 // Filter out intrinsics
397 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
399 if (Form == X86Local::Pseudo ||
400 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
401 return FILTER_STRONG;
404 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
405 // printed as a separate "instruction".
407 if (Name.find("_Int") != Name.npos ||
408 Name.find("Int_") != Name.npos)
409 return FILTER_STRONG;
411 // Filter out instructions with segment override prefixes.
412 // They're too messy to handle now and we'll special case them if needed.
415 return FILTER_STRONG;
423 // Filter out instructions with a LOCK prefix;
424 // prefer forms that do not have the prefix
428 // Filter out alternate forms of AVX instructions
429 if (Name.find("_alt") != Name.npos ||
430 Name.find("XrYr") != Name.npos ||
431 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
432 Name.find("_64mr") != Name.npos ||
433 Name.find("Xrr") != Name.npos ||
434 Name.find("rr64") != Name.npos)
439 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
441 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
444 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
446 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
448 if (Name.find("Fs") != Name.npos)
450 if (Name == "PUSH64i16" ||
451 Name == "MOVPQI2QImr" ||
452 Name == "VMOVPQI2QImr" ||
453 Name == "MMX_MOVD64rrv164" ||
454 Name == "MOV64ri64i32" ||
455 Name == "VMASKMOVDQU64" ||
456 Name == "VEXTRACTPSrr64" ||
457 Name == "VMOVQd64rr" ||
458 Name == "VMOVQs64rr")
461 if (HasFROperands && Name.find("MOV") != Name.npos &&
462 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
463 (Name.find("to") != Name.npos)))
464 return FILTER_STRONG;
466 return FILTER_NORMAL;
469 bool RecognizableInstr::hasFROperands() const {
470 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
471 unsigned numOperands = OperandList.size();
473 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
474 const std::string &recName = OperandList[operandIndex].Rec->getName();
476 if (recName.find("FR") != recName.npos)
482 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
483 unsigned &physicalOperandIndex,
484 unsigned &numPhysicalOperands,
485 const unsigned *operandMapping,
486 OperandEncoding (*encodingFromString)
488 bool hasOpSizePrefix)) {
490 if (physicalOperandIndex >= numPhysicalOperands)
493 assert(physicalOperandIndex < numPhysicalOperands);
496 while (operandMapping[operandIndex] != operandIndex) {
497 Spec->operands[operandIndex].encoding = ENCODING_DUP;
498 Spec->operands[operandIndex].type =
499 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
503 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
505 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
507 Spec->operands[operandIndex].type = typeFromString(typeName,
513 ++physicalOperandIndex;
516 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
519 if (!ShouldBeEmitted)
524 Spec->filtered = true;
527 ShouldBeEmitted = false;
533 Spec->insnContext = insnContext();
535 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
537 unsigned numOperands = OperandList.size();
538 unsigned numPhysicalOperands = 0;
540 // operandMapping maps from operands in OperandList to their originals.
541 // If operandMapping[i] != i, then the entry is a duplicate.
542 unsigned operandMapping[X86_MAX_OPERANDS];
543 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
545 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
546 if (OperandList[operandIndex].Constraints.size()) {
547 const CGIOperandList::ConstraintInfo &Constraint =
548 OperandList[operandIndex].Constraints[0];
549 if (Constraint.isTied()) {
550 operandMapping[operandIndex] = operandIndex;
551 operandMapping[Constraint.getTiedOperand()] = operandIndex;
553 ++numPhysicalOperands;
554 operandMapping[operandIndex] = operandIndex;
557 ++numPhysicalOperands;
558 operandMapping[operandIndex] = operandIndex;
562 #define HANDLE_OPERAND(class) \
563 handleOperand(false, \
565 physicalOperandIndex, \
566 numPhysicalOperands, \
568 class##EncodingFromString);
570 #define HANDLE_OPTIONAL(class) \
571 handleOperand(true, \
573 physicalOperandIndex, \
574 numPhysicalOperands, \
576 class##EncodingFromString);
578 // operandIndex should always be < numOperands
579 unsigned operandIndex = 0;
580 // physicalOperandIndex should always be < numPhysicalOperands
581 unsigned physicalOperandIndex = 0;
584 case X86Local::RawFrm:
585 // Operand 1 (optional) is an address or immediate.
586 // Operand 2 (optional) is an immediate.
587 assert(numPhysicalOperands <= 2 &&
588 "Unexpected number of operands for RawFrm");
589 HANDLE_OPTIONAL(relocation)
590 HANDLE_OPTIONAL(immediate)
592 case X86Local::AddRegFrm:
593 // Operand 1 is added to the opcode.
594 // Operand 2 (optional) is an address.
595 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
596 "Unexpected number of operands for AddRegFrm");
597 HANDLE_OPERAND(opcodeModifier)
598 HANDLE_OPTIONAL(relocation)
600 case X86Local::MRMDestReg:
601 // Operand 1 is a register operand in the R/M field.
602 // Operand 2 is a register operand in the Reg/Opcode field.
603 // - In AVX, there is a register operand in the VEX.vvvv field here -
604 // Operand 3 (optional) is an immediate.
606 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
607 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
609 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
610 "Unexpected number of operands for MRMDestRegFrm");
612 HANDLE_OPERAND(rmRegister)
615 // FIXME: In AVX, the register below becomes the one encoded
616 // in ModRMVEX and the one above the one in the VEX.VVVV field
617 HANDLE_OPERAND(vvvvRegister)
619 HANDLE_OPERAND(roRegister)
620 HANDLE_OPTIONAL(immediate)
622 case X86Local::MRMDestMem:
623 // Operand 1 is a memory operand (possibly SIB-extended)
624 // Operand 2 is a register operand in the Reg/Opcode field.
625 // - In AVX, there is a register operand in the VEX.vvvv field here -
626 // Operand 3 (optional) is an immediate.
628 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
629 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
631 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
632 "Unexpected number of operands for MRMDestMemFrm");
633 HANDLE_OPERAND(memory)
636 // FIXME: In AVX, the register below becomes the one encoded
637 // in ModRMVEX and the one above the one in the VEX.VVVV field
638 HANDLE_OPERAND(vvvvRegister)
640 HANDLE_OPERAND(roRegister)
641 HANDLE_OPTIONAL(immediate)
643 case X86Local::MRMSrcReg:
644 // Operand 1 is a register operand in the Reg/Opcode field.
645 // Operand 2 is a register operand in the R/M field.
646 // - In AVX, there is a register operand in the VEX.vvvv field here -
647 // Operand 3 (optional) is an immediate.
648 // Operand 4 (optional) is an immediate.
650 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
651 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
652 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
654 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
655 "Unexpected number of operands for MRMSrcRegFrm");
657 HANDLE_OPERAND(roRegister)
660 // FIXME: In AVX, the register below becomes the one encoded
661 // in ModRMVEX and the one above the one in the VEX.VVVV field
662 HANDLE_OPERAND(vvvvRegister)
665 HANDLE_OPERAND(immediate)
667 HANDLE_OPERAND(rmRegister)
669 if (HasVEX_4VOp3Prefix)
670 HANDLE_OPERAND(vvvvRegister)
672 if (!HasMemOp4Prefix)
673 HANDLE_OPTIONAL(immediate)
674 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
675 HANDLE_OPTIONAL(immediate)
677 case X86Local::MRMSrcMem:
678 // Operand 1 is a register operand in the Reg/Opcode field.
679 // Operand 2 is a memory operand (possibly SIB-extended)
680 // - In AVX, there is a register operand in the VEX.vvvv field here -
681 // Operand 3 (optional) is an immediate.
683 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
684 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
685 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
687 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
688 "Unexpected number of operands for MRMSrcMemFrm");
690 HANDLE_OPERAND(roRegister)
693 // FIXME: In AVX, the register below becomes the one encoded
694 // in ModRMVEX and the one above the one in the VEX.VVVV field
695 HANDLE_OPERAND(vvvvRegister)
698 HANDLE_OPERAND(immediate)
700 HANDLE_OPERAND(memory)
702 if (HasVEX_4VOp3Prefix)
703 HANDLE_OPERAND(vvvvRegister)
705 if (!HasMemOp4Prefix)
706 HANDLE_OPTIONAL(immediate)
707 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
709 case X86Local::MRM0r:
710 case X86Local::MRM1r:
711 case X86Local::MRM2r:
712 case X86Local::MRM3r:
713 case X86Local::MRM4r:
714 case X86Local::MRM5r:
715 case X86Local::MRM6r:
716 case X86Local::MRM7r:
717 // Operand 1 is a register operand in the R/M field.
718 // Operand 2 (optional) is an immediate or relocation.
719 // Operand 3 (optional) is an immediate.
721 assert(numPhysicalOperands <= 3 &&
722 "Unexpected number of operands for MRMnRFrm with VEX_4V");
724 assert(numPhysicalOperands <= 3 &&
725 "Unexpected number of operands for MRMnRFrm");
727 HANDLE_OPERAND(vvvvRegister)
728 HANDLE_OPTIONAL(rmRegister)
729 HANDLE_OPTIONAL(relocation)
730 HANDLE_OPTIONAL(immediate)
732 case X86Local::MRM0m:
733 case X86Local::MRM1m:
734 case X86Local::MRM2m:
735 case X86Local::MRM3m:
736 case X86Local::MRM4m:
737 case X86Local::MRM5m:
738 case X86Local::MRM6m:
739 case X86Local::MRM7m:
740 // Operand 1 is a memory operand (possibly SIB-extended)
741 // Operand 2 (optional) is an immediate or relocation.
743 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
744 "Unexpected number of operands for MRMnMFrm");
746 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
747 "Unexpected number of operands for MRMnMFrm");
749 HANDLE_OPERAND(vvvvRegister)
750 HANDLE_OPERAND(memory)
751 HANDLE_OPTIONAL(relocation)
753 case X86Local::RawFrmImm8:
754 // operand 1 is a 16-bit immediate
755 // operand 2 is an 8-bit immediate
756 assert(numPhysicalOperands == 2 &&
757 "Unexpected number of operands for X86Local::RawFrmImm8");
758 HANDLE_OPERAND(immediate)
759 HANDLE_OPERAND(immediate)
761 case X86Local::RawFrmImm16:
762 // operand 1 is a 16-bit immediate
763 // operand 2 is a 16-bit immediate
764 HANDLE_OPERAND(immediate)
765 HANDLE_OPERAND(immediate)
767 case X86Local::MRMInitReg:
772 #undef HANDLE_OPERAND
773 #undef HANDLE_OPTIONAL
776 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
777 // Special cases where the LLVM tables are not complete
779 #define MAP(from, to) \
780 case X86Local::MRM_##from: \
781 filter = new ExactFilter(0x##from); \
784 OpcodeType opcodeType = (OpcodeType)-1;
786 ModRMFilter* filter = NULL;
787 uint8_t opcodeToSet = 0;
790 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
794 opcodeType = TWOBYTE;
798 if (needsModRMForDecode(Form))
799 filter = new ModFilter(isRegFormat(Form));
801 filter = new DumbFilter();
803 #define EXTENSION_TABLE(n) case 0x##n:
804 TWO_BYTE_EXTENSION_TABLES
805 #undef EXTENSION_TABLE
808 llvm_unreachable("Unhandled two-byte extended opcode");
809 case X86Local::MRM0r:
810 case X86Local::MRM1r:
811 case X86Local::MRM2r:
812 case X86Local::MRM3r:
813 case X86Local::MRM4r:
814 case X86Local::MRM5r:
815 case X86Local::MRM6r:
816 case X86Local::MRM7r:
817 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
819 case X86Local::MRM0m:
820 case X86Local::MRM1m:
821 case X86Local::MRM2m:
822 case X86Local::MRM3m:
823 case X86Local::MRM4m:
824 case X86Local::MRM5m:
825 case X86Local::MRM6m:
826 case X86Local::MRM7m:
827 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
833 opcodeToSet = Opcode;
838 opcodeType = THREEBYTE_38;
841 if (needsModRMForDecode(Form))
842 filter = new ModFilter(isRegFormat(Form));
844 filter = new DumbFilter();
846 #define EXTENSION_TABLE(n) case 0x##n:
847 THREE_BYTE_38_EXTENSION_TABLES
848 #undef EXTENSION_TABLE
851 llvm_unreachable("Unhandled two-byte extended opcode");
852 case X86Local::MRM0r:
853 case X86Local::MRM1r:
854 case X86Local::MRM2r:
855 case X86Local::MRM3r:
856 case X86Local::MRM4r:
857 case X86Local::MRM5r:
858 case X86Local::MRM6r:
859 case X86Local::MRM7r:
860 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
862 case X86Local::MRM0m:
863 case X86Local::MRM1m:
864 case X86Local::MRM2m:
865 case X86Local::MRM3m:
866 case X86Local::MRM4m:
867 case X86Local::MRM5m:
868 case X86Local::MRM6m:
869 case X86Local::MRM7m:
870 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
876 opcodeToSet = Opcode;
880 opcodeType = THREEBYTE_3A;
881 if (needsModRMForDecode(Form))
882 filter = new ModFilter(isRegFormat(Form));
884 filter = new DumbFilter();
885 opcodeToSet = Opcode;
888 opcodeType = THREEBYTE_A6;
889 if (needsModRMForDecode(Form))
890 filter = new ModFilter(isRegFormat(Form));
892 filter = new DumbFilter();
893 opcodeToSet = Opcode;
896 opcodeType = THREEBYTE_A7;
897 if (needsModRMForDecode(Form))
898 filter = new ModFilter(isRegFormat(Form));
900 filter = new DumbFilter();
901 opcodeToSet = Opcode;
911 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
912 opcodeType = ONEBYTE;
913 if (Form == X86Local::AddRegFrm) {
914 Spec->modifierType = MODIFIER_MODRM;
915 Spec->modifierBase = Opcode;
916 filter = new AddRegEscapeFilter(Opcode);
918 filter = new EscapeFilter(true, Opcode);
920 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
924 opcodeType = ONEBYTE;
926 #define EXTENSION_TABLE(n) case 0x##n:
927 ONE_BYTE_EXTENSION_TABLES
928 #undef EXTENSION_TABLE
931 llvm_unreachable("Fell through the cracks of a single-byte "
933 case X86Local::MRM0r:
934 case X86Local::MRM1r:
935 case X86Local::MRM2r:
936 case X86Local::MRM3r:
937 case X86Local::MRM4r:
938 case X86Local::MRM5r:
939 case X86Local::MRM6r:
940 case X86Local::MRM7r:
941 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
943 case X86Local::MRM0m:
944 case X86Local::MRM1m:
945 case X86Local::MRM2m:
946 case X86Local::MRM3m:
947 case X86Local::MRM4m:
948 case X86Local::MRM5m:
949 case X86Local::MRM6m:
950 case X86Local::MRM7m:
951 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
964 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
967 if (needsModRMForDecode(Form))
968 filter = new ModFilter(isRegFormat(Form));
970 filter = new DumbFilter();
973 opcodeToSet = Opcode;
976 assert(opcodeType != (OpcodeType)-1 &&
977 "Opcode type not set");
978 assert(filter && "Filter not set");
980 if (Form == X86Local::AddRegFrm) {
981 if(Spec->modifierType != MODIFIER_MODRM) {
982 assert(opcodeToSet < 0xf9 &&
983 "Not enough room for all ADDREG_FRM operands");
985 uint8_t currentOpcode;
987 for (currentOpcode = opcodeToSet;
988 currentOpcode < opcodeToSet + 8;
990 tables.setTableFields(opcodeType,
994 UID, Is32Bit, IgnoresVEX_L);
996 Spec->modifierType = MODIFIER_OPCODE;
997 Spec->modifierBase = opcodeToSet;
999 // modifierBase was set where MODIFIER_MODRM was set
1000 tables.setTableFields(opcodeType,
1004 UID, Is32Bit, IgnoresVEX_L);
1007 tables.setTableFields(opcodeType,
1011 UID, Is32Bit, IgnoresVEX_L);
1013 Spec->modifierType = MODIFIER_NONE;
1014 Spec->modifierBase = opcodeToSet;
1022 #define TYPE(str, type) if (s == str) return type;
1023 OperandType RecognizableInstr::typeFromString(const std::string &s,
1025 bool hasREX_WPrefix,
1026 bool hasOpSizePrefix) {
1028 // For SSE instructions, we ignore the OpSize prefix and force operand
1030 TYPE("GR16", TYPE_R16)
1031 TYPE("GR32", TYPE_R32)
1032 TYPE("GR64", TYPE_R64)
1034 if(hasREX_WPrefix) {
1035 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1037 TYPE("GR32", TYPE_R32)
1039 if(!hasOpSizePrefix) {
1040 // For instructions without an OpSize prefix, a declared 16-bit register or
1041 // immediate encoding is special.
1042 TYPE("GR16", TYPE_R16)
1043 TYPE("i16imm", TYPE_IMM16)
1045 TYPE("i16mem", TYPE_Mv)
1046 TYPE("i16imm", TYPE_IMMv)
1047 TYPE("i16i8imm", TYPE_IMMv)
1048 TYPE("GR16", TYPE_Rv)
1049 TYPE("i32mem", TYPE_Mv)
1050 TYPE("i32imm", TYPE_IMMv)
1051 TYPE("i32i8imm", TYPE_IMM32)
1052 TYPE("u32u8imm", TYPE_IMM32)
1053 TYPE("GR32", TYPE_Rv)
1054 TYPE("i64mem", TYPE_Mv)
1055 TYPE("i64i32imm", TYPE_IMM64)
1056 TYPE("i64i8imm", TYPE_IMM64)
1057 TYPE("GR64", TYPE_R64)
1058 TYPE("i8mem", TYPE_M8)
1059 TYPE("i8imm", TYPE_IMM8)
1060 TYPE("GR8", TYPE_R8)
1061 TYPE("VR128", TYPE_XMM128)
1062 TYPE("f128mem", TYPE_M128)
1063 TYPE("f256mem", TYPE_M256)
1064 TYPE("FR64", TYPE_XMM64)
1065 TYPE("f64mem", TYPE_M64FP)
1066 TYPE("sdmem", TYPE_M64FP)
1067 TYPE("FR32", TYPE_XMM32)
1068 TYPE("f32mem", TYPE_M32FP)
1069 TYPE("ssmem", TYPE_M32FP)
1070 TYPE("RST", TYPE_ST)
1071 TYPE("i128mem", TYPE_M128)
1072 TYPE("i256mem", TYPE_M256)
1073 TYPE("i64i32imm_pcrel", TYPE_REL64)
1074 TYPE("i16imm_pcrel", TYPE_REL16)
1075 TYPE("i32imm_pcrel", TYPE_REL32)
1076 TYPE("SSECC", TYPE_IMM3)
1077 TYPE("AVXCC", TYPE_IMM5)
1078 TYPE("brtarget", TYPE_RELv)
1079 TYPE("uncondbrtarget", TYPE_RELv)
1080 TYPE("brtarget8", TYPE_REL8)
1081 TYPE("f80mem", TYPE_M80FP)
1082 TYPE("lea32mem", TYPE_LEA)
1083 TYPE("lea64_32mem", TYPE_LEA)
1084 TYPE("lea64mem", TYPE_LEA)
1085 TYPE("VR64", TYPE_MM64)
1086 TYPE("i64imm", TYPE_IMMv)
1087 TYPE("opaque32mem", TYPE_M1616)
1088 TYPE("opaque48mem", TYPE_M1632)
1089 TYPE("opaque80mem", TYPE_M1664)
1090 TYPE("opaque512mem", TYPE_M512)
1091 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1092 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1093 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1094 TYPE("offset8", TYPE_MOFFS8)
1095 TYPE("offset16", TYPE_MOFFS16)
1096 TYPE("offset32", TYPE_MOFFS32)
1097 TYPE("offset64", TYPE_MOFFS64)
1098 TYPE("VR256", TYPE_XMM256)
1099 TYPE("GR16_NOAX", TYPE_Rv)
1100 TYPE("GR32_NOAX", TYPE_Rv)
1101 TYPE("GR64_NOAX", TYPE_R64)
1102 TYPE("vx32mem", TYPE_M32)
1103 TYPE("vy32mem", TYPE_M32)
1104 TYPE("vx64mem", TYPE_M64)
1105 TYPE("vy64mem", TYPE_M64)
1106 errs() << "Unhandled type string " << s << "\n";
1107 llvm_unreachable("Unhandled type string");
1111 #define ENCODING(str, encoding) if (s == str) return encoding;
1112 OperandEncoding RecognizableInstr::immediateEncodingFromString
1113 (const std::string &s,
1114 bool hasOpSizePrefix) {
1115 if(!hasOpSizePrefix) {
1116 // For instructions without an OpSize prefix, a declared 16-bit register or
1117 // immediate encoding is special.
1118 ENCODING("i16imm", ENCODING_IW)
1120 ENCODING("i32i8imm", ENCODING_IB)
1121 ENCODING("u32u8imm", ENCODING_IB)
1122 ENCODING("SSECC", ENCODING_IB)
1123 ENCODING("AVXCC", ENCODING_IB)
1124 ENCODING("i16imm", ENCODING_Iv)
1125 ENCODING("i16i8imm", ENCODING_IB)
1126 ENCODING("i32imm", ENCODING_Iv)
1127 ENCODING("i64i32imm", ENCODING_ID)
1128 ENCODING("i64i8imm", ENCODING_IB)
1129 ENCODING("i8imm", ENCODING_IB)
1130 // This is not a typo. Instructions like BLENDVPD put
1131 // register IDs in 8-bit immediates nowadays.
1132 ENCODING("VR256", ENCODING_IB)
1133 ENCODING("VR128", ENCODING_IB)
1134 ENCODING("FR32", ENCODING_IB)
1135 ENCODING("FR64", ENCODING_IB)
1136 errs() << "Unhandled immediate encoding " << s << "\n";
1137 llvm_unreachable("Unhandled immediate encoding");
1140 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1141 (const std::string &s,
1142 bool hasOpSizePrefix) {
1143 ENCODING("GR16", ENCODING_RM)
1144 ENCODING("GR32", ENCODING_RM)
1145 ENCODING("GR64", ENCODING_RM)
1146 ENCODING("GR8", ENCODING_RM)
1147 ENCODING("VR128", ENCODING_RM)
1148 ENCODING("FR64", ENCODING_RM)
1149 ENCODING("FR32", ENCODING_RM)
1150 ENCODING("VR64", ENCODING_RM)
1151 ENCODING("VR256", ENCODING_RM)
1152 errs() << "Unhandled R/M register encoding " << s << "\n";
1153 llvm_unreachable("Unhandled R/M register encoding");
1156 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1157 (const std::string &s,
1158 bool hasOpSizePrefix) {
1159 ENCODING("GR16", ENCODING_REG)
1160 ENCODING("GR32", ENCODING_REG)
1161 ENCODING("GR64", ENCODING_REG)
1162 ENCODING("GR8", ENCODING_REG)
1163 ENCODING("VR128", ENCODING_REG)
1164 ENCODING("FR64", ENCODING_REG)
1165 ENCODING("FR32", ENCODING_REG)
1166 ENCODING("VR64", ENCODING_REG)
1167 ENCODING("SEGMENT_REG", ENCODING_REG)
1168 ENCODING("DEBUG_REG", ENCODING_REG)
1169 ENCODING("CONTROL_REG", ENCODING_REG)
1170 ENCODING("VR256", ENCODING_REG)
1171 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1172 llvm_unreachable("Unhandled reg/opcode register encoding");
1175 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1176 (const std::string &s,
1177 bool hasOpSizePrefix) {
1178 ENCODING("GR32", ENCODING_VVVV)
1179 ENCODING("GR64", ENCODING_VVVV)
1180 ENCODING("FR32", ENCODING_VVVV)
1181 ENCODING("FR64", ENCODING_VVVV)
1182 ENCODING("VR128", ENCODING_VVVV)
1183 ENCODING("VR256", ENCODING_VVVV)
1184 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1185 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1188 OperandEncoding RecognizableInstr::memoryEncodingFromString
1189 (const std::string &s,
1190 bool hasOpSizePrefix) {
1191 ENCODING("i16mem", ENCODING_RM)
1192 ENCODING("i32mem", ENCODING_RM)
1193 ENCODING("i64mem", ENCODING_RM)
1194 ENCODING("i8mem", ENCODING_RM)
1195 ENCODING("ssmem", ENCODING_RM)
1196 ENCODING("sdmem", ENCODING_RM)
1197 ENCODING("f128mem", ENCODING_RM)
1198 ENCODING("f256mem", ENCODING_RM)
1199 ENCODING("f64mem", ENCODING_RM)
1200 ENCODING("f32mem", ENCODING_RM)
1201 ENCODING("i128mem", ENCODING_RM)
1202 ENCODING("i256mem", ENCODING_RM)
1203 ENCODING("f80mem", ENCODING_RM)
1204 ENCODING("lea32mem", ENCODING_RM)
1205 ENCODING("lea64_32mem", ENCODING_RM)
1206 ENCODING("lea64mem", ENCODING_RM)
1207 ENCODING("opaque32mem", ENCODING_RM)
1208 ENCODING("opaque48mem", ENCODING_RM)
1209 ENCODING("opaque80mem", ENCODING_RM)
1210 ENCODING("opaque512mem", ENCODING_RM)
1211 ENCODING("vx32mem", ENCODING_RM)
1212 ENCODING("vy32mem", ENCODING_RM)
1213 ENCODING("vx64mem", ENCODING_RM)
1214 ENCODING("vy64mem", ENCODING_RM)
1215 errs() << "Unhandled memory encoding " << s << "\n";
1216 llvm_unreachable("Unhandled memory encoding");
1219 OperandEncoding RecognizableInstr::relocationEncodingFromString
1220 (const std::string &s,
1221 bool hasOpSizePrefix) {
1222 if(!hasOpSizePrefix) {
1223 // For instructions without an OpSize prefix, a declared 16-bit register or
1224 // immediate encoding is special.
1225 ENCODING("i16imm", ENCODING_IW)
1227 ENCODING("i16imm", ENCODING_Iv)
1228 ENCODING("i16i8imm", ENCODING_IB)
1229 ENCODING("i32imm", ENCODING_Iv)
1230 ENCODING("i32i8imm", ENCODING_IB)
1231 ENCODING("i64i32imm", ENCODING_ID)
1232 ENCODING("i64i8imm", ENCODING_IB)
1233 ENCODING("i8imm", ENCODING_IB)
1234 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1235 ENCODING("i16imm_pcrel", ENCODING_IW)
1236 ENCODING("i32imm_pcrel", ENCODING_ID)
1237 ENCODING("brtarget", ENCODING_Iv)
1238 ENCODING("brtarget8", ENCODING_IB)
1239 ENCODING("i64imm", ENCODING_IO)
1240 ENCODING("offset8", ENCODING_Ia)
1241 ENCODING("offset16", ENCODING_Ia)
1242 ENCODING("offset32", ENCODING_Ia)
1243 ENCODING("offset64", ENCODING_Ia)
1244 errs() << "Unhandled relocation encoding " << s << "\n";
1245 llvm_unreachable("Unhandled relocation encoding");
1248 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1249 (const std::string &s,
1250 bool hasOpSizePrefix) {
1251 ENCODING("RST", ENCODING_I)
1252 ENCODING("GR32", ENCODING_Rv)
1253 ENCODING("GR64", ENCODING_RO)
1254 ENCODING("GR16", ENCODING_Rv)
1255 ENCODING("GR8", ENCODING_RB)
1256 ENCODING("GR16_NOAX", ENCODING_Rv)
1257 ENCODING("GR32_NOAX", ENCODING_Rv)
1258 ENCODING("GR64_NOAX", ENCODING_RO)
1259 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1260 llvm_unreachable("Unhandled opcode modifier encoding");