1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
49 // A clone of X86 since we can't depend on something that is generated.
59 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
60 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
61 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
62 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
64 #define MAP(from, to) MRM_##from = to,
75 D8 = 3, D9 = 4, DA = 5, DB = 6,
76 DC = 7, DD = 8, DE = 9, DF = 10,
79 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
83 // If rows are added to the opcode extension tables, then corresponding entries
84 // must be added here.
86 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
87 // that byte to ONE_BYTE_EXTENSION_TABLES.
89 // If the row corresponds to two bytes where the first is 0f, add an entry for
90 // the second byte to TWO_BYTE_EXTENSION_TABLES.
92 // If the row corresponds to some other set of bytes, you will need to modify
93 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
94 // to the X86 TD files, except in two cases: if the first two bytes of such a
95 // new combination are 0f 38 or 0f 3a, you just have to add maps called
96 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
97 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
98 // in RecognizableInstr::emitDecodePath().
100 #define ONE_BYTE_EXTENSION_TABLES \
101 EXTENSION_TABLE(80) \
102 EXTENSION_TABLE(81) \
103 EXTENSION_TABLE(82) \
104 EXTENSION_TABLE(83) \
105 EXTENSION_TABLE(8f) \
106 EXTENSION_TABLE(c0) \
107 EXTENSION_TABLE(c1) \
108 EXTENSION_TABLE(c6) \
109 EXTENSION_TABLE(c7) \
110 EXTENSION_TABLE(d0) \
111 EXTENSION_TABLE(d1) \
112 EXTENSION_TABLE(d2) \
113 EXTENSION_TABLE(d3) \
114 EXTENSION_TABLE(f6) \
115 EXTENSION_TABLE(f7) \
116 EXTENSION_TABLE(fe) \
119 #define TWO_BYTE_EXTENSION_TABLES \
120 EXTENSION_TABLE(00) \
121 EXTENSION_TABLE(01) \
122 EXTENSION_TABLE(18) \
123 EXTENSION_TABLE(71) \
124 EXTENSION_TABLE(72) \
125 EXTENSION_TABLE(73) \
126 EXTENSION_TABLE(ae) \
127 EXTENSION_TABLE(ba) \
130 #define THREE_BYTE_38_EXTENSION_TABLES \
133 using namespace X86Disassembler;
135 /// needsModRMForDecode - Indicates whether a particular instruction requires a
136 /// ModR/M byte for the instruction to be properly decoded. For example, a
137 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
140 /// @param form - The form of the instruction.
141 /// @return - true if the form implies that a ModR/M byte is required, false
143 static bool needsModRMForDecode(uint8_t form) {
144 if (form == X86Local::MRMDestReg ||
145 form == X86Local::MRMDestMem ||
146 form == X86Local::MRMSrcReg ||
147 form == X86Local::MRMSrcMem ||
148 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
149 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
155 /// isRegFormat - Indicates whether a particular form requires the Mod field of
156 /// the ModR/M byte to be 0b11.
158 /// @param form - The form of the instruction.
159 /// @return - true if the form implies that Mod must be 0b11, false
161 static bool isRegFormat(uint8_t form) {
162 if (form == X86Local::MRMDestReg ||
163 form == X86Local::MRMSrcReg ||
164 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
170 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
171 /// Useful for switch statements and the like.
173 /// @param init - A reference to the BitsInit to be decoded.
174 /// @return - The field, with the first bit in the BitsInit as the lowest
176 static uint8_t byteFromBitsInit(BitsInit &init) {
177 int width = init.getNumBits();
179 assert(width <= 8 && "Field is too large for uint8_t!");
186 for (index = 0; index < width; index++) {
187 if (static_cast<BitInit*>(init.getBit(index))->getValue())
196 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
197 /// name of the field.
199 /// @param rec - The record from which to extract the value.
200 /// @param name - The name of the field in the record.
201 /// @return - The field, as translated by byteFromBitsInit().
202 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
203 BitsInit* bits = rec->getValueAsBitsInit(name);
204 return byteFromBitsInit(*bits);
207 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
208 const CodeGenInstruction &insn,
213 Name = Rec->getName();
214 Spec = &tables.specForUID(UID);
216 if (!Rec->isSubClassOf("X86Inst")) {
217 ShouldBeEmitted = false;
221 Prefix = byteFromRec(Rec, "Prefix");
222 Opcode = byteFromRec(Rec, "Opcode");
223 Form = byteFromRec(Rec, "FormBits");
224 SegOvr = byteFromRec(Rec, "SegOvrBits");
226 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
227 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
228 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
229 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
230 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
231 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
232 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
233 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
234 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
235 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
237 Name = Rec->getName();
238 AsmString = Rec->getValueAsString("AsmString");
240 Operands = &insn.Operands.OperandList;
242 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
243 (Name.find("CRC32") != Name.npos);
244 HasFROperands = hasFROperands();
245 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
247 // Check for 64-bit inst which does not require REX
250 // FIXME: Is there some better way to check for In64BitMode?
251 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
252 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
253 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
257 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
262 // FIXME: These instructions aren't marked as 64-bit in any way
263 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
264 Rec->getName() == "MASKMOVDQU64" ||
265 Rec->getName() == "POPFS64" ||
266 Rec->getName() == "POPGS64" ||
267 Rec->getName() == "PUSHFS64" ||
268 Rec->getName() == "PUSHGS64" ||
269 Rec->getName() == "REX64_PREFIX" ||
270 Rec->getName().find("MOV64") != Name.npos ||
271 Rec->getName().find("PUSH64") != Name.npos ||
272 Rec->getName().find("POP64") != Name.npos;
274 ShouldBeEmitted = true;
277 void RecognizableInstr::processInstr(DisassemblerTables &tables,
278 const CodeGenInstruction &insn,
281 // Ignore "asm parser only" instructions.
282 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
285 RecognizableInstr recogInstr(tables, insn, uid);
287 recogInstr.emitInstructionSpecifier(tables);
289 if (recogInstr.shouldBeEmitted())
290 recogInstr.emitDecodePath(tables);
293 InstructionContext RecognizableInstr::insnContext() const {
294 InstructionContext insnContext;
296 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
297 if (HasVEX_LPrefix && HasVEX_WPrefix) {
299 insnContext = IC_VEX_L_W_OPSIZE;
301 llvm_unreachable("Don't support VEX.L and VEX.W together");
302 } else if (HasOpSizePrefix && HasVEX_LPrefix)
303 insnContext = IC_VEX_L_OPSIZE;
304 else if (HasOpSizePrefix && HasVEX_WPrefix)
305 insnContext = IC_VEX_W_OPSIZE;
306 else if (HasOpSizePrefix)
307 insnContext = IC_VEX_OPSIZE;
308 else if (HasVEX_LPrefix &&
309 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
310 insnContext = IC_VEX_L_XS;
311 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
312 Prefix == X86Local::T8XD ||
313 Prefix == X86Local::TAXD))
314 insnContext = IC_VEX_L_XD;
315 else if (HasVEX_WPrefix &&
316 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
317 insnContext = IC_VEX_W_XS;
318 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
319 Prefix == X86Local::T8XD ||
320 Prefix == X86Local::TAXD))
321 insnContext = IC_VEX_W_XD;
322 else if (HasVEX_WPrefix)
323 insnContext = IC_VEX_W;
324 else if (HasVEX_LPrefix)
325 insnContext = IC_VEX_L;
326 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
327 Prefix == X86Local::TAXD)
328 insnContext = IC_VEX_XD;
329 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
330 insnContext = IC_VEX_XS;
332 insnContext = IC_VEX;
333 } else if (Is64Bit || HasREX_WPrefix) {
334 if (HasREX_WPrefix && HasOpSizePrefix)
335 insnContext = IC_64BIT_REXW_OPSIZE;
336 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
337 Prefix == X86Local::T8XD ||
338 Prefix == X86Local::TAXD))
339 insnContext = IC_64BIT_XD_OPSIZE;
340 else if (HasOpSizePrefix &&
341 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
342 insnContext = IC_64BIT_XS_OPSIZE;
343 else if (HasOpSizePrefix)
344 insnContext = IC_64BIT_OPSIZE;
345 else if (HasREX_WPrefix &&
346 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
347 insnContext = IC_64BIT_REXW_XS;
348 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
349 Prefix == X86Local::T8XD ||
350 Prefix == X86Local::TAXD))
351 insnContext = IC_64BIT_REXW_XD;
352 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
353 Prefix == X86Local::TAXD)
354 insnContext = IC_64BIT_XD;
355 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
356 insnContext = IC_64BIT_XS;
357 else if (HasREX_WPrefix)
358 insnContext = IC_64BIT_REXW;
360 insnContext = IC_64BIT;
362 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
363 Prefix == X86Local::T8XD ||
364 Prefix == X86Local::TAXD))
365 insnContext = IC_XD_OPSIZE;
366 else if (HasOpSizePrefix &&
367 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
368 insnContext = IC_XS_OPSIZE;
369 else if (HasOpSizePrefix)
370 insnContext = IC_OPSIZE;
371 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
372 Prefix == X86Local::TAXD)
374 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
375 Prefix == X86Local::REP)
384 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
389 // Filter out intrinsics
391 if (!Rec->isSubClassOf("X86Inst"))
392 return FILTER_STRONG;
394 if (Form == X86Local::Pseudo ||
395 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
396 return FILTER_STRONG;
398 if (Form == X86Local::MRMInitReg)
399 return FILTER_STRONG;
402 // Filter out artificial instructions
404 if (Name.find("_Int") != Name.npos ||
405 Name.find("Int_") != Name.npos ||
406 Name.find("_NOREX") != Name.npos ||
407 Name.find("2SDL") != Name.npos ||
408 Name == "LOCK_PREFIX")
409 return FILTER_STRONG;
411 // Filter out instructions with segment override prefixes.
412 // They're too messy to handle now and we'll special case them if needed.
415 return FILTER_STRONG;
417 // Filter out instructions that can't be printed.
419 if (AsmString.size() == 0)
420 return FILTER_STRONG;
422 // Filter out instructions with subreg operands.
424 if (AsmString.find("subreg") != AsmString.npos)
425 return FILTER_STRONG;
432 // Filter out instructions with a LOCK prefix;
433 // prefer forms that do not have the prefix
437 // Filter out alternate forms of AVX instructions
438 if (Name.find("_alt") != Name.npos ||
439 Name.find("XrYr") != Name.npos ||
440 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
441 Name.find("_64mr") != Name.npos ||
442 Name.find("Xrr") != Name.npos ||
443 Name.find("rr64") != Name.npos)
448 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
450 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
453 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
455 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
457 if (Name.find("Fs") != Name.npos)
459 if (Name == "PUSH64i16" ||
460 Name == "MOVPQI2QImr" ||
461 Name == "VMOVPQI2QImr" ||
462 Name == "MMX_MOVD64rrv164" ||
463 Name == "MOV64ri64i32" ||
464 Name == "VMASKMOVDQU64" ||
465 Name == "VEXTRACTPSrr64" ||
466 Name == "VMOVQd64rr" ||
467 Name == "VMOVQs64rr")
470 if (HasFROperands && Name.find("MOV") != Name.npos &&
471 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
472 (Name.find("to") != Name.npos)))
475 return FILTER_NORMAL;
478 bool RecognizableInstr::hasFROperands() const {
479 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
480 unsigned numOperands = OperandList.size();
482 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
483 const std::string &recName = OperandList[operandIndex].Rec->getName();
485 if (recName.find("FR") != recName.npos)
491 bool RecognizableInstr::has256BitOperands() const {
492 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
493 unsigned numOperands = OperandList.size();
495 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
496 const std::string &recName = OperandList[operandIndex].Rec->getName();
498 if (!recName.compare("VR256") || !recName.compare("f256mem")) {
505 void RecognizableInstr::handleOperand(
507 unsigned &operandIndex,
508 unsigned &physicalOperandIndex,
509 unsigned &numPhysicalOperands,
510 unsigned *operandMapping,
511 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
513 if (physicalOperandIndex >= numPhysicalOperands)
516 assert(physicalOperandIndex < numPhysicalOperands);
519 while (operandMapping[operandIndex] != operandIndex) {
520 Spec->operands[operandIndex].encoding = ENCODING_DUP;
521 Spec->operands[operandIndex].type =
522 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
526 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
528 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
530 Spec->operands[operandIndex].type = typeFromString(typeName,
536 ++physicalOperandIndex;
539 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
542 if (!Rec->isSubClassOf("X86Inst"))
547 Spec->filtered = true;
550 ShouldBeEmitted = false;
556 Spec->insnContext = insnContext();
558 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
560 unsigned operandIndex;
561 unsigned numOperands = OperandList.size();
562 unsigned numPhysicalOperands = 0;
564 // operandMapping maps from operands in OperandList to their originals.
565 // If operandMapping[i] != i, then the entry is a duplicate.
566 unsigned operandMapping[X86_MAX_OPERANDS];
568 bool hasFROperands = false;
570 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
572 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
573 if (OperandList[operandIndex].Constraints.size()) {
574 const CGIOperandList::ConstraintInfo &Constraint =
575 OperandList[operandIndex].Constraints[0];
576 if (Constraint.isTied()) {
577 operandMapping[operandIndex] = Constraint.getTiedOperand();
579 ++numPhysicalOperands;
580 operandMapping[operandIndex] = operandIndex;
583 ++numPhysicalOperands;
584 operandMapping[operandIndex] = operandIndex;
587 const std::string &recName = OperandList[operandIndex].Rec->getName();
589 if (recName.find("FR") != recName.npos)
590 hasFROperands = true;
593 if (hasFROperands && Name.find("MOV") != Name.npos &&
594 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
595 (Name.find("to") != Name.npos)))
596 ShouldBeEmitted = false;
598 if (!ShouldBeEmitted)
601 #define HANDLE_OPERAND(class) \
602 handleOperand(false, \
604 physicalOperandIndex, \
605 numPhysicalOperands, \
607 class##EncodingFromString);
609 #define HANDLE_OPTIONAL(class) \
610 handleOperand(true, \
612 physicalOperandIndex, \
613 numPhysicalOperands, \
615 class##EncodingFromString);
617 // operandIndex should always be < numOperands
619 // physicalOperandIndex should always be < numPhysicalOperands
620 unsigned physicalOperandIndex = 0;
623 case X86Local::RawFrm:
624 // Operand 1 (optional) is an address or immediate.
625 // Operand 2 (optional) is an immediate.
626 assert(numPhysicalOperands <= 2 &&
627 "Unexpected number of operands for RawFrm");
628 HANDLE_OPTIONAL(relocation)
629 HANDLE_OPTIONAL(immediate)
631 case X86Local::AddRegFrm:
632 // Operand 1 is added to the opcode.
633 // Operand 2 (optional) is an address.
634 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
635 "Unexpected number of operands for AddRegFrm");
636 HANDLE_OPERAND(opcodeModifier)
637 HANDLE_OPTIONAL(relocation)
639 case X86Local::MRMDestReg:
640 // Operand 1 is a register operand in the R/M field.
641 // Operand 2 is a register operand in the Reg/Opcode field.
642 // - In AVX, there is a register operand in the VEX.vvvv field here -
643 // Operand 3 (optional) is an immediate.
645 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
646 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
648 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
649 "Unexpected number of operands for MRMDestRegFrm");
651 HANDLE_OPERAND(rmRegister)
654 // FIXME: In AVX, the register below becomes the one encoded
655 // in ModRMVEX and the one above the one in the VEX.VVVV field
656 HANDLE_OPERAND(vvvvRegister)
658 HANDLE_OPERAND(roRegister)
659 HANDLE_OPTIONAL(immediate)
661 case X86Local::MRMDestMem:
662 // Operand 1 is a memory operand (possibly SIB-extended)
663 // Operand 2 is a register operand in the Reg/Opcode field.
664 // - In AVX, there is a register operand in the VEX.vvvv field here -
665 // Operand 3 (optional) is an immediate.
667 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
668 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
670 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
671 "Unexpected number of operands for MRMDestMemFrm");
672 HANDLE_OPERAND(memory)
675 // FIXME: In AVX, the register below becomes the one encoded
676 // in ModRMVEX and the one above the one in the VEX.VVVV field
677 HANDLE_OPERAND(vvvvRegister)
679 HANDLE_OPERAND(roRegister)
680 HANDLE_OPTIONAL(immediate)
682 case X86Local::MRMSrcReg:
683 // Operand 1 is a register operand in the Reg/Opcode field.
684 // Operand 2 is a register operand in the R/M field.
685 // - In AVX, there is a register operand in the VEX.vvvv field here -
686 // Operand 3 (optional) is an immediate.
688 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
689 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
690 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
692 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
693 "Unexpected number of operands for MRMSrcRegFrm");
695 HANDLE_OPERAND(roRegister)
698 // FIXME: In AVX, the register below becomes the one encoded
699 // in ModRMVEX and the one above the one in the VEX.VVVV field
700 HANDLE_OPERAND(vvvvRegister)
703 HANDLE_OPERAND(immediate)
705 HANDLE_OPERAND(rmRegister)
707 if (HasVEX_4VOp3Prefix)
708 HANDLE_OPERAND(vvvvRegister)
710 if (!HasMemOp4Prefix)
711 HANDLE_OPTIONAL(immediate)
712 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
714 case X86Local::MRMSrcMem:
715 // Operand 1 is a register operand in the Reg/Opcode field.
716 // Operand 2 is a memory operand (possibly SIB-extended)
717 // - In AVX, there is a register operand in the VEX.vvvv field here -
718 // Operand 3 (optional) is an immediate.
720 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
721 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
722 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
724 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
725 "Unexpected number of operands for MRMSrcMemFrm");
727 HANDLE_OPERAND(roRegister)
730 // FIXME: In AVX, the register below becomes the one encoded
731 // in ModRMVEX and the one above the one in the VEX.VVVV field
732 HANDLE_OPERAND(vvvvRegister)
735 HANDLE_OPERAND(immediate)
737 HANDLE_OPERAND(memory)
739 if (HasVEX_4VOp3Prefix)
740 HANDLE_OPERAND(vvvvRegister)
742 if (!HasMemOp4Prefix)
743 HANDLE_OPTIONAL(immediate)
744 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
746 case X86Local::MRM0r:
747 case X86Local::MRM1r:
748 case X86Local::MRM2r:
749 case X86Local::MRM3r:
750 case X86Local::MRM4r:
751 case X86Local::MRM5r:
752 case X86Local::MRM6r:
753 case X86Local::MRM7r:
754 // Operand 1 is a register operand in the R/M field.
755 // Operand 2 (optional) is an immediate or relocation.
757 assert(numPhysicalOperands <= 3 &&
758 "Unexpected number of operands for MRMnRFrm with VEX_4V");
760 assert(numPhysicalOperands <= 2 &&
761 "Unexpected number of operands for MRMnRFrm");
763 HANDLE_OPERAND(vvvvRegister)
764 HANDLE_OPTIONAL(rmRegister)
765 HANDLE_OPTIONAL(relocation)
767 case X86Local::MRM0m:
768 case X86Local::MRM1m:
769 case X86Local::MRM2m:
770 case X86Local::MRM3m:
771 case X86Local::MRM4m:
772 case X86Local::MRM5m:
773 case X86Local::MRM6m:
774 case X86Local::MRM7m:
775 // Operand 1 is a memory operand (possibly SIB-extended)
776 // Operand 2 (optional) is an immediate or relocation.
778 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
779 "Unexpected number of operands for MRMnMFrm");
781 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
782 "Unexpected number of operands for MRMnMFrm");
784 HANDLE_OPERAND(vvvvRegister)
785 HANDLE_OPERAND(memory)
786 HANDLE_OPTIONAL(relocation)
788 case X86Local::RawFrmImm8:
789 // operand 1 is a 16-bit immediate
790 // operand 2 is an 8-bit immediate
791 assert(numPhysicalOperands == 2 &&
792 "Unexpected number of operands for X86Local::RawFrmImm8");
793 HANDLE_OPERAND(immediate)
794 HANDLE_OPERAND(immediate)
796 case X86Local::RawFrmImm16:
797 // operand 1 is a 16-bit immediate
798 // operand 2 is a 16-bit immediate
799 HANDLE_OPERAND(immediate)
800 HANDLE_OPERAND(immediate)
802 case X86Local::MRMInitReg:
807 #undef HANDLE_OPERAND
808 #undef HANDLE_OPTIONAL
811 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
812 // Special cases where the LLVM tables are not complete
814 #define MAP(from, to) \
815 case X86Local::MRM_##from: \
816 filter = new ExactFilter(0x##from); \
819 OpcodeType opcodeType = (OpcodeType)-1;
821 ModRMFilter* filter = NULL;
822 uint8_t opcodeToSet = 0;
825 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
829 opcodeType = TWOBYTE;
833 if (needsModRMForDecode(Form))
834 filter = new ModFilter(isRegFormat(Form));
836 filter = new DumbFilter();
838 #define EXTENSION_TABLE(n) case 0x##n:
839 TWO_BYTE_EXTENSION_TABLES
840 #undef EXTENSION_TABLE
843 llvm_unreachable("Unhandled two-byte extended opcode");
844 case X86Local::MRM0r:
845 case X86Local::MRM1r:
846 case X86Local::MRM2r:
847 case X86Local::MRM3r:
848 case X86Local::MRM4r:
849 case X86Local::MRM5r:
850 case X86Local::MRM6r:
851 case X86Local::MRM7r:
852 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
854 case X86Local::MRM0m:
855 case X86Local::MRM1m:
856 case X86Local::MRM2m:
857 case X86Local::MRM3m:
858 case X86Local::MRM4m:
859 case X86Local::MRM5m:
860 case X86Local::MRM6m:
861 case X86Local::MRM7m:
862 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
868 opcodeToSet = Opcode;
873 opcodeType = THREEBYTE_38;
876 if (needsModRMForDecode(Form))
877 filter = new ModFilter(isRegFormat(Form));
879 filter = new DumbFilter();
881 #define EXTENSION_TABLE(n) case 0x##n:
882 THREE_BYTE_38_EXTENSION_TABLES
883 #undef EXTENSION_TABLE
886 llvm_unreachable("Unhandled two-byte extended opcode");
887 case X86Local::MRM0r:
888 case X86Local::MRM1r:
889 case X86Local::MRM2r:
890 case X86Local::MRM3r:
891 case X86Local::MRM4r:
892 case X86Local::MRM5r:
893 case X86Local::MRM6r:
894 case X86Local::MRM7r:
895 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
897 case X86Local::MRM0m:
898 case X86Local::MRM1m:
899 case X86Local::MRM2m:
900 case X86Local::MRM3m:
901 case X86Local::MRM4m:
902 case X86Local::MRM5m:
903 case X86Local::MRM6m:
904 case X86Local::MRM7m:
905 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
911 opcodeToSet = Opcode;
915 opcodeType = THREEBYTE_3A;
916 if (needsModRMForDecode(Form))
917 filter = new ModFilter(isRegFormat(Form));
919 filter = new DumbFilter();
920 opcodeToSet = Opcode;
923 opcodeType = THREEBYTE_A6;
924 if (needsModRMForDecode(Form))
925 filter = new ModFilter(isRegFormat(Form));
927 filter = new DumbFilter();
928 opcodeToSet = Opcode;
931 opcodeType = THREEBYTE_A7;
932 if (needsModRMForDecode(Form))
933 filter = new ModFilter(isRegFormat(Form));
935 filter = new DumbFilter();
936 opcodeToSet = Opcode;
946 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
947 opcodeType = ONEBYTE;
948 if (Form == X86Local::AddRegFrm) {
949 Spec->modifierType = MODIFIER_MODRM;
950 Spec->modifierBase = Opcode;
951 filter = new AddRegEscapeFilter(Opcode);
953 filter = new EscapeFilter(true, Opcode);
955 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
959 opcodeType = ONEBYTE;
961 #define EXTENSION_TABLE(n) case 0x##n:
962 ONE_BYTE_EXTENSION_TABLES
963 #undef EXTENSION_TABLE
966 llvm_unreachable("Fell through the cracks of a single-byte "
968 case X86Local::MRM0r:
969 case X86Local::MRM1r:
970 case X86Local::MRM2r:
971 case X86Local::MRM3r:
972 case X86Local::MRM4r:
973 case X86Local::MRM5r:
974 case X86Local::MRM6r:
975 case X86Local::MRM7r:
976 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
978 case X86Local::MRM0m:
979 case X86Local::MRM1m:
980 case X86Local::MRM2m:
981 case X86Local::MRM3m:
982 case X86Local::MRM4m:
983 case X86Local::MRM5m:
984 case X86Local::MRM6m:
985 case X86Local::MRM7m:
986 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
999 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1002 if (needsModRMForDecode(Form))
1003 filter = new ModFilter(isRegFormat(Form));
1005 filter = new DumbFilter();
1007 } // switch (Opcode)
1008 opcodeToSet = Opcode;
1009 } // switch (Prefix)
1011 assert(opcodeType != (OpcodeType)-1 &&
1012 "Opcode type not set");
1013 assert(filter && "Filter not set");
1015 if (Form == X86Local::AddRegFrm) {
1016 if(Spec->modifierType != MODIFIER_MODRM) {
1017 assert(opcodeToSet < 0xf9 &&
1018 "Not enough room for all ADDREG_FRM operands");
1020 uint8_t currentOpcode;
1022 for (currentOpcode = opcodeToSet;
1023 currentOpcode < opcodeToSet + 8;
1025 tables.setTableFields(opcodeType,
1029 UID, Is32Bit, IgnoresVEX_L);
1031 Spec->modifierType = MODIFIER_OPCODE;
1032 Spec->modifierBase = opcodeToSet;
1034 // modifierBase was set where MODIFIER_MODRM was set
1035 tables.setTableFields(opcodeType,
1039 UID, Is32Bit, IgnoresVEX_L);
1042 tables.setTableFields(opcodeType,
1046 UID, Is32Bit, IgnoresVEX_L);
1048 Spec->modifierType = MODIFIER_NONE;
1049 Spec->modifierBase = opcodeToSet;
1057 #define TYPE(str, type) if (s == str) return type;
1058 OperandType RecognizableInstr::typeFromString(const std::string &s,
1060 bool hasREX_WPrefix,
1061 bool hasOpSizePrefix) {
1063 // For SSE instructions, we ignore the OpSize prefix and force operand
1065 TYPE("GR16", TYPE_R16)
1066 TYPE("GR32", TYPE_R32)
1067 TYPE("GR64", TYPE_R64)
1069 if(hasREX_WPrefix) {
1070 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1072 TYPE("GR32", TYPE_R32)
1074 if(!hasOpSizePrefix) {
1075 // For instructions without an OpSize prefix, a declared 16-bit register or
1076 // immediate encoding is special.
1077 TYPE("GR16", TYPE_R16)
1078 TYPE("i16imm", TYPE_IMM16)
1080 TYPE("i16mem", TYPE_Mv)
1081 TYPE("i16imm", TYPE_IMMv)
1082 TYPE("i16i8imm", TYPE_IMMv)
1083 TYPE("GR16", TYPE_Rv)
1084 TYPE("i32mem", TYPE_Mv)
1085 TYPE("i32imm", TYPE_IMMv)
1086 TYPE("i32i8imm", TYPE_IMM32)
1087 TYPE("u32u8imm", TYPE_IMM32)
1088 TYPE("GR32", TYPE_Rv)
1089 TYPE("i64mem", TYPE_Mv)
1090 TYPE("i64i32imm", TYPE_IMM64)
1091 TYPE("i64i8imm", TYPE_IMM64)
1092 TYPE("GR64", TYPE_R64)
1093 TYPE("i8mem", TYPE_M8)
1094 TYPE("i8imm", TYPE_IMM8)
1095 TYPE("GR8", TYPE_R8)
1096 TYPE("VR128", TYPE_XMM128)
1097 TYPE("f128mem", TYPE_M128)
1098 TYPE("f256mem", TYPE_M256)
1099 TYPE("FR64", TYPE_XMM64)
1100 TYPE("f64mem", TYPE_M64FP)
1101 TYPE("sdmem", TYPE_M64FP)
1102 TYPE("FR32", TYPE_XMM32)
1103 TYPE("f32mem", TYPE_M32FP)
1104 TYPE("ssmem", TYPE_M32FP)
1105 TYPE("RST", TYPE_ST)
1106 TYPE("i128mem", TYPE_M128)
1107 TYPE("i256mem", TYPE_M256)
1108 TYPE("i64i32imm_pcrel", TYPE_REL64)
1109 TYPE("i16imm_pcrel", TYPE_REL16)
1110 TYPE("i32imm_pcrel", TYPE_REL32)
1111 TYPE("SSECC", TYPE_IMM3)
1112 TYPE("brtarget", TYPE_RELv)
1113 TYPE("uncondbrtarget", TYPE_RELv)
1114 TYPE("brtarget8", TYPE_REL8)
1115 TYPE("f80mem", TYPE_M80FP)
1116 TYPE("lea32mem", TYPE_LEA)
1117 TYPE("lea64_32mem", TYPE_LEA)
1118 TYPE("lea64mem", TYPE_LEA)
1119 TYPE("VR64", TYPE_MM64)
1120 TYPE("i64imm", TYPE_IMMv)
1121 TYPE("opaque32mem", TYPE_M1616)
1122 TYPE("opaque48mem", TYPE_M1632)
1123 TYPE("opaque80mem", TYPE_M1664)
1124 TYPE("opaque512mem", TYPE_M512)
1125 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1126 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1127 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1128 TYPE("offset8", TYPE_MOFFS8)
1129 TYPE("offset16", TYPE_MOFFS16)
1130 TYPE("offset32", TYPE_MOFFS32)
1131 TYPE("offset64", TYPE_MOFFS64)
1132 TYPE("VR256", TYPE_XMM256)
1133 TYPE("GR16_NOAX", TYPE_Rv)
1134 TYPE("GR32_NOAX", TYPE_Rv)
1135 TYPE("GR64_NOAX", TYPE_R64)
1136 errs() << "Unhandled type string " << s << "\n";
1137 llvm_unreachable("Unhandled type string");
1141 #define ENCODING(str, encoding) if (s == str) return encoding;
1142 OperandEncoding RecognizableInstr::immediateEncodingFromString
1143 (const std::string &s,
1144 bool hasOpSizePrefix) {
1145 if(!hasOpSizePrefix) {
1146 // For instructions without an OpSize prefix, a declared 16-bit register or
1147 // immediate encoding is special.
1148 ENCODING("i16imm", ENCODING_IW)
1150 ENCODING("i32i8imm", ENCODING_IB)
1151 ENCODING("u32u8imm", ENCODING_IB)
1152 ENCODING("SSECC", ENCODING_IB)
1153 ENCODING("i16imm", ENCODING_Iv)
1154 ENCODING("i16i8imm", ENCODING_IB)
1155 ENCODING("i32imm", ENCODING_Iv)
1156 ENCODING("i64i32imm", ENCODING_ID)
1157 ENCODING("i64i8imm", ENCODING_IB)
1158 ENCODING("i8imm", ENCODING_IB)
1159 // This is not a typo. Instructions like BLENDVPD put
1160 // register IDs in 8-bit immediates nowadays.
1161 ENCODING("VR256", ENCODING_IB)
1162 ENCODING("VR128", ENCODING_IB)
1163 errs() << "Unhandled immediate encoding " << s << "\n";
1164 llvm_unreachable("Unhandled immediate encoding");
1167 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1168 (const std::string &s,
1169 bool hasOpSizePrefix) {
1170 ENCODING("GR16", ENCODING_RM)
1171 ENCODING("GR32", ENCODING_RM)
1172 ENCODING("GR64", ENCODING_RM)
1173 ENCODING("GR8", ENCODING_RM)
1174 ENCODING("VR128", ENCODING_RM)
1175 ENCODING("FR64", ENCODING_RM)
1176 ENCODING("FR32", ENCODING_RM)
1177 ENCODING("VR64", ENCODING_RM)
1178 ENCODING("VR256", ENCODING_RM)
1179 errs() << "Unhandled R/M register encoding " << s << "\n";
1180 llvm_unreachable("Unhandled R/M register encoding");
1183 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1184 (const std::string &s,
1185 bool hasOpSizePrefix) {
1186 ENCODING("GR16", ENCODING_REG)
1187 ENCODING("GR32", ENCODING_REG)
1188 ENCODING("GR64", ENCODING_REG)
1189 ENCODING("GR8", ENCODING_REG)
1190 ENCODING("VR128", ENCODING_REG)
1191 ENCODING("FR64", ENCODING_REG)
1192 ENCODING("FR32", ENCODING_REG)
1193 ENCODING("VR64", ENCODING_REG)
1194 ENCODING("SEGMENT_REG", ENCODING_REG)
1195 ENCODING("DEBUG_REG", ENCODING_REG)
1196 ENCODING("CONTROL_REG", ENCODING_REG)
1197 ENCODING("VR256", ENCODING_REG)
1198 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1199 llvm_unreachable("Unhandled reg/opcode register encoding");
1202 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1203 (const std::string &s,
1204 bool hasOpSizePrefix) {
1205 ENCODING("GR32", ENCODING_VVVV)
1206 ENCODING("GR64", ENCODING_VVVV)
1207 ENCODING("FR32", ENCODING_VVVV)
1208 ENCODING("FR64", ENCODING_VVVV)
1209 ENCODING("VR128", ENCODING_VVVV)
1210 ENCODING("VR256", ENCODING_VVVV)
1211 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1212 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1215 OperandEncoding RecognizableInstr::memoryEncodingFromString
1216 (const std::string &s,
1217 bool hasOpSizePrefix) {
1218 ENCODING("i16mem", ENCODING_RM)
1219 ENCODING("i32mem", ENCODING_RM)
1220 ENCODING("i64mem", ENCODING_RM)
1221 ENCODING("i8mem", ENCODING_RM)
1222 ENCODING("ssmem", ENCODING_RM)
1223 ENCODING("sdmem", ENCODING_RM)
1224 ENCODING("f128mem", ENCODING_RM)
1225 ENCODING("f256mem", ENCODING_RM)
1226 ENCODING("f64mem", ENCODING_RM)
1227 ENCODING("f32mem", ENCODING_RM)
1228 ENCODING("i128mem", ENCODING_RM)
1229 ENCODING("i256mem", ENCODING_RM)
1230 ENCODING("f80mem", ENCODING_RM)
1231 ENCODING("lea32mem", ENCODING_RM)
1232 ENCODING("lea64_32mem", ENCODING_RM)
1233 ENCODING("lea64mem", ENCODING_RM)
1234 ENCODING("opaque32mem", ENCODING_RM)
1235 ENCODING("opaque48mem", ENCODING_RM)
1236 ENCODING("opaque80mem", ENCODING_RM)
1237 ENCODING("opaque512mem", ENCODING_RM)
1238 errs() << "Unhandled memory encoding " << s << "\n";
1239 llvm_unreachable("Unhandled memory encoding");
1242 OperandEncoding RecognizableInstr::relocationEncodingFromString
1243 (const std::string &s,
1244 bool hasOpSizePrefix) {
1245 if(!hasOpSizePrefix) {
1246 // For instructions without an OpSize prefix, a declared 16-bit register or
1247 // immediate encoding is special.
1248 ENCODING("i16imm", ENCODING_IW)
1250 ENCODING("i16imm", ENCODING_Iv)
1251 ENCODING("i16i8imm", ENCODING_IB)
1252 ENCODING("i32imm", ENCODING_Iv)
1253 ENCODING("i32i8imm", ENCODING_IB)
1254 ENCODING("i64i32imm", ENCODING_ID)
1255 ENCODING("i64i8imm", ENCODING_IB)
1256 ENCODING("i8imm", ENCODING_IB)
1257 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1258 ENCODING("i16imm_pcrel", ENCODING_IW)
1259 ENCODING("i32imm_pcrel", ENCODING_ID)
1260 ENCODING("brtarget", ENCODING_Iv)
1261 ENCODING("brtarget8", ENCODING_IB)
1262 ENCODING("i64imm", ENCODING_IO)
1263 ENCODING("offset8", ENCODING_Ia)
1264 ENCODING("offset16", ENCODING_Ia)
1265 ENCODING("offset32", ENCODING_Ia)
1266 ENCODING("offset64", ENCODING_Ia)
1267 errs() << "Unhandled relocation encoding " << s << "\n";
1268 llvm_unreachable("Unhandled relocation encoding");
1271 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1272 (const std::string &s,
1273 bool hasOpSizePrefix) {
1274 ENCODING("RST", ENCODING_I)
1275 ENCODING("GR32", ENCODING_Rv)
1276 ENCODING("GR64", ENCODING_RO)
1277 ENCODING("GR16", ENCODING_Rv)
1278 ENCODING("GR8", ENCODING_RB)
1279 ENCODING("GR16_NOAX", ENCODING_Rv)
1280 ENCODING("GR32_NOAX", ENCODING_Rv)
1281 ENCODING("GR64_NOAX", ENCODING_RO)
1282 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1283 llvm_unreachable("Unhandled opcode modifier encoding");