1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
86 // If rows are added to the opcode extension tables, then corresponding entries
87 // must be added here.
89 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
90 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 // If the row corresponds to two bytes where the first is 0f, add an entry for
93 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 // If the row corresponds to some other set of bytes, you will need to modify
96 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
97 // to the X86 TD files, except in two cases: if the first two bytes of such a
98 // new combination are 0f 38 or 0f 3a, you just have to add maps called
99 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
100 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
101 // in RecognizableInstr::emitDecodePath().
103 #define ONE_BYTE_EXTENSION_TABLES \
104 EXTENSION_TABLE(80) \
105 EXTENSION_TABLE(81) \
106 EXTENSION_TABLE(82) \
107 EXTENSION_TABLE(83) \
108 EXTENSION_TABLE(8f) \
109 EXTENSION_TABLE(c0) \
110 EXTENSION_TABLE(c1) \
111 EXTENSION_TABLE(c6) \
112 EXTENSION_TABLE(c7) \
113 EXTENSION_TABLE(d0) \
114 EXTENSION_TABLE(d1) \
115 EXTENSION_TABLE(d2) \
116 EXTENSION_TABLE(d3) \
117 EXTENSION_TABLE(f6) \
118 EXTENSION_TABLE(f7) \
119 EXTENSION_TABLE(fe) \
122 #define TWO_BYTE_EXTENSION_TABLES \
123 EXTENSION_TABLE(00) \
124 EXTENSION_TABLE(01) \
125 EXTENSION_TABLE(0d) \
126 EXTENSION_TABLE(18) \
127 EXTENSION_TABLE(71) \
128 EXTENSION_TABLE(72) \
129 EXTENSION_TABLE(73) \
130 EXTENSION_TABLE(ae) \
131 EXTENSION_TABLE(ba) \
134 #define THREE_BYTE_38_EXTENSION_TABLES \
137 using namespace X86Disassembler;
139 /// needsModRMForDecode - Indicates whether a particular instruction requires a
140 /// ModR/M byte for the instruction to be properly decoded. For example, a
141 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
144 /// @param form - The form of the instruction.
145 /// @return - true if the form implies that a ModR/M byte is required, false
147 static bool needsModRMForDecode(uint8_t form) {
148 if (form == X86Local::MRMDestReg ||
149 form == X86Local::MRMDestMem ||
150 form == X86Local::MRMSrcReg ||
151 form == X86Local::MRMSrcMem ||
152 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
153 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159 /// isRegFormat - Indicates whether a particular form requires the Mod field of
160 /// the ModR/M byte to be 0b11.
162 /// @param form - The form of the instruction.
163 /// @return - true if the form implies that Mod must be 0b11, false
165 static bool isRegFormat(uint8_t form) {
166 if (form == X86Local::MRMDestReg ||
167 form == X86Local::MRMSrcReg ||
168 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
175 /// Useful for switch statements and the like.
177 /// @param init - A reference to the BitsInit to be decoded.
178 /// @return - The field, with the first bit in the BitsInit as the lowest
180 static uint8_t byteFromBitsInit(BitsInit &init) {
181 int width = init.getNumBits();
183 assert(width <= 8 && "Field is too large for uint8_t!");
190 for (index = 0; index < width; index++) {
191 if (static_cast<BitInit*>(init.getBit(index))->getValue())
200 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
201 /// name of the field.
203 /// @param rec - The record from which to extract the value.
204 /// @param name - The name of the field in the record.
205 /// @return - The field, as translated by byteFromBitsInit().
206 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
207 BitsInit* bits = rec->getValueAsBitsInit(name);
208 return byteFromBitsInit(*bits);
211 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
212 const CodeGenInstruction &insn,
217 Name = Rec->getName();
218 Spec = &tables.specForUID(UID);
220 if (!Rec->isSubClassOf("X86Inst")) {
221 ShouldBeEmitted = false;
225 Prefix = byteFromRec(Rec, "Prefix");
226 Opcode = byteFromRec(Rec, "Opcode");
227 Form = byteFromRec(Rec, "FormBits");
228 SegOvr = byteFromRec(Rec, "SegOvrBits");
230 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
231 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
232 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
233 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
234 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
235 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
236 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
237 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
238 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
239 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
240 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
241 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
242 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
243 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
244 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
246 Name = Rec->getName();
247 AsmString = Rec->getValueAsString("AsmString");
249 Operands = &insn.Operands.OperandList;
251 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
252 (Name.find("CRC32") != Name.npos);
253 HasFROperands = hasFROperands();
254 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
256 // Check for 64-bit inst which does not require REX
259 // FIXME: Is there some better way to check for In64BitMode?
260 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
261 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
262 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
266 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
271 // FIXME: These instructions aren't marked as 64-bit in any way
272 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
273 Rec->getName() == "MASKMOVDQU64" ||
274 Rec->getName() == "POPFS64" ||
275 Rec->getName() == "POPGS64" ||
276 Rec->getName() == "PUSHFS64" ||
277 Rec->getName() == "PUSHGS64" ||
278 Rec->getName() == "REX64_PREFIX" ||
279 Rec->getName().find("MOV64") != Name.npos ||
280 Rec->getName().find("PUSH64") != Name.npos ||
281 Rec->getName().find("POP64") != Name.npos;
283 ShouldBeEmitted = true;
286 void RecognizableInstr::processInstr(DisassemblerTables &tables,
287 const CodeGenInstruction &insn,
290 // Ignore "asm parser only" instructions.
291 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
294 RecognizableInstr recogInstr(tables, insn, uid);
296 recogInstr.emitInstructionSpecifier(tables);
298 if (recogInstr.shouldBeEmitted())
299 recogInstr.emitDecodePath(tables);
302 #define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
303 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
305 InstructionContext RecognizableInstr::insnContext() const {
306 InstructionContext insnContext;
309 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
311 sprintf(msg, "Don't support VEX.L if EVEX_L2 is enabled: %s", Name.c_str());
312 llvm_unreachable(msg);
315 if (HasVEX_LPrefix && HasVEX_WPrefix) {
317 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
318 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
319 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
320 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
321 Prefix == X86Local::TAXD)
322 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
324 insnContext = EVEX_KB(IC_EVEX_L_W);
325 } else if (HasVEX_LPrefix) {
328 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
329 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
330 insnContext = EVEX_KB(IC_EVEX_L_XS);
331 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
332 Prefix == X86Local::TAXD)
333 insnContext = EVEX_KB(IC_EVEX_L_XD);
335 insnContext = EVEX_KB(IC_EVEX_L);
337 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
340 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
341 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
343 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
344 Prefix == X86Local::TAXD)
345 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
347 insnContext = EVEX_KB(IC_EVEX_L2_W);
348 } else if (HasEVEX_L2Prefix) {
351 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
352 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
353 Prefix == X86Local::TAXD)
354 insnContext = EVEX_KB(IC_EVEX_L2_XD);
355 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
356 insnContext = EVEX_KB(IC_EVEX_L2_XS);
358 insnContext = EVEX_KB(IC_EVEX_L2);
360 else if (HasVEX_WPrefix) {
363 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
364 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
365 insnContext = EVEX_KB(IC_EVEX_W_XS);
366 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
367 Prefix == X86Local::TAXD)
368 insnContext = EVEX_KB(IC_EVEX_W_XD);
370 insnContext = EVEX_KB(IC_EVEX_W);
373 else if (HasOpSizePrefix)
374 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
375 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
376 Prefix == X86Local::TAXD)
377 insnContext = EVEX_KB(IC_EVEX_XD);
378 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
379 insnContext = EVEX_KB(IC_EVEX_XS);
381 insnContext = EVEX_KB(IC_EVEX);
383 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
384 if (HasVEX_LPrefix && HasVEX_WPrefix) {
386 insnContext = IC_VEX_L_W_OPSIZE;
387 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
388 insnContext = IC_VEX_L_W_XS;
389 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
390 Prefix == X86Local::TAXD)
391 insnContext = IC_VEX_L_W_XD;
393 insnContext = IC_VEX_L_W;
394 } else if (HasOpSizePrefix && HasVEX_LPrefix)
395 insnContext = IC_VEX_L_OPSIZE;
396 else if (HasOpSizePrefix && HasVEX_WPrefix)
397 insnContext = IC_VEX_W_OPSIZE;
398 else if (HasOpSizePrefix)
399 insnContext = IC_VEX_OPSIZE;
400 else if (HasVEX_LPrefix &&
401 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
402 insnContext = IC_VEX_L_XS;
403 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
404 Prefix == X86Local::T8XD ||
405 Prefix == X86Local::TAXD))
406 insnContext = IC_VEX_L_XD;
407 else if (HasVEX_WPrefix &&
408 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
409 insnContext = IC_VEX_W_XS;
410 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
411 Prefix == X86Local::T8XD ||
412 Prefix == X86Local::TAXD))
413 insnContext = IC_VEX_W_XD;
414 else if (HasVEX_WPrefix)
415 insnContext = IC_VEX_W;
416 else if (HasVEX_LPrefix)
417 insnContext = IC_VEX_L;
418 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
419 Prefix == X86Local::TAXD)
420 insnContext = IC_VEX_XD;
421 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
422 insnContext = IC_VEX_XS;
424 insnContext = IC_VEX;
425 } else if (Is64Bit || HasREX_WPrefix) {
426 if (HasREX_WPrefix && HasOpSizePrefix)
427 insnContext = IC_64BIT_REXW_OPSIZE;
428 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
429 Prefix == X86Local::T8XD ||
430 Prefix == X86Local::TAXD))
431 insnContext = IC_64BIT_XD_OPSIZE;
432 else if (HasOpSizePrefix &&
433 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
434 insnContext = IC_64BIT_XS_OPSIZE;
435 else if (HasOpSizePrefix)
436 insnContext = IC_64BIT_OPSIZE;
437 else if (HasAdSizePrefix)
438 insnContext = IC_64BIT_ADSIZE;
439 else if (HasREX_WPrefix &&
440 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
441 insnContext = IC_64BIT_REXW_XS;
442 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
443 Prefix == X86Local::T8XD ||
444 Prefix == X86Local::TAXD))
445 insnContext = IC_64BIT_REXW_XD;
446 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
447 Prefix == X86Local::TAXD)
448 insnContext = IC_64BIT_XD;
449 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
450 insnContext = IC_64BIT_XS;
451 else if (HasREX_WPrefix)
452 insnContext = IC_64BIT_REXW;
454 insnContext = IC_64BIT;
456 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
457 Prefix == X86Local::T8XD ||
458 Prefix == X86Local::TAXD))
459 insnContext = IC_XD_OPSIZE;
460 else if (HasOpSizePrefix &&
461 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
462 insnContext = IC_XS_OPSIZE;
463 else if (HasOpSizePrefix)
464 insnContext = IC_OPSIZE;
465 else if (HasAdSizePrefix)
466 insnContext = IC_ADSIZE;
467 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
468 Prefix == X86Local::TAXD)
470 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
471 Prefix == X86Local::REP)
480 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
485 // Filter out intrinsics
487 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
489 if (Form == X86Local::Pseudo ||
490 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
491 return FILTER_STRONG;
494 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
495 // printed as a separate "instruction".
497 if (Name.find("_Int") != Name.npos ||
498 Name.find("Int_") != Name.npos)
499 return FILTER_STRONG;
501 // Filter out instructions with segment override prefixes.
502 // They're too messy to handle now and we'll special case them if needed.
505 return FILTER_STRONG;
513 // Filter out instructions with a LOCK prefix;
514 // prefer forms that do not have the prefix
518 // Filter out alternate forms of AVX instructions
519 if (Name.find("_alt") != Name.npos ||
520 Name.find("XrYr") != Name.npos ||
521 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
522 Name.find("_64mr") != Name.npos ||
523 Name.find("Xrr") != Name.npos ||
524 Name.find("rr64") != Name.npos)
529 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
531 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
534 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
536 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
538 if (Name.find("Fs") != Name.npos)
540 if (Name == "PUSH64i16" ||
541 Name == "MOVPQI2QImr" ||
542 Name == "VMOVPQI2QImr" ||
543 Name == "MMX_MOVD64rrv164" ||
544 Name == "MOV64ri64i32" ||
545 Name == "VMASKMOVDQU64" ||
546 Name == "VEXTRACTPSrr64" ||
547 Name == "VMOVQd64rr" ||
548 Name == "VMOVQs64rr")
551 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
552 // For now, just prefer the REP versions.
553 if (Name == "XACQUIRE_PREFIX" ||
554 Name == "XRELEASE_PREFIX")
557 if (HasFROperands && Name.find("MOV") != Name.npos &&
558 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
559 (Name.find("to") != Name.npos)))
560 return FILTER_STRONG;
562 return FILTER_NORMAL;
565 bool RecognizableInstr::hasFROperands() const {
566 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
567 unsigned numOperands = OperandList.size();
569 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
570 const std::string &recName = OperandList[operandIndex].Rec->getName();
572 if (recName.find("FR") != recName.npos)
578 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
579 unsigned &physicalOperandIndex,
580 unsigned &numPhysicalOperands,
581 const unsigned *operandMapping,
582 OperandEncoding (*encodingFromString)
584 bool hasOpSizePrefix)) {
586 if (physicalOperandIndex >= numPhysicalOperands)
589 assert(physicalOperandIndex < numPhysicalOperands);
592 while (operandMapping[operandIndex] != operandIndex) {
593 Spec->operands[operandIndex].encoding = ENCODING_DUP;
594 Spec->operands[operandIndex].type =
595 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
599 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
601 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
603 Spec->operands[operandIndex].type = typeFromString(typeName,
609 ++physicalOperandIndex;
612 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
615 if (!ShouldBeEmitted)
620 Spec->filtered = true;
623 ShouldBeEmitted = false;
629 Spec->insnContext = insnContext();
631 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
633 unsigned numOperands = OperandList.size();
634 unsigned numPhysicalOperands = 0;
636 // operandMapping maps from operands in OperandList to their originals.
637 // If operandMapping[i] != i, then the entry is a duplicate.
638 unsigned operandMapping[X86_MAX_OPERANDS];
639 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
641 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
642 if (OperandList[operandIndex].Constraints.size()) {
643 const CGIOperandList::ConstraintInfo &Constraint =
644 OperandList[operandIndex].Constraints[0];
645 if (Constraint.isTied()) {
646 operandMapping[operandIndex] = operandIndex;
647 operandMapping[Constraint.getTiedOperand()] = operandIndex;
649 ++numPhysicalOperands;
650 operandMapping[operandIndex] = operandIndex;
653 ++numPhysicalOperands;
654 operandMapping[operandIndex] = operandIndex;
658 #define HANDLE_OPERAND(class) \
659 handleOperand(false, \
661 physicalOperandIndex, \
662 numPhysicalOperands, \
664 class##EncodingFromString);
666 #define HANDLE_OPTIONAL(class) \
667 handleOperand(true, \
669 physicalOperandIndex, \
670 numPhysicalOperands, \
672 class##EncodingFromString);
674 // operandIndex should always be < numOperands
675 unsigned operandIndex = 0;
676 // physicalOperandIndex should always be < numPhysicalOperands
677 unsigned physicalOperandIndex = 0;
680 case X86Local::RawFrm:
681 // Operand 1 (optional) is an address or immediate.
682 // Operand 2 (optional) is an immediate.
683 assert(numPhysicalOperands <= 2 &&
684 "Unexpected number of operands for RawFrm");
685 HANDLE_OPTIONAL(relocation)
686 HANDLE_OPTIONAL(immediate)
688 case X86Local::AddRegFrm:
689 // Operand 1 is added to the opcode.
690 // Operand 2 (optional) is an address.
691 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
692 "Unexpected number of operands for AddRegFrm");
693 HANDLE_OPERAND(opcodeModifier)
694 HANDLE_OPTIONAL(relocation)
696 case X86Local::MRMDestReg:
697 // Operand 1 is a register operand in the R/M field.
698 // Operand 2 is a register operand in the Reg/Opcode field.
699 // - In AVX, there is a register operand in the VEX.vvvv field here -
700 // Operand 3 (optional) is an immediate.
702 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
703 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
705 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
706 "Unexpected number of operands for MRMDestRegFrm");
708 HANDLE_OPERAND(rmRegister)
711 // FIXME: In AVX, the register below becomes the one encoded
712 // in ModRMVEX and the one above the one in the VEX.VVVV field
713 HANDLE_OPERAND(vvvvRegister)
715 HANDLE_OPERAND(roRegister)
716 HANDLE_OPTIONAL(immediate)
718 case X86Local::MRMDestMem:
719 // Operand 1 is a memory operand (possibly SIB-extended)
720 // Operand 2 is a register operand in the Reg/Opcode field.
721 // - In AVX, there is a register operand in the VEX.vvvv field here -
722 // Operand 3 (optional) is an immediate.
724 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
725 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
727 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
728 "Unexpected number of operands for MRMDestMemFrm");
729 HANDLE_OPERAND(memory)
732 HANDLE_OPERAND(writemaskRegister)
735 // FIXME: In AVX, the register below becomes the one encoded
736 // in ModRMVEX and the one above the one in the VEX.VVVV field
737 HANDLE_OPERAND(vvvvRegister)
739 HANDLE_OPERAND(roRegister)
740 HANDLE_OPTIONAL(immediate)
742 case X86Local::MRMSrcReg:
743 // Operand 1 is a register operand in the Reg/Opcode field.
744 // Operand 2 is a register operand in the R/M field.
745 // - In AVX, there is a register operand in the VEX.vvvv field here -
746 // Operand 3 (optional) is an immediate.
747 // Operand 4 (optional) is an immediate.
749 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
750 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
751 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
753 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
754 "Unexpected number of operands for MRMSrcRegFrm");
756 HANDLE_OPERAND(roRegister)
759 HANDLE_OPERAND(writemaskRegister)
762 // FIXME: In AVX, the register below becomes the one encoded
763 // in ModRMVEX and the one above the one in the VEX.VVVV field
764 HANDLE_OPERAND(vvvvRegister)
767 HANDLE_OPERAND(immediate)
769 HANDLE_OPERAND(rmRegister)
771 if (HasVEX_4VOp3Prefix)
772 HANDLE_OPERAND(vvvvRegister)
774 if (!HasMemOp4Prefix)
775 HANDLE_OPTIONAL(immediate)
776 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
777 HANDLE_OPTIONAL(immediate)
779 case X86Local::MRMSrcMem:
780 // Operand 1 is a register operand in the Reg/Opcode field.
781 // Operand 2 is a memory operand (possibly SIB-extended)
782 // - In AVX, there is a register operand in the VEX.vvvv field here -
783 // Operand 3 (optional) is an immediate.
785 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
786 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
787 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
789 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
790 "Unexpected number of operands for MRMSrcMemFrm");
792 HANDLE_OPERAND(roRegister)
795 HANDLE_OPERAND(writemaskRegister)
798 // FIXME: In AVX, the register below becomes the one encoded
799 // in ModRMVEX and the one above the one in the VEX.VVVV field
800 HANDLE_OPERAND(vvvvRegister)
803 HANDLE_OPERAND(immediate)
805 HANDLE_OPERAND(memory)
807 if (HasVEX_4VOp3Prefix)
808 HANDLE_OPERAND(vvvvRegister)
810 if (!HasMemOp4Prefix)
811 HANDLE_OPTIONAL(immediate)
812 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
814 case X86Local::MRM0r:
815 case X86Local::MRM1r:
816 case X86Local::MRM2r:
817 case X86Local::MRM3r:
818 case X86Local::MRM4r:
819 case X86Local::MRM5r:
820 case X86Local::MRM6r:
821 case X86Local::MRM7r:
822 // Operand 1 is a register operand in the R/M field.
823 // Operand 2 (optional) is an immediate or relocation.
824 // Operand 3 (optional) is an immediate.
826 assert(numPhysicalOperands <= 3 &&
827 "Unexpected number of operands for MRMnRFrm with VEX_4V");
829 assert(numPhysicalOperands <= 3 &&
830 "Unexpected number of operands for MRMnRFrm");
832 HANDLE_OPERAND(vvvvRegister)
833 HANDLE_OPTIONAL(rmRegister)
834 HANDLE_OPTIONAL(relocation)
835 HANDLE_OPTIONAL(immediate)
837 case X86Local::MRM0m:
838 case X86Local::MRM1m:
839 case X86Local::MRM2m:
840 case X86Local::MRM3m:
841 case X86Local::MRM4m:
842 case X86Local::MRM5m:
843 case X86Local::MRM6m:
844 case X86Local::MRM7m:
845 // Operand 1 is a memory operand (possibly SIB-extended)
846 // Operand 2 (optional) is an immediate or relocation.
848 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
849 "Unexpected number of operands for MRMnMFrm");
851 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
852 "Unexpected number of operands for MRMnMFrm");
854 HANDLE_OPERAND(vvvvRegister)
855 HANDLE_OPERAND(memory)
856 HANDLE_OPTIONAL(relocation)
858 case X86Local::RawFrmImm8:
859 // operand 1 is a 16-bit immediate
860 // operand 2 is an 8-bit immediate
861 assert(numPhysicalOperands == 2 &&
862 "Unexpected number of operands for X86Local::RawFrmImm8");
863 HANDLE_OPERAND(immediate)
864 HANDLE_OPERAND(immediate)
866 case X86Local::RawFrmImm16:
867 // operand 1 is a 16-bit immediate
868 // operand 2 is a 16-bit immediate
869 HANDLE_OPERAND(immediate)
870 HANDLE_OPERAND(immediate)
872 case X86Local::MRM_F8:
873 if (Opcode == 0xc6) {
874 assert(numPhysicalOperands == 1 &&
875 "Unexpected number of operands for X86Local::MRM_F8");
876 HANDLE_OPERAND(immediate)
877 } else if (Opcode == 0xc7) {
878 assert(numPhysicalOperands == 1 &&
879 "Unexpected number of operands for X86Local::MRM_F8");
880 HANDLE_OPERAND(relocation)
883 case X86Local::MRMInitReg:
888 #undef HANDLE_OPERAND
889 #undef HANDLE_OPTIONAL
892 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
893 // Special cases where the LLVM tables are not complete
895 #define MAP(from, to) \
896 case X86Local::MRM_##from: \
897 filter = new ExactFilter(0x##from); \
900 OpcodeType opcodeType = (OpcodeType)-1;
902 ModRMFilter* filter = NULL;
903 uint8_t opcodeToSet = 0;
906 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
910 opcodeType = TWOBYTE;
914 if (needsModRMForDecode(Form))
915 filter = new ModFilter(isRegFormat(Form));
917 filter = new DumbFilter();
919 #define EXTENSION_TABLE(n) case 0x##n:
920 TWO_BYTE_EXTENSION_TABLES
921 #undef EXTENSION_TABLE
924 llvm_unreachable("Unhandled two-byte extended opcode");
925 case X86Local::MRM0r:
926 case X86Local::MRM1r:
927 case X86Local::MRM2r:
928 case X86Local::MRM3r:
929 case X86Local::MRM4r:
930 case X86Local::MRM5r:
931 case X86Local::MRM6r:
932 case X86Local::MRM7r:
933 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
935 case X86Local::MRM0m:
936 case X86Local::MRM1m:
937 case X86Local::MRM2m:
938 case X86Local::MRM3m:
939 case X86Local::MRM4m:
940 case X86Local::MRM5m:
941 case X86Local::MRM6m:
942 case X86Local::MRM7m:
943 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
949 opcodeToSet = Opcode;
954 opcodeType = THREEBYTE_38;
957 if (needsModRMForDecode(Form))
958 filter = new ModFilter(isRegFormat(Form));
960 filter = new DumbFilter();
962 #define EXTENSION_TABLE(n) case 0x##n:
963 THREE_BYTE_38_EXTENSION_TABLES
964 #undef EXTENSION_TABLE
967 llvm_unreachable("Unhandled two-byte extended opcode");
968 case X86Local::MRM0r:
969 case X86Local::MRM1r:
970 case X86Local::MRM2r:
971 case X86Local::MRM3r:
972 case X86Local::MRM4r:
973 case X86Local::MRM5r:
974 case X86Local::MRM6r:
975 case X86Local::MRM7r:
976 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
978 case X86Local::MRM0m:
979 case X86Local::MRM1m:
980 case X86Local::MRM2m:
981 case X86Local::MRM3m:
982 case X86Local::MRM4m:
983 case X86Local::MRM5m:
984 case X86Local::MRM6m:
985 case X86Local::MRM7m:
986 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
992 opcodeToSet = Opcode;
996 opcodeType = THREEBYTE_3A;
997 if (needsModRMForDecode(Form))
998 filter = new ModFilter(isRegFormat(Form));
1000 filter = new DumbFilter();
1001 opcodeToSet = Opcode;
1004 opcodeType = THREEBYTE_A6;
1005 if (needsModRMForDecode(Form))
1006 filter = new ModFilter(isRegFormat(Form));
1008 filter = new DumbFilter();
1009 opcodeToSet = Opcode;
1012 opcodeType = THREEBYTE_A7;
1013 if (needsModRMForDecode(Form))
1014 filter = new ModFilter(isRegFormat(Form));
1016 filter = new DumbFilter();
1017 opcodeToSet = Opcode;
1027 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1028 opcodeType = ONEBYTE;
1029 if (Form == X86Local::AddRegFrm) {
1030 Spec->modifierType = MODIFIER_MODRM;
1031 Spec->modifierBase = Opcode;
1032 filter = new AddRegEscapeFilter(Opcode);
1034 filter = new EscapeFilter(true, Opcode);
1036 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1040 opcodeType = ONEBYTE;
1042 #define EXTENSION_TABLE(n) case 0x##n:
1043 ONE_BYTE_EXTENSION_TABLES
1044 #undef EXTENSION_TABLE
1047 llvm_unreachable("Fell through the cracks of a single-byte "
1049 case X86Local::MRM0r:
1050 case X86Local::MRM1r:
1051 case X86Local::MRM2r:
1052 case X86Local::MRM3r:
1053 case X86Local::MRM4r:
1054 case X86Local::MRM5r:
1055 case X86Local::MRM6r:
1056 case X86Local::MRM7r:
1057 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1059 case X86Local::MRM0m:
1060 case X86Local::MRM1m:
1061 case X86Local::MRM2m:
1062 case X86Local::MRM3m:
1063 case X86Local::MRM4m:
1064 case X86Local::MRM5m:
1065 case X86Local::MRM6m:
1066 case X86Local::MRM7m:
1067 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1080 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1083 if (needsModRMForDecode(Form))
1084 filter = new ModFilter(isRegFormat(Form));
1086 filter = new DumbFilter();
1088 } // switch (Opcode)
1089 opcodeToSet = Opcode;
1090 } // switch (Prefix)
1092 assert(opcodeType != (OpcodeType)-1 &&
1093 "Opcode type not set");
1094 assert(filter && "Filter not set");
1096 if (Form == X86Local::AddRegFrm) {
1097 if(Spec->modifierType != MODIFIER_MODRM) {
1098 assert(opcodeToSet < 0xf9 &&
1099 "Not enough room for all ADDREG_FRM operands");
1101 uint8_t currentOpcode;
1103 for (currentOpcode = opcodeToSet;
1104 currentOpcode < opcodeToSet + 8;
1106 tables.setTableFields(opcodeType,
1110 UID, Is32Bit, IgnoresVEX_L);
1112 Spec->modifierType = MODIFIER_OPCODE;
1113 Spec->modifierBase = opcodeToSet;
1115 // modifierBase was set where MODIFIER_MODRM was set
1116 tables.setTableFields(opcodeType,
1120 UID, Is32Bit, IgnoresVEX_L);
1123 tables.setTableFields(opcodeType,
1127 UID, Is32Bit, IgnoresVEX_L);
1129 Spec->modifierType = MODIFIER_NONE;
1130 Spec->modifierBase = opcodeToSet;
1138 #define TYPE(str, type) if (s == str) return type;
1139 OperandType RecognizableInstr::typeFromString(const std::string &s,
1141 bool hasREX_WPrefix,
1142 bool hasOpSizePrefix) {
1144 // For SSE instructions, we ignore the OpSize prefix and force operand
1146 TYPE("GR16", TYPE_R16)
1147 TYPE("GR32", TYPE_R32)
1148 TYPE("GR64", TYPE_R64)
1150 if(hasREX_WPrefix) {
1151 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1153 TYPE("GR32", TYPE_R32)
1155 if(!hasOpSizePrefix) {
1156 // For instructions without an OpSize prefix, a declared 16-bit register or
1157 // immediate encoding is special.
1158 TYPE("GR16", TYPE_R16)
1159 TYPE("i16imm", TYPE_IMM16)
1161 TYPE("i16mem", TYPE_Mv)
1162 TYPE("i16imm", TYPE_IMMv)
1163 TYPE("i16i8imm", TYPE_IMMv)
1164 TYPE("GR16", TYPE_Rv)
1165 TYPE("i32mem", TYPE_Mv)
1166 TYPE("i32imm", TYPE_IMMv)
1167 TYPE("i32i8imm", TYPE_IMM32)
1168 TYPE("u32u8imm", TYPE_IMM32)
1169 TYPE("GR32", TYPE_Rv)
1170 TYPE("i64mem", TYPE_Mv)
1171 TYPE("i64i32imm", TYPE_IMM64)
1172 TYPE("i64i8imm", TYPE_IMM64)
1173 TYPE("GR64", TYPE_R64)
1174 TYPE("i8mem", TYPE_M8)
1175 TYPE("i8imm", TYPE_IMM8)
1176 TYPE("GR8", TYPE_R8)
1177 TYPE("VR128", TYPE_XMM128)
1178 TYPE("VR128X", TYPE_XMM128)
1179 TYPE("f128mem", TYPE_M128)
1180 TYPE("f256mem", TYPE_M256)
1181 TYPE("f512mem", TYPE_M512)
1182 TYPE("FR64", TYPE_XMM64)
1183 TYPE("FR64X", TYPE_XMM64)
1184 TYPE("f64mem", TYPE_M64FP)
1185 TYPE("sdmem", TYPE_M64FP)
1186 TYPE("FR32", TYPE_XMM32)
1187 TYPE("FR32X", TYPE_XMM32)
1188 TYPE("f32mem", TYPE_M32FP)
1189 TYPE("ssmem", TYPE_M32FP)
1190 TYPE("RST", TYPE_ST)
1191 TYPE("i128mem", TYPE_M128)
1192 TYPE("i256mem", TYPE_M256)
1193 TYPE("i512mem", TYPE_M512)
1194 TYPE("i64i32imm_pcrel", TYPE_REL64)
1195 TYPE("i16imm_pcrel", TYPE_REL16)
1196 TYPE("i32imm_pcrel", TYPE_REL32)
1197 TYPE("SSECC", TYPE_IMM3)
1198 TYPE("AVXCC", TYPE_IMM5)
1199 TYPE("brtarget", TYPE_RELv)
1200 TYPE("uncondbrtarget", TYPE_RELv)
1201 TYPE("brtarget8", TYPE_REL8)
1202 TYPE("f80mem", TYPE_M80FP)
1203 TYPE("lea32mem", TYPE_LEA)
1204 TYPE("lea64_32mem", TYPE_LEA)
1205 TYPE("lea64mem", TYPE_LEA)
1206 TYPE("VR64", TYPE_MM64)
1207 TYPE("i64imm", TYPE_IMMv)
1208 TYPE("opaque32mem", TYPE_M1616)
1209 TYPE("opaque48mem", TYPE_M1632)
1210 TYPE("opaque80mem", TYPE_M1664)
1211 TYPE("opaque512mem", TYPE_M512)
1212 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1213 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1214 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1215 TYPE("offset8", TYPE_MOFFS8)
1216 TYPE("offset16", TYPE_MOFFS16)
1217 TYPE("offset32", TYPE_MOFFS32)
1218 TYPE("offset64", TYPE_MOFFS64)
1219 TYPE("VR256", TYPE_XMM256)
1220 TYPE("VR256X", TYPE_XMM256)
1221 TYPE("VR512", TYPE_XMM512)
1222 TYPE("VK8", TYPE_VK8)
1223 TYPE("VK8WM", TYPE_VK8)
1224 TYPE("VK16", TYPE_VK16)
1225 TYPE("VK16WM", TYPE_VK16)
1226 TYPE("GR16_NOAX", TYPE_Rv)
1227 TYPE("GR32_NOAX", TYPE_Rv)
1228 TYPE("GR64_NOAX", TYPE_R64)
1229 TYPE("vx32mem", TYPE_M32)
1230 TYPE("vy32mem", TYPE_M32)
1231 TYPE("vz32mem", TYPE_M32)
1232 TYPE("vx64mem", TYPE_M64)
1233 TYPE("vy64mem", TYPE_M64)
1234 TYPE("vy64xmem", TYPE_M64)
1235 TYPE("vz64mem", TYPE_M64)
1236 errs() << "Unhandled type string " << s << "\n";
1237 llvm_unreachable("Unhandled type string");
1241 #define ENCODING(str, encoding) if (s == str) return encoding;
1242 OperandEncoding RecognizableInstr::immediateEncodingFromString
1243 (const std::string &s,
1244 bool hasOpSizePrefix) {
1245 if(!hasOpSizePrefix) {
1246 // For instructions without an OpSize prefix, a declared 16-bit register or
1247 // immediate encoding is special.
1248 ENCODING("i16imm", ENCODING_IW)
1250 ENCODING("i32i8imm", ENCODING_IB)
1251 ENCODING("u32u8imm", ENCODING_IB)
1252 ENCODING("SSECC", ENCODING_IB)
1253 ENCODING("AVXCC", ENCODING_IB)
1254 ENCODING("i16imm", ENCODING_Iv)
1255 ENCODING("i16i8imm", ENCODING_IB)
1256 ENCODING("i32imm", ENCODING_Iv)
1257 ENCODING("i64i32imm", ENCODING_ID)
1258 ENCODING("i64i8imm", ENCODING_IB)
1259 ENCODING("i8imm", ENCODING_IB)
1260 // This is not a typo. Instructions like BLENDVPD put
1261 // register IDs in 8-bit immediates nowadays.
1262 ENCODING("FR32", ENCODING_IB)
1263 ENCODING("FR64", ENCODING_IB)
1264 ENCODING("VR128", ENCODING_IB)
1265 ENCODING("VR256", ENCODING_IB)
1266 ENCODING("FR32X", ENCODING_IB)
1267 ENCODING("FR64X", ENCODING_IB)
1268 ENCODING("VR128X", ENCODING_IB)
1269 ENCODING("VR256X", ENCODING_IB)
1270 ENCODING("VR512", ENCODING_IB)
1271 errs() << "Unhandled immediate encoding " << s << "\n";
1272 llvm_unreachable("Unhandled immediate encoding");
1275 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1276 (const std::string &s,
1277 bool hasOpSizePrefix) {
1278 ENCODING("GR16", ENCODING_RM)
1279 ENCODING("GR32", ENCODING_RM)
1280 ENCODING("GR64", ENCODING_RM)
1281 ENCODING("GR8", ENCODING_RM)
1282 ENCODING("VR128", ENCODING_RM)
1283 ENCODING("VR128X", ENCODING_RM)
1284 ENCODING("FR64", ENCODING_RM)
1285 ENCODING("FR32", ENCODING_RM)
1286 ENCODING("FR64X", ENCODING_RM)
1287 ENCODING("FR32X", ENCODING_RM)
1288 ENCODING("VR64", ENCODING_RM)
1289 ENCODING("VR256", ENCODING_RM)
1290 ENCODING("VR256X", ENCODING_RM)
1291 ENCODING("VR512", ENCODING_RM)
1292 ENCODING("VK8", ENCODING_RM)
1293 ENCODING("VK16", ENCODING_RM)
1294 errs() << "Unhandled R/M register encoding " << s << "\n";
1295 llvm_unreachable("Unhandled R/M register encoding");
1298 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1299 (const std::string &s,
1300 bool hasOpSizePrefix) {
1301 ENCODING("GR16", ENCODING_REG)
1302 ENCODING("GR32", ENCODING_REG)
1303 ENCODING("GR64", ENCODING_REG)
1304 ENCODING("GR8", ENCODING_REG)
1305 ENCODING("VR128", ENCODING_REG)
1306 ENCODING("FR64", ENCODING_REG)
1307 ENCODING("FR32", ENCODING_REG)
1308 ENCODING("VR64", ENCODING_REG)
1309 ENCODING("SEGMENT_REG", ENCODING_REG)
1310 ENCODING("DEBUG_REG", ENCODING_REG)
1311 ENCODING("CONTROL_REG", ENCODING_REG)
1312 ENCODING("VR256", ENCODING_REG)
1313 ENCODING("VR256X", ENCODING_REG)
1314 ENCODING("VR128X", ENCODING_REG)
1315 ENCODING("FR64X", ENCODING_REG)
1316 ENCODING("FR32X", ENCODING_REG)
1317 ENCODING("VR512", ENCODING_REG)
1318 ENCODING("VK8", ENCODING_REG)
1319 ENCODING("VK16", ENCODING_REG)
1320 ENCODING("VK8WM", ENCODING_REG)
1321 ENCODING("VK16WM", ENCODING_REG)
1322 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1323 llvm_unreachable("Unhandled reg/opcode register encoding");
1326 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1327 (const std::string &s,
1328 bool hasOpSizePrefix) {
1329 ENCODING("GR32", ENCODING_VVVV)
1330 ENCODING("GR64", ENCODING_VVVV)
1331 ENCODING("FR32", ENCODING_VVVV)
1332 ENCODING("FR64", ENCODING_VVVV)
1333 ENCODING("VR128", ENCODING_VVVV)
1334 ENCODING("VR256", ENCODING_VVVV)
1335 ENCODING("FR32X", ENCODING_VVVV)
1336 ENCODING("FR64X", ENCODING_VVVV)
1337 ENCODING("VR128X", ENCODING_VVVV)
1338 ENCODING("VR256X", ENCODING_VVVV)
1339 ENCODING("VR512", ENCODING_VVVV)
1340 ENCODING("VK8", ENCODING_VVVV)
1341 ENCODING("VK16", ENCODING_VVVV)
1342 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1343 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1346 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1347 (const std::string &s,
1348 bool hasOpSizePrefix) {
1349 ENCODING("VK8WM", ENCODING_WRITEMASK)
1350 ENCODING("VK16WM", ENCODING_WRITEMASK)
1351 errs() << "Unhandled mask register encoding " << s << "\n";
1352 llvm_unreachable("Unhandled mask register encoding");
1355 OperandEncoding RecognizableInstr::memoryEncodingFromString
1356 (const std::string &s,
1357 bool hasOpSizePrefix) {
1358 ENCODING("i16mem", ENCODING_RM)
1359 ENCODING("i32mem", ENCODING_RM)
1360 ENCODING("i64mem", ENCODING_RM)
1361 ENCODING("i8mem", ENCODING_RM)
1362 ENCODING("ssmem", ENCODING_RM)
1363 ENCODING("sdmem", ENCODING_RM)
1364 ENCODING("f128mem", ENCODING_RM)
1365 ENCODING("f256mem", ENCODING_RM)
1366 ENCODING("f512mem", ENCODING_RM)
1367 ENCODING("f64mem", ENCODING_RM)
1368 ENCODING("f32mem", ENCODING_RM)
1369 ENCODING("i128mem", ENCODING_RM)
1370 ENCODING("i256mem", ENCODING_RM)
1371 ENCODING("i512mem", ENCODING_RM)
1372 ENCODING("f80mem", ENCODING_RM)
1373 ENCODING("lea32mem", ENCODING_RM)
1374 ENCODING("lea64_32mem", ENCODING_RM)
1375 ENCODING("lea64mem", ENCODING_RM)
1376 ENCODING("opaque32mem", ENCODING_RM)
1377 ENCODING("opaque48mem", ENCODING_RM)
1378 ENCODING("opaque80mem", ENCODING_RM)
1379 ENCODING("opaque512mem", ENCODING_RM)
1380 ENCODING("vx32mem", ENCODING_RM)
1381 ENCODING("vy32mem", ENCODING_RM)
1382 ENCODING("vz32mem", ENCODING_RM)
1383 ENCODING("vx64mem", ENCODING_RM)
1384 ENCODING("vy64mem", ENCODING_RM)
1385 ENCODING("vy64xmem", ENCODING_RM)
1386 ENCODING("vz64mem", ENCODING_RM)
1387 errs() << "Unhandled memory encoding " << s << "\n";
1388 llvm_unreachable("Unhandled memory encoding");
1391 OperandEncoding RecognizableInstr::relocationEncodingFromString
1392 (const std::string &s,
1393 bool hasOpSizePrefix) {
1394 if(!hasOpSizePrefix) {
1395 // For instructions without an OpSize prefix, a declared 16-bit register or
1396 // immediate encoding is special.
1397 ENCODING("i16imm", ENCODING_IW)
1399 ENCODING("i16imm", ENCODING_Iv)
1400 ENCODING("i16i8imm", ENCODING_IB)
1401 ENCODING("i32imm", ENCODING_Iv)
1402 ENCODING("i32i8imm", ENCODING_IB)
1403 ENCODING("i64i32imm", ENCODING_ID)
1404 ENCODING("i64i8imm", ENCODING_IB)
1405 ENCODING("i8imm", ENCODING_IB)
1406 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1407 ENCODING("i16imm_pcrel", ENCODING_IW)
1408 ENCODING("i32imm_pcrel", ENCODING_ID)
1409 ENCODING("brtarget", ENCODING_Iv)
1410 ENCODING("brtarget8", ENCODING_IB)
1411 ENCODING("i64imm", ENCODING_IO)
1412 ENCODING("offset8", ENCODING_Ia)
1413 ENCODING("offset16", ENCODING_Ia)
1414 ENCODING("offset32", ENCODING_Ia)
1415 ENCODING("offset64", ENCODING_Ia)
1416 errs() << "Unhandled relocation encoding " << s << "\n";
1417 llvm_unreachable("Unhandled relocation encoding");
1420 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1421 (const std::string &s,
1422 bool hasOpSizePrefix) {
1423 ENCODING("RST", ENCODING_I)
1424 ENCODING("GR32", ENCODING_Rv)
1425 ENCODING("GR64", ENCODING_RO)
1426 ENCODING("GR16", ENCODING_Rv)
1427 ENCODING("GR8", ENCODING_RB)
1428 ENCODING("GR16_NOAX", ENCODING_Rv)
1429 ENCODING("GR32_NOAX", ENCODING_Rv)
1430 ENCODING("GR64_NOAX", ENCODING_RO)
1431 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1432 llvm_unreachable("Unhandled opcode modifier encoding");