1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
50 // A clone of X86 since we can't depend on something that is generated.
60 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
61 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
62 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
63 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
65 #define MAP(from, to) MRM_##from = to,
76 D8 = 3, D9 = 4, DA = 5, DB = 6,
77 DC = 7, DD = 8, DE = 9, DF = 10,
80 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
84 // If rows are added to the opcode extension tables, then corresponding entries
85 // must be added here.
87 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
88 // that byte to ONE_BYTE_EXTENSION_TABLES.
90 // If the row corresponds to two bytes where the first is 0f, add an entry for
91 // the second byte to TWO_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to some other set of bytes, you will need to modify
94 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
95 // to the X86 TD files, except in two cases: if the first two bytes of such a
96 // new combination are 0f 38 or 0f 3a, you just have to add maps called
97 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
98 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
99 // in RecognizableInstr::emitDecodePath().
101 #define ONE_BYTE_EXTENSION_TABLES \
102 EXTENSION_TABLE(80) \
103 EXTENSION_TABLE(81) \
104 EXTENSION_TABLE(82) \
105 EXTENSION_TABLE(83) \
106 EXTENSION_TABLE(8f) \
107 EXTENSION_TABLE(c0) \
108 EXTENSION_TABLE(c1) \
109 EXTENSION_TABLE(c6) \
110 EXTENSION_TABLE(c7) \
111 EXTENSION_TABLE(d0) \
112 EXTENSION_TABLE(d1) \
113 EXTENSION_TABLE(d2) \
114 EXTENSION_TABLE(d3) \
115 EXTENSION_TABLE(f6) \
116 EXTENSION_TABLE(f7) \
117 EXTENSION_TABLE(fe) \
120 #define TWO_BYTE_EXTENSION_TABLES \
121 EXTENSION_TABLE(00) \
122 EXTENSION_TABLE(01) \
123 EXTENSION_TABLE(18) \
124 EXTENSION_TABLE(71) \
125 EXTENSION_TABLE(72) \
126 EXTENSION_TABLE(73) \
127 EXTENSION_TABLE(ae) \
128 EXTENSION_TABLE(ba) \
131 #define THREE_BYTE_38_EXTENSION_TABLES \
134 using namespace X86Disassembler;
136 /// needsModRMForDecode - Indicates whether a particular instruction requires a
137 /// ModR/M byte for the instruction to be properly decoded. For example, a
138 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
141 /// @param form - The form of the instruction.
142 /// @return - true if the form implies that a ModR/M byte is required, false
144 static bool needsModRMForDecode(uint8_t form) {
145 if (form == X86Local::MRMDestReg ||
146 form == X86Local::MRMDestMem ||
147 form == X86Local::MRMSrcReg ||
148 form == X86Local::MRMSrcMem ||
149 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
150 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
156 /// isRegFormat - Indicates whether a particular form requires the Mod field of
157 /// the ModR/M byte to be 0b11.
159 /// @param form - The form of the instruction.
160 /// @return - true if the form implies that Mod must be 0b11, false
162 static bool isRegFormat(uint8_t form) {
163 if (form == X86Local::MRMDestReg ||
164 form == X86Local::MRMSrcReg ||
165 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
171 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
172 /// Useful for switch statements and the like.
174 /// @param init - A reference to the BitsInit to be decoded.
175 /// @return - The field, with the first bit in the BitsInit as the lowest
177 static uint8_t byteFromBitsInit(BitsInit &init) {
178 int width = init.getNumBits();
180 assert(width <= 8 && "Field is too large for uint8_t!");
187 for (index = 0; index < width; index++) {
188 if (static_cast<BitInit*>(init.getBit(index))->getValue())
197 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
198 /// name of the field.
200 /// @param rec - The record from which to extract the value.
201 /// @param name - The name of the field in the record.
202 /// @return - The field, as translated by byteFromBitsInit().
203 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
204 BitsInit* bits = rec->getValueAsBitsInit(name);
205 return byteFromBitsInit(*bits);
208 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
209 const CodeGenInstruction &insn,
214 Name = Rec->getName();
215 Spec = &tables.specForUID(UID);
217 if (!Rec->isSubClassOf("X86Inst")) {
218 ShouldBeEmitted = false;
222 Prefix = byteFromRec(Rec, "Prefix");
223 Opcode = byteFromRec(Rec, "Opcode");
224 Form = byteFromRec(Rec, "FormBits");
225 SegOvr = byteFromRec(Rec, "SegOvrBits");
227 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
228 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
229 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
230 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
231 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
232 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
233 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
234 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
235 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
236 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
237 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
239 Name = Rec->getName();
240 AsmString = Rec->getValueAsString("AsmString");
242 Operands = &insn.Operands.OperandList;
244 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
245 (Name.find("CRC32") != Name.npos);
246 HasFROperands = hasFROperands();
247 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
249 // Check for 64-bit inst which does not require REX
252 // FIXME: Is there some better way to check for In64BitMode?
253 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
254 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
255 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
259 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
264 // FIXME: These instructions aren't marked as 64-bit in any way
265 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
266 Rec->getName() == "MASKMOVDQU64" ||
267 Rec->getName() == "POPFS64" ||
268 Rec->getName() == "POPGS64" ||
269 Rec->getName() == "PUSHFS64" ||
270 Rec->getName() == "PUSHGS64" ||
271 Rec->getName() == "REX64_PREFIX" ||
272 Rec->getName().find("MOV64") != Name.npos ||
273 Rec->getName().find("PUSH64") != Name.npos ||
274 Rec->getName().find("POP64") != Name.npos;
276 ShouldBeEmitted = true;
279 void RecognizableInstr::processInstr(DisassemblerTables &tables,
280 const CodeGenInstruction &insn,
283 // Ignore "asm parser only" instructions.
284 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
287 RecognizableInstr recogInstr(tables, insn, uid);
289 recogInstr.emitInstructionSpecifier(tables);
291 if (recogInstr.shouldBeEmitted())
292 recogInstr.emitDecodePath(tables);
295 InstructionContext RecognizableInstr::insnContext() const {
296 InstructionContext insnContext;
298 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
299 if (HasVEX_LPrefix && HasVEX_WPrefix) {
301 insnContext = IC_VEX_L_W_OPSIZE;
303 llvm_unreachable("Don't support VEX.L and VEX.W together");
304 } else if (HasOpSizePrefix && HasVEX_LPrefix)
305 insnContext = IC_VEX_L_OPSIZE;
306 else if (HasOpSizePrefix && HasVEX_WPrefix)
307 insnContext = IC_VEX_W_OPSIZE;
308 else if (HasOpSizePrefix)
309 insnContext = IC_VEX_OPSIZE;
310 else if (HasVEX_LPrefix &&
311 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
312 insnContext = IC_VEX_L_XS;
313 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
314 Prefix == X86Local::T8XD ||
315 Prefix == X86Local::TAXD))
316 insnContext = IC_VEX_L_XD;
317 else if (HasVEX_WPrefix &&
318 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
319 insnContext = IC_VEX_W_XS;
320 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
321 Prefix == X86Local::T8XD ||
322 Prefix == X86Local::TAXD))
323 insnContext = IC_VEX_W_XD;
324 else if (HasVEX_WPrefix)
325 insnContext = IC_VEX_W;
326 else if (HasVEX_LPrefix)
327 insnContext = IC_VEX_L;
328 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329 Prefix == X86Local::TAXD)
330 insnContext = IC_VEX_XD;
331 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
332 insnContext = IC_VEX_XS;
334 insnContext = IC_VEX;
335 } else if (Is64Bit || HasREX_WPrefix) {
336 if (HasREX_WPrefix && HasOpSizePrefix)
337 insnContext = IC_64BIT_REXW_OPSIZE;
338 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
339 Prefix == X86Local::T8XD ||
340 Prefix == X86Local::TAXD))
341 insnContext = IC_64BIT_XD_OPSIZE;
342 else if (HasOpSizePrefix &&
343 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
344 insnContext = IC_64BIT_XS_OPSIZE;
345 else if (HasOpSizePrefix)
346 insnContext = IC_64BIT_OPSIZE;
347 else if (HasAdSizePrefix)
348 insnContext = IC_64BIT_ADSIZE;
349 else if (HasREX_WPrefix &&
350 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
351 insnContext = IC_64BIT_REXW_XS;
352 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
353 Prefix == X86Local::T8XD ||
354 Prefix == X86Local::TAXD))
355 insnContext = IC_64BIT_REXW_XD;
356 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357 Prefix == X86Local::TAXD)
358 insnContext = IC_64BIT_XD;
359 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360 insnContext = IC_64BIT_XS;
361 else if (HasREX_WPrefix)
362 insnContext = IC_64BIT_REXW;
364 insnContext = IC_64BIT;
366 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
367 Prefix == X86Local::T8XD ||
368 Prefix == X86Local::TAXD))
369 insnContext = IC_XD_OPSIZE;
370 else if (HasOpSizePrefix &&
371 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
372 insnContext = IC_XS_OPSIZE;
373 else if (HasOpSizePrefix)
374 insnContext = IC_OPSIZE;
375 else if (HasAdSizePrefix)
376 insnContext = IC_ADSIZE;
377 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
378 Prefix == X86Local::TAXD)
380 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
381 Prefix == X86Local::REP)
390 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
395 // Filter out intrinsics
397 if (!Rec->isSubClassOf("X86Inst"))
398 return FILTER_STRONG;
400 if (Form == X86Local::Pseudo ||
401 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
402 return FILTER_STRONG;
404 if (Form == X86Local::MRMInitReg)
405 return FILTER_STRONG;
408 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
409 // printed as a separate "instruction".
411 if (Name.find("_Int") != Name.npos ||
412 Name.find("Int_") != Name.npos ||
413 Name.find("_NOREX") != Name.npos ||
414 Name.find("2SDL") != Name.npos)
415 return FILTER_STRONG;
417 // Filter out instructions with segment override prefixes.
418 // They're too messy to handle now and we'll special case them if needed.
421 return FILTER_STRONG;
423 // Filter out instructions that can't be printed.
425 if (AsmString.size() == 0)
426 return FILTER_STRONG;
428 // Filter out instructions with subreg operands.
430 if (AsmString.find("subreg") != AsmString.npos)
431 return FILTER_STRONG;
438 // Filter out instructions with a LOCK prefix;
439 // prefer forms that do not have the prefix
443 // Filter out alternate forms of AVX instructions
444 if (Name.find("_alt") != Name.npos ||
445 Name.find("XrYr") != Name.npos ||
446 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
447 Name.find("_64mr") != Name.npos ||
448 Name.find("Xrr") != Name.npos ||
449 Name.find("rr64") != Name.npos)
454 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
456 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
459 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
461 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
463 if (Name.find("Fs") != Name.npos)
465 if (Name == "PUSH64i16" ||
466 Name == "MOVPQI2QImr" ||
467 Name == "VMOVPQI2QImr" ||
468 Name == "MMX_MOVD64rrv164" ||
469 Name == "MOV64ri64i32" ||
470 Name == "VMASKMOVDQU64" ||
471 Name == "VEXTRACTPSrr64" ||
472 Name == "VMOVQd64rr" ||
473 Name == "VMOVQs64rr")
476 if (HasFROperands && Name.find("MOV") != Name.npos &&
477 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
478 (Name.find("to") != Name.npos)))
481 return FILTER_NORMAL;
484 bool RecognizableInstr::hasFROperands() const {
485 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
486 unsigned numOperands = OperandList.size();
488 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
489 const std::string &recName = OperandList[operandIndex].Rec->getName();
491 if (recName.find("FR") != recName.npos)
497 bool RecognizableInstr::has256BitOperands() const {
498 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
499 unsigned numOperands = OperandList.size();
501 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
502 const std::string &recName = OperandList[operandIndex].Rec->getName();
504 if (!recName.compare("VR256") || !recName.compare("f256mem")) {
511 void RecognizableInstr::handleOperand(
513 unsigned &operandIndex,
514 unsigned &physicalOperandIndex,
515 unsigned &numPhysicalOperands,
516 unsigned *operandMapping,
517 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
519 if (physicalOperandIndex >= numPhysicalOperands)
522 assert(physicalOperandIndex < numPhysicalOperands);
525 while (operandMapping[operandIndex] != operandIndex) {
526 Spec->operands[operandIndex].encoding = ENCODING_DUP;
527 Spec->operands[operandIndex].type =
528 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
532 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
534 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
536 Spec->operands[operandIndex].type = typeFromString(typeName,
542 ++physicalOperandIndex;
545 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
548 if (!Rec->isSubClassOf("X86Inst"))
553 Spec->filtered = true;
556 ShouldBeEmitted = false;
562 Spec->insnContext = insnContext();
564 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
566 unsigned operandIndex;
567 unsigned numOperands = OperandList.size();
568 unsigned numPhysicalOperands = 0;
570 // operandMapping maps from operands in OperandList to their originals.
571 // If operandMapping[i] != i, then the entry is a duplicate.
572 unsigned operandMapping[X86_MAX_OPERANDS];
574 bool hasFROperands = false;
576 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
578 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
579 if (OperandList[operandIndex].Constraints.size()) {
580 const CGIOperandList::ConstraintInfo &Constraint =
581 OperandList[operandIndex].Constraints[0];
582 if (Constraint.isTied()) {
583 operandMapping[operandIndex] = Constraint.getTiedOperand();
585 ++numPhysicalOperands;
586 operandMapping[operandIndex] = operandIndex;
589 ++numPhysicalOperands;
590 operandMapping[operandIndex] = operandIndex;
593 const std::string &recName = OperandList[operandIndex].Rec->getName();
595 if (recName.find("FR") != recName.npos)
596 hasFROperands = true;
599 if (hasFROperands && Name.find("MOV") != Name.npos &&
600 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
601 (Name.find("to") != Name.npos)))
602 ShouldBeEmitted = false;
604 if (!ShouldBeEmitted)
607 #define HANDLE_OPERAND(class) \
608 handleOperand(false, \
610 physicalOperandIndex, \
611 numPhysicalOperands, \
613 class##EncodingFromString);
615 #define HANDLE_OPTIONAL(class) \
616 handleOperand(true, \
618 physicalOperandIndex, \
619 numPhysicalOperands, \
621 class##EncodingFromString);
623 // operandIndex should always be < numOperands
625 // physicalOperandIndex should always be < numPhysicalOperands
626 unsigned physicalOperandIndex = 0;
629 case X86Local::RawFrm:
630 // Operand 1 (optional) is an address or immediate.
631 // Operand 2 (optional) is an immediate.
632 assert(numPhysicalOperands <= 2 &&
633 "Unexpected number of operands for RawFrm");
634 HANDLE_OPTIONAL(relocation)
635 HANDLE_OPTIONAL(immediate)
637 case X86Local::AddRegFrm:
638 // Operand 1 is added to the opcode.
639 // Operand 2 (optional) is an address.
640 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
641 "Unexpected number of operands for AddRegFrm");
642 HANDLE_OPERAND(opcodeModifier)
643 HANDLE_OPTIONAL(relocation)
645 case X86Local::MRMDestReg:
646 // Operand 1 is a register operand in the R/M field.
647 // Operand 2 is a register operand in the Reg/Opcode field.
648 // - In AVX, there is a register operand in the VEX.vvvv field here -
649 // Operand 3 (optional) is an immediate.
651 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
652 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
654 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
655 "Unexpected number of operands for MRMDestRegFrm");
657 HANDLE_OPERAND(rmRegister)
660 // FIXME: In AVX, the register below becomes the one encoded
661 // in ModRMVEX and the one above the one in the VEX.VVVV field
662 HANDLE_OPERAND(vvvvRegister)
664 HANDLE_OPERAND(roRegister)
665 HANDLE_OPTIONAL(immediate)
667 case X86Local::MRMDestMem:
668 // Operand 1 is a memory operand (possibly SIB-extended)
669 // Operand 2 is a register operand in the Reg/Opcode field.
670 // - In AVX, there is a register operand in the VEX.vvvv field here -
671 // Operand 3 (optional) is an immediate.
673 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
674 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
676 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
677 "Unexpected number of operands for MRMDestMemFrm");
678 HANDLE_OPERAND(memory)
681 // FIXME: In AVX, the register below becomes the one encoded
682 // in ModRMVEX and the one above the one in the VEX.VVVV field
683 HANDLE_OPERAND(vvvvRegister)
685 HANDLE_OPERAND(roRegister)
686 HANDLE_OPTIONAL(immediate)
688 case X86Local::MRMSrcReg:
689 // Operand 1 is a register operand in the Reg/Opcode field.
690 // Operand 2 is a register operand in the R/M field.
691 // - In AVX, there is a register operand in the VEX.vvvv field here -
692 // Operand 3 (optional) is an immediate.
694 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
695 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
696 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
698 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
699 "Unexpected number of operands for MRMSrcRegFrm");
701 HANDLE_OPERAND(roRegister)
704 // FIXME: In AVX, the register below becomes the one encoded
705 // in ModRMVEX and the one above the one in the VEX.VVVV field
706 HANDLE_OPERAND(vvvvRegister)
709 HANDLE_OPERAND(immediate)
711 HANDLE_OPERAND(rmRegister)
713 if (HasVEX_4VOp3Prefix)
714 HANDLE_OPERAND(vvvvRegister)
716 if (!HasMemOp4Prefix)
717 HANDLE_OPTIONAL(immediate)
718 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
720 case X86Local::MRMSrcMem:
721 // Operand 1 is a register operand in the Reg/Opcode field.
722 // Operand 2 is a memory operand (possibly SIB-extended)
723 // - In AVX, there is a register operand in the VEX.vvvv field here -
724 // Operand 3 (optional) is an immediate.
726 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
727 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
728 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
730 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
731 "Unexpected number of operands for MRMSrcMemFrm");
733 HANDLE_OPERAND(roRegister)
736 // FIXME: In AVX, the register below becomes the one encoded
737 // in ModRMVEX and the one above the one in the VEX.VVVV field
738 HANDLE_OPERAND(vvvvRegister)
741 HANDLE_OPERAND(immediate)
743 HANDLE_OPERAND(memory)
745 if (HasVEX_4VOp3Prefix)
746 HANDLE_OPERAND(vvvvRegister)
748 if (!HasMemOp4Prefix)
749 HANDLE_OPTIONAL(immediate)
750 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
752 case X86Local::MRM0r:
753 case X86Local::MRM1r:
754 case X86Local::MRM2r:
755 case X86Local::MRM3r:
756 case X86Local::MRM4r:
757 case X86Local::MRM5r:
758 case X86Local::MRM6r:
759 case X86Local::MRM7r:
760 // Operand 1 is a register operand in the R/M field.
761 // Operand 2 (optional) is an immediate or relocation.
763 assert(numPhysicalOperands <= 3 &&
764 "Unexpected number of operands for MRMnRFrm with VEX_4V");
766 assert(numPhysicalOperands <= 2 &&
767 "Unexpected number of operands for MRMnRFrm");
769 HANDLE_OPERAND(vvvvRegister)
770 HANDLE_OPTIONAL(rmRegister)
771 HANDLE_OPTIONAL(relocation)
773 case X86Local::MRM0m:
774 case X86Local::MRM1m:
775 case X86Local::MRM2m:
776 case X86Local::MRM3m:
777 case X86Local::MRM4m:
778 case X86Local::MRM5m:
779 case X86Local::MRM6m:
780 case X86Local::MRM7m:
781 // Operand 1 is a memory operand (possibly SIB-extended)
782 // Operand 2 (optional) is an immediate or relocation.
784 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
785 "Unexpected number of operands for MRMnMFrm");
787 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
788 "Unexpected number of operands for MRMnMFrm");
790 HANDLE_OPERAND(vvvvRegister)
791 HANDLE_OPERAND(memory)
792 HANDLE_OPTIONAL(relocation)
794 case X86Local::RawFrmImm8:
795 // operand 1 is a 16-bit immediate
796 // operand 2 is an 8-bit immediate
797 assert(numPhysicalOperands == 2 &&
798 "Unexpected number of operands for X86Local::RawFrmImm8");
799 HANDLE_OPERAND(immediate)
800 HANDLE_OPERAND(immediate)
802 case X86Local::RawFrmImm16:
803 // operand 1 is a 16-bit immediate
804 // operand 2 is a 16-bit immediate
805 HANDLE_OPERAND(immediate)
806 HANDLE_OPERAND(immediate)
808 case X86Local::MRMInitReg:
813 #undef HANDLE_OPERAND
814 #undef HANDLE_OPTIONAL
817 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
818 // Special cases where the LLVM tables are not complete
820 #define MAP(from, to) \
821 case X86Local::MRM_##from: \
822 filter = new ExactFilter(0x##from); \
825 OpcodeType opcodeType = (OpcodeType)-1;
827 ModRMFilter* filter = NULL;
828 uint8_t opcodeToSet = 0;
831 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
835 opcodeType = TWOBYTE;
839 if (needsModRMForDecode(Form))
840 filter = new ModFilter(isRegFormat(Form));
842 filter = new DumbFilter();
844 #define EXTENSION_TABLE(n) case 0x##n:
845 TWO_BYTE_EXTENSION_TABLES
846 #undef EXTENSION_TABLE
849 llvm_unreachable("Unhandled two-byte extended opcode");
850 case X86Local::MRM0r:
851 case X86Local::MRM1r:
852 case X86Local::MRM2r:
853 case X86Local::MRM3r:
854 case X86Local::MRM4r:
855 case X86Local::MRM5r:
856 case X86Local::MRM6r:
857 case X86Local::MRM7r:
858 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
860 case X86Local::MRM0m:
861 case X86Local::MRM1m:
862 case X86Local::MRM2m:
863 case X86Local::MRM3m:
864 case X86Local::MRM4m:
865 case X86Local::MRM5m:
866 case X86Local::MRM6m:
867 case X86Local::MRM7m:
868 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
874 opcodeToSet = Opcode;
879 opcodeType = THREEBYTE_38;
882 if (needsModRMForDecode(Form))
883 filter = new ModFilter(isRegFormat(Form));
885 filter = new DumbFilter();
887 #define EXTENSION_TABLE(n) case 0x##n:
888 THREE_BYTE_38_EXTENSION_TABLES
889 #undef EXTENSION_TABLE
892 llvm_unreachable("Unhandled two-byte extended opcode");
893 case X86Local::MRM0r:
894 case X86Local::MRM1r:
895 case X86Local::MRM2r:
896 case X86Local::MRM3r:
897 case X86Local::MRM4r:
898 case X86Local::MRM5r:
899 case X86Local::MRM6r:
900 case X86Local::MRM7r:
901 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
903 case X86Local::MRM0m:
904 case X86Local::MRM1m:
905 case X86Local::MRM2m:
906 case X86Local::MRM3m:
907 case X86Local::MRM4m:
908 case X86Local::MRM5m:
909 case X86Local::MRM6m:
910 case X86Local::MRM7m:
911 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
917 opcodeToSet = Opcode;
921 opcodeType = THREEBYTE_3A;
922 if (needsModRMForDecode(Form))
923 filter = new ModFilter(isRegFormat(Form));
925 filter = new DumbFilter();
926 opcodeToSet = Opcode;
929 opcodeType = THREEBYTE_A6;
930 if (needsModRMForDecode(Form))
931 filter = new ModFilter(isRegFormat(Form));
933 filter = new DumbFilter();
934 opcodeToSet = Opcode;
937 opcodeType = THREEBYTE_A7;
938 if (needsModRMForDecode(Form))
939 filter = new ModFilter(isRegFormat(Form));
941 filter = new DumbFilter();
942 opcodeToSet = Opcode;
952 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
953 opcodeType = ONEBYTE;
954 if (Form == X86Local::AddRegFrm) {
955 Spec->modifierType = MODIFIER_MODRM;
956 Spec->modifierBase = Opcode;
957 filter = new AddRegEscapeFilter(Opcode);
959 filter = new EscapeFilter(true, Opcode);
961 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
965 opcodeType = ONEBYTE;
967 #define EXTENSION_TABLE(n) case 0x##n:
968 ONE_BYTE_EXTENSION_TABLES
969 #undef EXTENSION_TABLE
972 llvm_unreachable("Fell through the cracks of a single-byte "
974 case X86Local::MRM0r:
975 case X86Local::MRM1r:
976 case X86Local::MRM2r:
977 case X86Local::MRM3r:
978 case X86Local::MRM4r:
979 case X86Local::MRM5r:
980 case X86Local::MRM6r:
981 case X86Local::MRM7r:
982 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
984 case X86Local::MRM0m:
985 case X86Local::MRM1m:
986 case X86Local::MRM2m:
987 case X86Local::MRM3m:
988 case X86Local::MRM4m:
989 case X86Local::MRM5m:
990 case X86Local::MRM6m:
991 case X86Local::MRM7m:
992 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1005 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1008 if (needsModRMForDecode(Form))
1009 filter = new ModFilter(isRegFormat(Form));
1011 filter = new DumbFilter();
1013 } // switch (Opcode)
1014 opcodeToSet = Opcode;
1015 } // switch (Prefix)
1017 assert(opcodeType != (OpcodeType)-1 &&
1018 "Opcode type not set");
1019 assert(filter && "Filter not set");
1021 if (Form == X86Local::AddRegFrm) {
1022 if(Spec->modifierType != MODIFIER_MODRM) {
1023 assert(opcodeToSet < 0xf9 &&
1024 "Not enough room for all ADDREG_FRM operands");
1026 uint8_t currentOpcode;
1028 for (currentOpcode = opcodeToSet;
1029 currentOpcode < opcodeToSet + 8;
1031 tables.setTableFields(opcodeType,
1035 UID, Is32Bit, IgnoresVEX_L);
1037 Spec->modifierType = MODIFIER_OPCODE;
1038 Spec->modifierBase = opcodeToSet;
1040 // modifierBase was set where MODIFIER_MODRM was set
1041 tables.setTableFields(opcodeType,
1045 UID, Is32Bit, IgnoresVEX_L);
1048 tables.setTableFields(opcodeType,
1052 UID, Is32Bit, IgnoresVEX_L);
1054 Spec->modifierType = MODIFIER_NONE;
1055 Spec->modifierBase = opcodeToSet;
1063 #define TYPE(str, type) if (s == str) return type;
1064 OperandType RecognizableInstr::typeFromString(const std::string &s,
1066 bool hasREX_WPrefix,
1067 bool hasOpSizePrefix) {
1069 // For SSE instructions, we ignore the OpSize prefix and force operand
1071 TYPE("GR16", TYPE_R16)
1072 TYPE("GR32", TYPE_R32)
1073 TYPE("GR64", TYPE_R64)
1075 if(hasREX_WPrefix) {
1076 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1078 TYPE("GR32", TYPE_R32)
1080 if(!hasOpSizePrefix) {
1081 // For instructions without an OpSize prefix, a declared 16-bit register or
1082 // immediate encoding is special.
1083 TYPE("GR16", TYPE_R16)
1084 TYPE("i16imm", TYPE_IMM16)
1086 TYPE("i16mem", TYPE_Mv)
1087 TYPE("i16imm", TYPE_IMMv)
1088 TYPE("i16i8imm", TYPE_IMMv)
1089 TYPE("GR16", TYPE_Rv)
1090 TYPE("i32mem", TYPE_Mv)
1091 TYPE("i32imm", TYPE_IMMv)
1092 TYPE("i32i8imm", TYPE_IMM32)
1093 TYPE("u32u8imm", TYPE_IMM32)
1094 TYPE("GR32", TYPE_Rv)
1095 TYPE("i64mem", TYPE_Mv)
1096 TYPE("i64i32imm", TYPE_IMM64)
1097 TYPE("i64i8imm", TYPE_IMM64)
1098 TYPE("GR64", TYPE_R64)
1099 TYPE("i8mem", TYPE_M8)
1100 TYPE("i8imm", TYPE_IMM8)
1101 TYPE("GR8", TYPE_R8)
1102 TYPE("VR128", TYPE_XMM128)
1103 TYPE("f128mem", TYPE_M128)
1104 TYPE("f256mem", TYPE_M256)
1105 TYPE("FR64", TYPE_XMM64)
1106 TYPE("f64mem", TYPE_M64FP)
1107 TYPE("sdmem", TYPE_M64FP)
1108 TYPE("FR32", TYPE_XMM32)
1109 TYPE("f32mem", TYPE_M32FP)
1110 TYPE("ssmem", TYPE_M32FP)
1111 TYPE("RST", TYPE_ST)
1112 TYPE("i128mem", TYPE_M128)
1113 TYPE("i256mem", TYPE_M256)
1114 TYPE("i64i32imm_pcrel", TYPE_REL64)
1115 TYPE("i16imm_pcrel", TYPE_REL16)
1116 TYPE("i32imm_pcrel", TYPE_REL32)
1117 TYPE("SSECC", TYPE_IMM3)
1118 TYPE("brtarget", TYPE_RELv)
1119 TYPE("uncondbrtarget", TYPE_RELv)
1120 TYPE("brtarget8", TYPE_REL8)
1121 TYPE("f80mem", TYPE_M80FP)
1122 TYPE("lea32mem", TYPE_LEA)
1123 TYPE("lea64_32mem", TYPE_LEA)
1124 TYPE("lea64mem", TYPE_LEA)
1125 TYPE("VR64", TYPE_MM64)
1126 TYPE("i64imm", TYPE_IMMv)
1127 TYPE("opaque32mem", TYPE_M1616)
1128 TYPE("opaque48mem", TYPE_M1632)
1129 TYPE("opaque80mem", TYPE_M1664)
1130 TYPE("opaque512mem", TYPE_M512)
1131 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1132 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1133 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1134 TYPE("offset8", TYPE_MOFFS8)
1135 TYPE("offset16", TYPE_MOFFS16)
1136 TYPE("offset32", TYPE_MOFFS32)
1137 TYPE("offset64", TYPE_MOFFS64)
1138 TYPE("VR256", TYPE_XMM256)
1139 TYPE("GR16_NOAX", TYPE_Rv)
1140 TYPE("GR32_NOAX", TYPE_Rv)
1141 TYPE("GR64_NOAX", TYPE_R64)
1142 errs() << "Unhandled type string " << s << "\n";
1143 llvm_unreachable("Unhandled type string");
1147 #define ENCODING(str, encoding) if (s == str) return encoding;
1148 OperandEncoding RecognizableInstr::immediateEncodingFromString
1149 (const std::string &s,
1150 bool hasOpSizePrefix) {
1151 if(!hasOpSizePrefix) {
1152 // For instructions without an OpSize prefix, a declared 16-bit register or
1153 // immediate encoding is special.
1154 ENCODING("i16imm", ENCODING_IW)
1156 ENCODING("i32i8imm", ENCODING_IB)
1157 ENCODING("u32u8imm", ENCODING_IB)
1158 ENCODING("SSECC", ENCODING_IB)
1159 ENCODING("i16imm", ENCODING_Iv)
1160 ENCODING("i16i8imm", ENCODING_IB)
1161 ENCODING("i32imm", ENCODING_Iv)
1162 ENCODING("i64i32imm", ENCODING_ID)
1163 ENCODING("i64i8imm", ENCODING_IB)
1164 ENCODING("i8imm", ENCODING_IB)
1165 // This is not a typo. Instructions like BLENDVPD put
1166 // register IDs in 8-bit immediates nowadays.
1167 ENCODING("VR256", ENCODING_IB)
1168 ENCODING("VR128", ENCODING_IB)
1169 errs() << "Unhandled immediate encoding " << s << "\n";
1170 llvm_unreachable("Unhandled immediate encoding");
1173 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1174 (const std::string &s,
1175 bool hasOpSizePrefix) {
1176 ENCODING("GR16", ENCODING_RM)
1177 ENCODING("GR32", ENCODING_RM)
1178 ENCODING("GR64", ENCODING_RM)
1179 ENCODING("GR8", ENCODING_RM)
1180 ENCODING("VR128", ENCODING_RM)
1181 ENCODING("FR64", ENCODING_RM)
1182 ENCODING("FR32", ENCODING_RM)
1183 ENCODING("VR64", ENCODING_RM)
1184 ENCODING("VR256", ENCODING_RM)
1185 errs() << "Unhandled R/M register encoding " << s << "\n";
1186 llvm_unreachable("Unhandled R/M register encoding");
1189 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1190 (const std::string &s,
1191 bool hasOpSizePrefix) {
1192 ENCODING("GR16", ENCODING_REG)
1193 ENCODING("GR32", ENCODING_REG)
1194 ENCODING("GR64", ENCODING_REG)
1195 ENCODING("GR8", ENCODING_REG)
1196 ENCODING("VR128", ENCODING_REG)
1197 ENCODING("FR64", ENCODING_REG)
1198 ENCODING("FR32", ENCODING_REG)
1199 ENCODING("VR64", ENCODING_REG)
1200 ENCODING("SEGMENT_REG", ENCODING_REG)
1201 ENCODING("DEBUG_REG", ENCODING_REG)
1202 ENCODING("CONTROL_REG", ENCODING_REG)
1203 ENCODING("VR256", ENCODING_REG)
1204 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1205 llvm_unreachable("Unhandled reg/opcode register encoding");
1208 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1209 (const std::string &s,
1210 bool hasOpSizePrefix) {
1211 ENCODING("GR32", ENCODING_VVVV)
1212 ENCODING("GR64", ENCODING_VVVV)
1213 ENCODING("FR32", ENCODING_VVVV)
1214 ENCODING("FR64", ENCODING_VVVV)
1215 ENCODING("VR128", ENCODING_VVVV)
1216 ENCODING("VR256", ENCODING_VVVV)
1217 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1218 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1221 OperandEncoding RecognizableInstr::memoryEncodingFromString
1222 (const std::string &s,
1223 bool hasOpSizePrefix) {
1224 ENCODING("i16mem", ENCODING_RM)
1225 ENCODING("i32mem", ENCODING_RM)
1226 ENCODING("i64mem", ENCODING_RM)
1227 ENCODING("i8mem", ENCODING_RM)
1228 ENCODING("ssmem", ENCODING_RM)
1229 ENCODING("sdmem", ENCODING_RM)
1230 ENCODING("f128mem", ENCODING_RM)
1231 ENCODING("f256mem", ENCODING_RM)
1232 ENCODING("f64mem", ENCODING_RM)
1233 ENCODING("f32mem", ENCODING_RM)
1234 ENCODING("i128mem", ENCODING_RM)
1235 ENCODING("i256mem", ENCODING_RM)
1236 ENCODING("f80mem", ENCODING_RM)
1237 ENCODING("lea32mem", ENCODING_RM)
1238 ENCODING("lea64_32mem", ENCODING_RM)
1239 ENCODING("lea64mem", ENCODING_RM)
1240 ENCODING("opaque32mem", ENCODING_RM)
1241 ENCODING("opaque48mem", ENCODING_RM)
1242 ENCODING("opaque80mem", ENCODING_RM)
1243 ENCODING("opaque512mem", ENCODING_RM)
1244 errs() << "Unhandled memory encoding " << s << "\n";
1245 llvm_unreachable("Unhandled memory encoding");
1248 OperandEncoding RecognizableInstr::relocationEncodingFromString
1249 (const std::string &s,
1250 bool hasOpSizePrefix) {
1251 if(!hasOpSizePrefix) {
1252 // For instructions without an OpSize prefix, a declared 16-bit register or
1253 // immediate encoding is special.
1254 ENCODING("i16imm", ENCODING_IW)
1256 ENCODING("i16imm", ENCODING_Iv)
1257 ENCODING("i16i8imm", ENCODING_IB)
1258 ENCODING("i32imm", ENCODING_Iv)
1259 ENCODING("i32i8imm", ENCODING_IB)
1260 ENCODING("i64i32imm", ENCODING_ID)
1261 ENCODING("i64i8imm", ENCODING_IB)
1262 ENCODING("i8imm", ENCODING_IB)
1263 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1264 ENCODING("i16imm_pcrel", ENCODING_IW)
1265 ENCODING("i32imm_pcrel", ENCODING_ID)
1266 ENCODING("brtarget", ENCODING_Iv)
1267 ENCODING("brtarget8", ENCODING_IB)
1268 ENCODING("i64imm", ENCODING_IO)
1269 ENCODING("offset8", ENCODING_Ia)
1270 ENCODING("offset16", ENCODING_Ia)
1271 ENCODING("offset32", ENCODING_Ia)
1272 ENCODING("offset64", ENCODING_Ia)
1273 errs() << "Unhandled relocation encoding " << s << "\n";
1274 llvm_unreachable("Unhandled relocation encoding");
1277 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1278 (const std::string &s,
1279 bool hasOpSizePrefix) {
1280 ENCODING("RST", ENCODING_I)
1281 ENCODING("GR32", ENCODING_Rv)
1282 ENCODING("GR64", ENCODING_RO)
1283 ENCODING("GR16", ENCODING_Rv)
1284 ENCODING("GR8", ENCODING_RB)
1285 ENCODING("GR16_NOAX", ENCODING_Rv)
1286 ENCODING("GR32_NOAX", ENCODING_Rv)
1287 ENCODING("GR64_NOAX", ENCODING_RO)
1288 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1289 llvm_unreachable("Unhandled opcode modifier encoding");