1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the interface of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #ifndef X86RECOGNIZABLEINSTR_H
18 #define X86RECOGNIZABLEINSTR_H
20 #include "X86DisassemblerTables.h"
22 #include "CodeGenTarget.h"
24 #include "llvm/TableGen/Record.h"
25 #include "llvm/Support/DataTypes.h"
26 #include "llvm/ADT/SmallVector.h"
30 namespace X86Disassembler {
32 /// RecognizableInstr - Encapsulates all information required to decode a single
33 /// instruction, as extracted from the LLVM instruction tables. Has methods
34 /// to interpret the information available in the LLVM tables, and to emit the
35 /// instruction into DisassemblerTables.
36 class RecognizableInstr {
38 /// The opcode of the instruction, as used in an MCInst
40 /// The record from the .td files corresponding to this instruction
42 /// The prefix field from the record
44 /// The opcode field from the record; this is the opcode used in the Intel
45 /// encoding and therefore distinct from the UID
47 /// The form field from the record
49 /// The segment override field from the record
51 /// The hasOpSizePrefix field from the record
53 /// The hasREX_WPrefix field from the record
55 /// The hasVEXPrefix field from the record
57 /// The hasVEX_4VPrefix field from the record
59 /// The hasVEX_4VOp3Prefix field from the record
60 bool HasVEX_4VOp3Prefix;
61 /// The hasVEX_WPrefix field from the record
63 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
65 /// The hasMemOp4Prefix field from the record
67 /// The ignoreVEX_L field from the record
69 /// The hasLockPrefix field from the record
71 /// The isCodeGenOnly filed from the record
73 // Whether the instruction has the predicate "In64BitMode"
75 // Whether the instruction has the predicate "In32BitMode"
78 /// The instruction name as listed in the tables
80 /// The AT&T AsmString for the instruction
81 std::string AsmString;
83 /// Indicates whether the instruction is SSE
85 /// Indicates whether the instruction has FR operands - MOVs with FR operands
86 /// are typically ignored
88 /// Indicates whether the instruction should be emitted into the decode
89 /// tables; regardless, it will be emitted into the instruction info table
92 /// The operands of the instruction, as listed in the CodeGenInstruction.
93 /// They are not one-to-one with operands listed in the MCInst; for example,
94 /// memory operands expand to 5 operands in the MCInst
95 const std::vector<CGIOperandList::OperandInfo>* Operands;
97 /// The description of the instruction that is emitted into the instruction
99 InstructionSpecifier* Spec;
101 /// insnContext - Returns the primary context in which the instruction is
104 /// @return - The context in which the instruction is valid.
105 InstructionContext insnContext() const;
108 FILTER_STRONG, // instruction has no place in the instruction tables
109 FILTER_WEAK, // instruction may conflict, and should be eliminated if
111 FILTER_NORMAL // instruction should have high priority and generate an
112 // error if it conflcits with any other FILTER_NORMAL
116 /// filter - Determines whether the instruction should be decodable. Some
117 /// instructions are pure intrinsics and use unencodable operands; many
118 /// synthetic instructions are duplicates of other instructions; other
119 /// instructions only differ in the logical way in which they are used, and
120 /// have the same decoding. Because these would cause decode conflicts,
121 /// they must be filtered out.
123 /// @return - The degree of filtering to be applied (see filter_ret).
124 filter_ret filter() const;
126 /// hasFROperands - Returns true if any operand is a FR operand.
127 bool hasFROperands() const;
129 /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand.
130 bool has256BitOperands() const;
132 /// typeFromString - Translates an operand type from the string provided in
133 /// the LLVM tables to an OperandType for use in the operand specifier.
135 /// @param s - The string, as extracted by calling Rec->getName()
136 /// on a CodeGenInstruction::OperandInfo.
137 /// @param isSSE - Indicates whether the instruction is an SSE
138 /// instruction. For SSE instructions, immediates are
139 /// fixed-size rather than being affected by the
140 /// mandatory OpSize prefix.
141 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
142 /// prefix. If it does, 32-bit register operands stay
143 /// 32-bit regardless of the operand size.
144 /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize
145 /// prefix. If it does not, then 16-bit register
146 /// operands stay 16-bit.
147 /// @return - The operand's type.
148 static OperandType typeFromString(const std::string& s,
151 bool hasOpSizePrefix);
153 /// immediateEncodingFromString - Translates an immediate encoding from the
154 /// string provided in the LLVM tables to an OperandEncoding for use in
155 /// the operand specifier.
157 /// @param s - See typeFromString().
158 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
159 /// prefix. If it does not, then 16-bit immediate
160 /// operands stay 16-bit.
161 /// @return - The operand's encoding.
162 static OperandEncoding immediateEncodingFromString(const std::string &s,
163 bool hasOpSizePrefix);
165 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
166 /// handles operands that are in the REG field of the ModR/M byte.
167 static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
168 bool hasOpSizePrefix);
170 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
171 /// handles operands that are in the REG field of the ModR/M byte.
172 static OperandEncoding roRegisterEncodingFromString(const std::string &s,
173 bool hasOpSizePrefix);
174 static OperandEncoding memoryEncodingFromString(const std::string &s,
175 bool hasOpSizePrefix);
176 static OperandEncoding relocationEncodingFromString(const std::string &s,
177 bool hasOpSizePrefix);
178 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
179 bool hasOpSizePrefix);
180 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
181 bool HasOpSizePrefix);
183 /// handleOperand - Converts a single operand from the LLVM table format to
184 /// the emitted table format, handling any duplicate operands it encounters
185 /// and then one non-duplicate.
187 /// @param optional - Determines whether to assert that the
189 /// @param operandIndex - The index into the generated operand table.
190 /// Incremented by this function one or more
191 /// times to reflect possible duplicate
193 /// @param physicalOperandIndex - The index of the current operand into the
194 /// set of non-duplicate ('physical') operands.
195 /// Incremented by this function once.
196 /// @param numPhysicalOperands - The number of non-duplicate operands in the
198 /// @param operandMapping - The operand mapping, which has an entry for
199 /// each operand that indicates whether it is a
200 /// duplicate, and of what.
201 void handleOperand(bool optional,
202 unsigned &operandIndex,
203 unsigned &physicalOperandIndex,
204 unsigned &numPhysicalOperands,
205 unsigned *operandMapping,
206 OperandEncoding (*encodingFromString)
208 bool hasOpSizePrefix));
210 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
211 /// filters out many instructions, at various points in decoding we
212 /// determine that the instruction should not actually be decodable. In
213 /// particular, MMX MOV instructions aren't emitted, but they're only
214 /// identified during operand parsing.
216 /// @return - true if at this point we believe the instruction should be
217 /// emitted; false if not. This will return false if filter() returns false
218 /// once emitInstructionSpecifier() has been called.
219 bool shouldBeEmitted() const {
220 return ShouldBeEmitted;
223 /// emitInstructionSpecifier - Loads the instruction specifier for the current
224 /// instruction into a DisassemblerTables.
226 /// @arg tables - The DisassemblerTables to populate with the specifier for
227 /// the current instruction.
228 void emitInstructionSpecifier(DisassemblerTables &tables);
230 /// emitDecodePath - Populates the proper fields in the decode tables
231 /// corresponding to the decode paths for this instruction.
233 /// @arg tables - The DisassemblerTables to populate with the decode
234 /// decode information for the current instruction.
235 void emitDecodePath(DisassemblerTables &tables) const;
237 /// Constructor - Initializes a RecognizableInstr with the appropriate fields
238 /// from a CodeGenInstruction.
240 /// @arg tables - The DisassemblerTables that the specifier will be added to.
241 /// @arg insn - The CodeGenInstruction to extract information from.
242 /// @arg uid - The unique ID of the current instruction.
243 RecognizableInstr(DisassemblerTables &tables,
244 const CodeGenInstruction &insn,
247 /// processInstr - Accepts a CodeGenInstruction and loads decode information
248 /// for it into a DisassemblerTables if appropriate.
250 /// @arg tables - The DiassemblerTables to be populated with decode
252 /// @arg insn - The CodeGenInstruction to be used as a source for this
254 /// @uid - The unique ID of the instruction.
255 static void processInstr(DisassemblerTables &tables,
256 const CodeGenInstruction &insn,
260 } // namespace X86Disassembler