1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the interface of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #ifndef X86RECOGNIZABLEINSTR_H
18 #define X86RECOGNIZABLEINSTR_H
20 #include "CodeGenTarget.h"
21 #include "X86DisassemblerTables.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/Support/DataTypes.h"
24 #include "llvm/TableGen/Record.h"
28 namespace X86Disassembler {
30 /// RecognizableInstr - Encapsulates all information required to decode a single
31 /// instruction, as extracted from the LLVM instruction tables. Has methods
32 /// to interpret the information available in the LLVM tables, and to emit the
33 /// instruction into DisassemblerTables.
34 class RecognizableInstr {
36 /// The opcode of the instruction, as used in an MCInst
38 /// The record from the .td files corresponding to this instruction
40 /// The prefix field from the record
42 /// The opcode field from the record; this is the opcode used in the Intel
43 /// encoding and therefore distinct from the UID
45 /// The form field from the record
47 /// The segment override field from the record
49 /// The hasOpSizePrefix field from the record
51 /// The hasAdSizePrefix field from the record
53 /// The hasREX_WPrefix field from the record
55 /// The hasVEXPrefix field from the record
57 /// The hasVEX_4VPrefix field from the record
59 /// The hasVEX_4VOp3Prefix field from the record
60 bool HasVEX_4VOp3Prefix;
61 /// The hasVEX_WPrefix field from the record
63 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
65 /// The hasMemOp4Prefix field from the record
67 /// The ignoreVEX_L field from the record
69 /// The hasEVEXPrefix field from the record
71 /// The hasEVEX_L2Prefix field from the record
72 bool HasEVEX_L2Prefix;
73 /// The hasEVEX_K field from the record
75 /// The hasEVEX_KZ field from the record
77 /// The hasEVEX_B field from the record
79 /// The hasLockPrefix field from the record
81 /// The isCodeGenOnly filed from the record
83 // Whether the instruction has the predicate "In64BitMode"
85 // Whether the instruction has the predicate "In32BitMode"
88 /// The instruction name as listed in the tables
90 /// The AT&T AsmString for the instruction
91 std::string AsmString;
93 /// Indicates whether the instruction is SSE
95 /// Indicates whether the instruction has FR operands - MOVs with FR operands
96 /// are typically ignored
98 /// Indicates whether the instruction should be emitted into the decode
99 /// tables; regardless, it will be emitted into the instruction info table
100 bool ShouldBeEmitted;
102 /// The operands of the instruction, as listed in the CodeGenInstruction.
103 /// They are not one-to-one with operands listed in the MCInst; for example,
104 /// memory operands expand to 5 operands in the MCInst
105 const std::vector<CGIOperandList::OperandInfo>* Operands;
107 /// The description of the instruction that is emitted into the instruction
109 InstructionSpecifier* Spec;
111 /// insnContext - Returns the primary context in which the instruction is
114 /// @return - The context in which the instruction is valid.
115 InstructionContext insnContext() const;
118 FILTER_STRONG, // instruction has no place in the instruction tables
119 FILTER_WEAK, // instruction may conflict, and should be eliminated if
121 FILTER_NORMAL // instruction should have high priority and generate an
122 // error if it conflcits with any other FILTER_NORMAL
126 /// filter - Determines whether the instruction should be decodable. Some
127 /// instructions are pure intrinsics and use unencodable operands; many
128 /// synthetic instructions are duplicates of other instructions; other
129 /// instructions only differ in the logical way in which they are used, and
130 /// have the same decoding. Because these would cause decode conflicts,
131 /// they must be filtered out.
133 /// @return - The degree of filtering to be applied (see filter_ret).
134 filter_ret filter() const;
136 /// hasFROperands - Returns true if any operand is a FR operand.
137 bool hasFROperands() const;
139 /// typeFromString - Translates an operand type from the string provided in
140 /// the LLVM tables to an OperandType for use in the operand specifier.
142 /// @param s - The string, as extracted by calling Rec->getName()
143 /// on a CodeGenInstruction::OperandInfo.
144 /// @param isSSE - Indicates whether the instruction is an SSE
145 /// instruction. For SSE instructions, immediates are
146 /// fixed-size rather than being affected by the
147 /// mandatory OpSize prefix.
148 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
149 /// prefix. If it does, 32-bit register operands stay
150 /// 32-bit regardless of the operand size.
151 /// @param hasOpSizePrefix Indicates whether the instruction has an OpSize
152 /// prefix. If it does not, then 16-bit register
153 /// operands stay 16-bit.
154 /// @return - The operand's type.
155 static OperandType typeFromString(const std::string& s,
158 bool hasOpSizePrefix);
160 /// immediateEncodingFromString - Translates an immediate encoding from the
161 /// string provided in the LLVM tables to an OperandEncoding for use in
162 /// the operand specifier.
164 /// @param s - See typeFromString().
165 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
166 /// prefix. If it does not, then 16-bit immediate
167 /// operands stay 16-bit.
168 /// @return - The operand's encoding.
169 static OperandEncoding immediateEncodingFromString(const std::string &s,
170 bool hasOpSizePrefix);
172 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
173 /// handles operands that are in the REG field of the ModR/M byte.
174 static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
175 bool hasOpSizePrefix);
177 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
178 /// handles operands that are in the REG field of the ModR/M byte.
179 static OperandEncoding roRegisterEncodingFromString(const std::string &s,
180 bool hasOpSizePrefix);
181 static OperandEncoding memoryEncodingFromString(const std::string &s,
182 bool hasOpSizePrefix);
183 static OperandEncoding relocationEncodingFromString(const std::string &s,
184 bool hasOpSizePrefix);
185 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
186 bool hasOpSizePrefix);
187 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
188 bool HasOpSizePrefix);
189 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
190 bool HasOpSizePrefix);
192 /// handleOperand - Converts a single operand from the LLVM table format to
193 /// the emitted table format, handling any duplicate operands it encounters
194 /// and then one non-duplicate.
196 /// @param optional - Determines whether to assert that the
198 /// @param operandIndex - The index into the generated operand table.
199 /// Incremented by this function one or more
200 /// times to reflect possible duplicate
202 /// @param physicalOperandIndex - The index of the current operand into the
203 /// set of non-duplicate ('physical') operands.
204 /// Incremented by this function once.
205 /// @param numPhysicalOperands - The number of non-duplicate operands in the
207 /// @param operandMapping - The operand mapping, which has an entry for
208 /// each operand that indicates whether it is a
209 /// duplicate, and of what.
210 void handleOperand(bool optional,
211 unsigned &operandIndex,
212 unsigned &physicalOperandIndex,
213 unsigned &numPhysicalOperands,
214 const unsigned *operandMapping,
215 OperandEncoding (*encodingFromString)
217 bool hasOpSizePrefix));
219 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
220 /// filters out many instructions, at various points in decoding we
221 /// determine that the instruction should not actually be decodable. In
222 /// particular, MMX MOV instructions aren't emitted, but they're only
223 /// identified during operand parsing.
225 /// @return - true if at this point we believe the instruction should be
226 /// emitted; false if not. This will return false if filter() returns false
227 /// once emitInstructionSpecifier() has been called.
228 bool shouldBeEmitted() const {
229 return ShouldBeEmitted;
232 /// emitInstructionSpecifier - Loads the instruction specifier for the current
233 /// instruction into a DisassemblerTables.
235 /// \param tables The DisassemblerTables to populate with the specifier for
236 /// the current instruction.
237 void emitInstructionSpecifier(DisassemblerTables &tables);
239 /// emitDecodePath - Populates the proper fields in the decode tables
240 /// corresponding to the decode paths for this instruction.
242 /// \param tables The DisassemblerTables to populate with the decode
243 /// decode information for the current instruction.
244 void emitDecodePath(DisassemblerTables &tables) const;
246 /// Constructor - Initializes a RecognizableInstr with the appropriate fields
247 /// from a CodeGenInstruction.
249 /// \param tables The DisassemblerTables that the specifier will be added to.
250 /// \param insn The CodeGenInstruction to extract information from.
251 /// \param uid The unique ID of the current instruction.
252 RecognizableInstr(DisassemblerTables &tables,
253 const CodeGenInstruction &insn,
256 /// processInstr - Accepts a CodeGenInstruction and loads decode information
257 /// for it into a DisassemblerTables if appropriate.
259 /// \param tables The DiassemblerTables to be populated with decode
261 /// \param insn The CodeGenInstruction to be used as a source for this
263 /// \param uid The unique ID of the instruction.
264 static void processInstr(DisassemblerTables &tables,
265 const CodeGenInstruction &insn,
269 } // namespace X86Disassembler