1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the interface of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #ifndef X86RECOGNIZABLEINSTR_H
18 #define X86RECOGNIZABLEINSTR_H
20 #include "X86DisassemblerTables.h"
22 #include "CodeGenTarget.h"
24 #include "llvm/TableGen/Record.h"
25 #include "llvm/Support/DataTypes.h"
26 #include "llvm/ADT/SmallVector.h"
30 namespace X86Disassembler {
32 /// RecognizableInstr - Encapsulates all information required to decode a single
33 /// instruction, as extracted from the LLVM instruction tables. Has methods
34 /// to interpret the information available in the LLVM tables, and to emit the
35 /// instruction into DisassemblerTables.
36 class RecognizableInstr {
38 /// The opcode of the instruction, as used in an MCInst
40 /// The record from the .td files corresponding to this instruction
42 /// The prefix field from the record
44 /// The opcode field from the record; this is the opcode used in the Intel
45 /// encoding and therefore distinct from the UID
47 /// The form field from the record
49 /// The segment override field from the record
51 /// The hasOpSizePrefix field from the record
53 /// The hasAdSizePrefix field from the record
55 /// The hasREX_WPrefix field from the record
57 /// The hasVEXPrefix field from the record
59 /// The hasVEX_4VPrefix field from the record
61 /// The hasVEX_4VOp3Prefix field from the record
62 bool HasVEX_4VOp3Prefix;
63 /// The hasVEX_WPrefix field from the record
65 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
67 /// The hasMemOp4Prefix field from the record
69 /// The ignoreVEX_L field from the record
71 /// The hasLockPrefix field from the record
73 /// The isCodeGenOnly filed from the record
75 // Whether the instruction has the predicate "In64BitMode"
77 // Whether the instruction has the predicate "In32BitMode"
80 /// The instruction name as listed in the tables
82 /// The AT&T AsmString for the instruction
83 std::string AsmString;
85 /// Indicates whether the instruction is SSE
87 /// Indicates whether the instruction has FR operands - MOVs with FR operands
88 /// are typically ignored
90 /// Indicates whether the instruction should be emitted into the decode
91 /// tables; regardless, it will be emitted into the instruction info table
94 /// The operands of the instruction, as listed in the CodeGenInstruction.
95 /// They are not one-to-one with operands listed in the MCInst; for example,
96 /// memory operands expand to 5 operands in the MCInst
97 const std::vector<CGIOperandList::OperandInfo>* Operands;
99 /// The description of the instruction that is emitted into the instruction
101 InstructionSpecifier* Spec;
103 /// insnContext - Returns the primary context in which the instruction is
106 /// @return - The context in which the instruction is valid.
107 InstructionContext insnContext() const;
110 FILTER_STRONG, // instruction has no place in the instruction tables
111 FILTER_WEAK, // instruction may conflict, and should be eliminated if
113 FILTER_NORMAL // instruction should have high priority and generate an
114 // error if it conflcits with any other FILTER_NORMAL
118 /// filter - Determines whether the instruction should be decodable. Some
119 /// instructions are pure intrinsics and use unencodable operands; many
120 /// synthetic instructions are duplicates of other instructions; other
121 /// instructions only differ in the logical way in which they are used, and
122 /// have the same decoding. Because these would cause decode conflicts,
123 /// they must be filtered out.
125 /// @return - The degree of filtering to be applied (see filter_ret).
126 filter_ret filter() const;
128 /// hasFROperands - Returns true if any operand is a FR operand.
129 bool hasFROperands() const;
131 /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand.
132 bool has256BitOperands() const;
134 /// typeFromString - Translates an operand type from the string provided in
135 /// the LLVM tables to an OperandType for use in the operand specifier.
137 /// @param s - The string, as extracted by calling Rec->getName()
138 /// on a CodeGenInstruction::OperandInfo.
139 /// @param isSSE - Indicates whether the instruction is an SSE
140 /// instruction. For SSE instructions, immediates are
141 /// fixed-size rather than being affected by the
142 /// mandatory OpSize prefix.
143 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
144 /// prefix. If it does, 32-bit register operands stay
145 /// 32-bit regardless of the operand size.
146 /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize
147 /// prefix. If it does not, then 16-bit register
148 /// operands stay 16-bit.
149 /// @return - The operand's type.
150 static OperandType typeFromString(const std::string& s,
153 bool hasOpSizePrefix);
155 /// immediateEncodingFromString - Translates an immediate encoding from the
156 /// string provided in the LLVM tables to an OperandEncoding for use in
157 /// the operand specifier.
159 /// @param s - See typeFromString().
160 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
161 /// prefix. If it does not, then 16-bit immediate
162 /// operands stay 16-bit.
163 /// @return - The operand's encoding.
164 static OperandEncoding immediateEncodingFromString(const std::string &s,
165 bool hasOpSizePrefix);
167 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
168 /// handles operands that are in the REG field of the ModR/M byte.
169 static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
170 bool hasOpSizePrefix);
172 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
173 /// handles operands that are in the REG field of the ModR/M byte.
174 static OperandEncoding roRegisterEncodingFromString(const std::string &s,
175 bool hasOpSizePrefix);
176 static OperandEncoding memoryEncodingFromString(const std::string &s,
177 bool hasOpSizePrefix);
178 static OperandEncoding relocationEncodingFromString(const std::string &s,
179 bool hasOpSizePrefix);
180 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
181 bool hasOpSizePrefix);
182 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
183 bool HasOpSizePrefix);
185 /// handleOperand - Converts a single operand from the LLVM table format to
186 /// the emitted table format, handling any duplicate operands it encounters
187 /// and then one non-duplicate.
189 /// @param optional - Determines whether to assert that the
191 /// @param operandIndex - The index into the generated operand table.
192 /// Incremented by this function one or more
193 /// times to reflect possible duplicate
195 /// @param physicalOperandIndex - The index of the current operand into the
196 /// set of non-duplicate ('physical') operands.
197 /// Incremented by this function once.
198 /// @param numPhysicalOperands - The number of non-duplicate operands in the
200 /// @param operandMapping - The operand mapping, which has an entry for
201 /// each operand that indicates whether it is a
202 /// duplicate, and of what.
203 void handleOperand(bool optional,
204 unsigned &operandIndex,
205 unsigned &physicalOperandIndex,
206 unsigned &numPhysicalOperands,
207 unsigned *operandMapping,
208 OperandEncoding (*encodingFromString)
210 bool hasOpSizePrefix));
212 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
213 /// filters out many instructions, at various points in decoding we
214 /// determine that the instruction should not actually be decodable. In
215 /// particular, MMX MOV instructions aren't emitted, but they're only
216 /// identified during operand parsing.
218 /// @return - true if at this point we believe the instruction should be
219 /// emitted; false if not. This will return false if filter() returns false
220 /// once emitInstructionSpecifier() has been called.
221 bool shouldBeEmitted() const {
222 return ShouldBeEmitted;
225 /// emitInstructionSpecifier - Loads the instruction specifier for the current
226 /// instruction into a DisassemblerTables.
228 /// @arg tables - The DisassemblerTables to populate with the specifier for
229 /// the current instruction.
230 void emitInstructionSpecifier(DisassemblerTables &tables);
232 /// emitDecodePath - Populates the proper fields in the decode tables
233 /// corresponding to the decode paths for this instruction.
235 /// @arg tables - The DisassemblerTables to populate with the decode
236 /// decode information for the current instruction.
237 void emitDecodePath(DisassemblerTables &tables) const;
239 /// Constructor - Initializes a RecognizableInstr with the appropriate fields
240 /// from a CodeGenInstruction.
242 /// @arg tables - The DisassemblerTables that the specifier will be added to.
243 /// @arg insn - The CodeGenInstruction to extract information from.
244 /// @arg uid - The unique ID of the current instruction.
245 RecognizableInstr(DisassemblerTables &tables,
246 const CodeGenInstruction &insn,
249 /// processInstr - Accepts a CodeGenInstruction and loads decode information
250 /// for it into a DisassemblerTables if appropriate.
252 /// @arg tables - The DiassemblerTables to be populated with decode
254 /// @arg insn - The CodeGenInstruction to be used as a source for this
256 /// @uid - The unique ID of the instruction.
257 static void processInstr(DisassemblerTables &tables,
258 const CodeGenInstruction &insn,
262 } // namespace X86Disassembler