1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the interface of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #ifndef X86RECOGNIZABLEINSTR_H
18 #define X86RECOGNIZABLEINSTR_H
20 #include "X86DisassemblerTables.h"
22 #include "CodeGenTarget.h"
25 #include "llvm/System/DataTypes.h"
26 #include "llvm/ADT/SmallVector.h"
30 namespace X86Disassembler {
32 /// RecognizableInstr - Encapsulates all information required to decode a single
33 /// instruction, as extracted from the LLVM instruction tables. Has methods
34 /// to interpret the information available in the LLVM tables, and to emit the
35 /// instruction into DisassemblerTables.
36 class RecognizableInstr {
38 /// The opcode of the instruction, as used in an MCInst
40 /// The record from the .td files corresponding to this instruction
42 /// The prefix field from the record
44 /// The opcode field from the record; this is the opcode used in the Intel
45 /// encoding and therefore distinct from the UID
47 /// The form field from the record
49 /// The segment override field from the record
51 /// The hasOpSizePrefix field from the record
53 /// The hasREX_WPrefix field from the record
55 /// The hasLockPrefix field from the record
57 /// The isCodeGenOnly filed from the record
60 /// The instruction name as listed in the tables
62 /// The AT&T AsmString for the instruction
63 std::string AsmString;
65 /// Indicates whether the instruction is SSE
67 /// Indicates whether the instruction has FR operands - MOVs with FR operands
68 /// are typically ignored
70 /// Indicates whether the instruction should be emitted into the decode
71 /// tables; regardless, it will be emitted into the instruction info table
74 /// The operands of the instruction, as listed in the CodeGenInstruction.
75 /// They are not one-to-one with operands listed in the MCInst; for example,
76 /// memory operands expand to 5 operands in the MCInst
77 const std::vector<CodeGenInstruction::OperandInfo>* Operands;
78 /// The description of the instruction that is emitted into the instruction
80 InstructionSpecifier* Spec;
82 /// insnContext - Returns the primary context in which the instruction is
85 /// @return - The context in which the instruction is valid.
86 InstructionContext insnContext() const;
89 FILTER_STRONG, // instruction has no place in the instruction tables
90 FILTER_WEAK, // instruction may conflict, and should be eliminated if
92 FILTER_NORMAL // instruction should have high priority and generate an
93 // error if it conflcits with any other FILTER_NORMAL
97 /// filter - Determines whether the instruction should be decodable. Some
98 /// instructions are pure intrinsics and use unencodable operands; many
99 /// synthetic instructions are duplicates of other instructions; other
100 /// instructions only differ in the logical way in which they are used, and
101 /// have the same decoding. Because these would cause decode conflicts,
102 /// they must be filtered out.
104 /// @return - The degree of filtering to be applied (see filter_ret).
105 filter_ret filter() const;
107 /// typeFromString - Translates an operand type from the string provided in
108 /// the LLVM tables to an OperandType for use in the operand specifier.
110 /// @param s - The string, as extracted by calling Rec->getName()
111 /// on a CodeGenInstruction::OperandInfo.
112 /// @param isSSE - Indicates whether the instruction is an SSE
113 /// instruction. For SSE instructions, immediates are
114 /// fixed-size rather than being affected by the
115 /// mandatory OpSize prefix.
116 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
117 /// prefix. If it does, 32-bit register operands stay
118 /// 32-bit regardless of the operand size.
119 /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize
120 /// prefix. If it does not, then 16-bit register
121 /// operands stay 16-bit.
122 /// @return - The operand's type.
123 static OperandType typeFromString(const std::string& s,
126 bool hasOpSizePrefix);
128 /// immediateEncodingFromString - Translates an immediate encoding from the
129 /// string provided in the LLVM tables to an OperandEncoding for use in
130 /// the operand specifier.
132 /// @param s - See typeFromString().
133 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
134 /// prefix. If it does not, then 16-bit immediate
135 /// operands stay 16-bit.
136 /// @return - The operand's encoding.
137 static OperandEncoding immediateEncodingFromString(const std::string &s,
138 bool hasOpSizePrefix);
140 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
141 /// handles operands that are in the REG field of the ModR/M byte.
142 static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
143 bool hasOpSizePrefix);
145 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
146 /// handles operands that are in the REG field of the ModR/M byte.
147 static OperandEncoding roRegisterEncodingFromString(const std::string &s,
148 bool hasOpSizePrefix);
149 static OperandEncoding memoryEncodingFromString(const std::string &s,
150 bool hasOpSizePrefix);
151 static OperandEncoding relocationEncodingFromString(const std::string &s,
152 bool hasOpSizePrefix);
153 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
154 bool hasOpSizePrefix);
156 /// handleOperand - Converts a single operand from the LLVM table format to
157 /// the emitted table format, handling any duplicate operands it encounters
158 /// and then one non-duplicate.
160 /// @param optional - Determines whether to assert that the
162 /// @param operandIndex - The index into the generated operand table.
163 /// Incremented by this function one or more
164 /// times to reflect possible duplicate
166 /// @param physicalOperandIndex - The index of the current operand into the
167 /// set of non-duplicate ('physical') operands.
168 /// Incremented by this function once.
169 /// @param numPhysicalOperands - The number of non-duplicate operands in the
171 /// @param operandMapping - The operand mapping, which has an entry for
172 /// each operand that indicates whether it is a
173 /// duplicate, and of what.
174 void handleOperand(bool optional,
175 unsigned &operandIndex,
176 unsigned &physicalOperandIndex,
177 unsigned &numPhysicalOperands,
178 unsigned *operandMapping,
179 OperandEncoding (*encodingFromString)
181 bool hasOpSizePrefix));
183 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
184 /// filters out many instructions, at various points in decoding we
185 /// determine that the instruction should not actually be decodable. In
186 /// particular, MMX MOV instructions aren't emitted, but they're only
187 /// identified during operand parsing.
189 /// @return - true if at this point we believe the instruction should be
190 /// emitted; false if not. This will return false if filter() returns false
191 /// once emitInstructionSpecifier() has been called.
192 bool shouldBeEmitted() const {
193 return ShouldBeEmitted;
196 /// emitInstructionSpecifier - Loads the instruction specifier for the current
197 /// instruction into a DisassemblerTables.
199 /// @arg tables - The DisassemblerTables to populate with the specifier for
200 /// the current instruction.
201 void emitInstructionSpecifier(DisassemblerTables &tables);
203 /// emitDecodePath - Populates the proper fields in the decode tables
204 /// corresponding to the decode paths for this instruction.
206 /// @arg tables - The DisassemblerTables to populate with the decode
207 /// decode information for the current instruction.
208 void emitDecodePath(DisassemblerTables &tables) const;
210 /// Constructor - Initializes a RecognizableInstr with the appropriate fields
211 /// from a CodeGenInstruction.
213 /// @arg tables - The DisassemblerTables that the specifier will be added to.
214 /// @arg insn - The CodeGenInstruction to extract information from.
215 /// @arg uid - The unique ID of the current instruction.
216 RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
220 /// processInstr - Accepts a CodeGenInstruction and loads decode information
221 /// for it into a DisassemblerTables if appropriate.
223 /// @arg tables - The DiassemblerTables to be populated with decode
225 /// @arg insn - The CodeGenInstruction to be used as a source for this
227 /// @uid - The unique ID of the instruction.
228 static void processInstr(DisassemblerTables &tables,
229 const CodeGenInstruction &insn,
233 } // namespace X86Disassembler