1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the interface of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #ifndef X86RECOGNIZABLEINSTR_H
18 #define X86RECOGNIZABLEINSTR_H
20 #include "X86DisassemblerTables.h"
22 #include "CodeGenTarget.h"
25 #include "llvm/System/DataTypes.h"
26 #include "llvm/ADT/SmallVector.h"
30 namespace X86Disassembler {
32 /// RecognizableInstr - Encapsulates all information required to decode a single
33 /// instruction, as extracted from the LLVM instruction tables. Has methods
34 /// to interpret the information available in the LLVM tables, and to emit the
35 /// instruction into DisassemblerTables.
36 class RecognizableInstr {
38 /// The opcode of the instruction, as used in an MCInst
40 /// The record from the .td files corresponding to this instruction
42 /// The prefix field from the record
44 /// The opcode field from the record; this is the opcode used in the Intel
45 /// encoding and therefore distinct from the UID
47 /// The form field from the record
49 /// The segment override field from the record
51 /// The hasOpSizePrefix field from the record
53 /// The hasREX_WPrefix field from the record
55 /// The hasVEX_4VPrefix field from the record
57 /// The hasLockPrefix field from the record
59 /// The isCodeGenOnly filed from the record
62 /// The instruction name as listed in the tables
64 /// The AT&T AsmString for the instruction
65 std::string AsmString;
67 /// Indicates whether the instruction is SSE
69 /// Indicates whether the instruction has FR operands - MOVs with FR operands
70 /// are typically ignored
72 /// Indicates whether the instruction should be emitted into the decode
73 /// tables; regardless, it will be emitted into the instruction info table
76 /// The operands of the instruction, as listed in the CodeGenInstruction.
77 /// They are not one-to-one with operands listed in the MCInst; for example,
78 /// memory operands expand to 5 operands in the MCInst
79 const std::vector<CodeGenInstruction::OperandInfo>* Operands;
80 /// The description of the instruction that is emitted into the instruction
82 InstructionSpecifier* Spec;
84 /// insnContext - Returns the primary context in which the instruction is
87 /// @return - The context in which the instruction is valid.
88 InstructionContext insnContext() const;
91 FILTER_STRONG, // instruction has no place in the instruction tables
92 FILTER_WEAK, // instruction may conflict, and should be eliminated if
94 FILTER_NORMAL // instruction should have high priority and generate an
95 // error if it conflcits with any other FILTER_NORMAL
99 /// filter - Determines whether the instruction should be decodable. Some
100 /// instructions are pure intrinsics and use unencodable operands; many
101 /// synthetic instructions are duplicates of other instructions; other
102 /// instructions only differ in the logical way in which they are used, and
103 /// have the same decoding. Because these would cause decode conflicts,
104 /// they must be filtered out.
106 /// @return - The degree of filtering to be applied (see filter_ret).
107 filter_ret filter() const;
109 /// typeFromString - Translates an operand type from the string provided in
110 /// the LLVM tables to an OperandType for use in the operand specifier.
112 /// @param s - The string, as extracted by calling Rec->getName()
113 /// on a CodeGenInstruction::OperandInfo.
114 /// @param isSSE - Indicates whether the instruction is an SSE
115 /// instruction. For SSE instructions, immediates are
116 /// fixed-size rather than being affected by the
117 /// mandatory OpSize prefix.
118 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
119 /// prefix. If it does, 32-bit register operands stay
120 /// 32-bit regardless of the operand size.
121 /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize
122 /// prefix. If it does not, then 16-bit register
123 /// operands stay 16-bit.
124 /// @return - The operand's type.
125 static OperandType typeFromString(const std::string& s,
128 bool hasOpSizePrefix);
130 /// immediateEncodingFromString - Translates an immediate encoding from the
131 /// string provided in the LLVM tables to an OperandEncoding for use in
132 /// the operand specifier.
134 /// @param s - See typeFromString().
135 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
136 /// prefix. If it does not, then 16-bit immediate
137 /// operands stay 16-bit.
138 /// @return - The operand's encoding.
139 static OperandEncoding immediateEncodingFromString(const std::string &s,
140 bool hasOpSizePrefix);
142 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
143 /// handles operands that are in the REG field of the ModR/M byte.
144 static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
145 bool hasOpSizePrefix);
147 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
148 /// handles operands that are in the REG field of the ModR/M byte.
149 static OperandEncoding roRegisterEncodingFromString(const std::string &s,
150 bool hasOpSizePrefix);
151 static OperandEncoding memoryEncodingFromString(const std::string &s,
152 bool hasOpSizePrefix);
153 static OperandEncoding relocationEncodingFromString(const std::string &s,
154 bool hasOpSizePrefix);
155 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
156 bool hasOpSizePrefix);
158 /// handleOperand - Converts a single operand from the LLVM table format to
159 /// the emitted table format, handling any duplicate operands it encounters
160 /// and then one non-duplicate.
162 /// @param optional - Determines whether to assert that the
164 /// @param operandIndex - The index into the generated operand table.
165 /// Incremented by this function one or more
166 /// times to reflect possible duplicate
168 /// @param physicalOperandIndex - The index of the current operand into the
169 /// set of non-duplicate ('physical') operands.
170 /// Incremented by this function once.
171 /// @param numPhysicalOperands - The number of non-duplicate operands in the
173 /// @param operandMapping - The operand mapping, which has an entry for
174 /// each operand that indicates whether it is a
175 /// duplicate, and of what.
176 void handleOperand(bool optional,
177 unsigned &operandIndex,
178 unsigned &physicalOperandIndex,
179 unsigned &numPhysicalOperands,
180 unsigned *operandMapping,
181 OperandEncoding (*encodingFromString)
183 bool hasOpSizePrefix));
185 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
186 /// filters out many instructions, at various points in decoding we
187 /// determine that the instruction should not actually be decodable. In
188 /// particular, MMX MOV instructions aren't emitted, but they're only
189 /// identified during operand parsing.
191 /// @return - true if at this point we believe the instruction should be
192 /// emitted; false if not. This will return false if filter() returns false
193 /// once emitInstructionSpecifier() has been called.
194 bool shouldBeEmitted() const {
195 return ShouldBeEmitted;
198 /// emitInstructionSpecifier - Loads the instruction specifier for the current
199 /// instruction into a DisassemblerTables.
201 /// @arg tables - The DisassemblerTables to populate with the specifier for
202 /// the current instruction.
203 void emitInstructionSpecifier(DisassemblerTables &tables);
205 /// emitDecodePath - Populates the proper fields in the decode tables
206 /// corresponding to the decode paths for this instruction.
208 /// @arg tables - The DisassemblerTables to populate with the decode
209 /// decode information for the current instruction.
210 void emitDecodePath(DisassemblerTables &tables) const;
212 /// Constructor - Initializes a RecognizableInstr with the appropriate fields
213 /// from a CodeGenInstruction.
215 /// @arg tables - The DisassemblerTables that the specifier will be added to.
216 /// @arg insn - The CodeGenInstruction to extract information from.
217 /// @arg uid - The unique ID of the current instruction.
218 RecognizableInstr(DisassemblerTables &tables,
219 const CodeGenInstruction &insn,
222 /// processInstr - Accepts a CodeGenInstruction and loads decode information
223 /// for it into a DisassemblerTables if appropriate.
225 /// @arg tables - The DiassemblerTables to be populated with decode
227 /// @arg insn - The CodeGenInstruction to be used as a source for this
229 /// @uid - The unique ID of the instruction.
230 static void processInstr(DisassemblerTables &tables,
231 const CodeGenInstruction &insn,
235 } // namespace X86Disassembler