1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the interface of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #ifndef X86RECOGNIZABLEINSTR_H
18 #define X86RECOGNIZABLEINSTR_H
20 #include "CodeGenTarget.h"
21 #include "X86DisassemblerTables.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/Support/DataTypes.h"
24 #include "llvm/TableGen/Record.h"
28 namespace X86Disassembler {
30 /// RecognizableInstr - Encapsulates all information required to decode a single
31 /// instruction, as extracted from the LLVM instruction tables. Has methods
32 /// to interpret the information available in the LLVM tables, and to emit the
33 /// instruction into DisassemblerTables.
34 class RecognizableInstr {
36 /// The opcode of the instruction, as used in an MCInst
38 /// The record from the .td files corresponding to this instruction
40 /// The prefix field from the record
42 /// The opcode field from the record; this is the opcode used in the Intel
43 /// encoding and therefore distinct from the UID
45 /// The form field from the record
47 /// The hasOpSizePrefix field from the record
49 /// The hasAdSizePrefix field from the record
51 /// The hasREX_WPrefix field from the record
53 /// The hasVEXPrefix field from the record
55 /// The hasVEX_4VPrefix field from the record
57 /// The hasVEX_4VOp3Prefix field from the record
58 bool HasVEX_4VOp3Prefix;
59 /// The hasVEX_WPrefix field from the record
61 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
63 /// The hasMemOp4Prefix field from the record
65 /// The ignoreVEX_L field from the record
67 /// The hasEVEXPrefix field from the record
69 /// The hasEVEX_L2Prefix field from the record
70 bool HasEVEX_L2Prefix;
71 /// The hasEVEX_K field from the record
73 /// The hasEVEX_KZ field from the record
75 /// The hasEVEX_B field from the record
77 /// The hasLockPrefix field from the record
79 /// The isCodeGenOnly field from the record
81 /// The ForceDisassemble field from the record
82 bool ForceDisassemble;
83 // Whether the instruction has the predicate "In64BitMode"
85 // Whether the instruction has the predicate "In32BitMode"
88 /// The instruction name as listed in the tables
90 /// The AT&T AsmString for the instruction
91 std::string AsmString;
93 /// Indicates whether the instruction is SSE
95 /// Indicates whether the instruction should be emitted into the decode
96 /// tables; regardless, it will be emitted into the instruction info table
99 /// The operands of the instruction, as listed in the CodeGenInstruction.
100 /// They are not one-to-one with operands listed in the MCInst; for example,
101 /// memory operands expand to 5 operands in the MCInst
102 const std::vector<CGIOperandList::OperandInfo>* Operands;
104 /// The description of the instruction that is emitted into the instruction
106 InstructionSpecifier* Spec;
108 /// insnContext - Returns the primary context in which the instruction is
111 /// @return - The context in which the instruction is valid.
112 InstructionContext insnContext() const;
115 FILTER_STRONG, // instruction has no place in the instruction tables
116 FILTER_WEAK, // instruction may conflict, and should be eliminated if
118 FILTER_NORMAL // instruction should have high priority and generate an
119 // error if it conflcits with any other FILTER_NORMAL
123 /// filter - Determines whether the instruction should be decodable. Some
124 /// instructions are pure intrinsics and use unencodable operands; many
125 /// synthetic instructions are duplicates of other instructions; other
126 /// instructions only differ in the logical way in which they are used, and
127 /// have the same decoding. Because these would cause decode conflicts,
128 /// they must be filtered out.
130 /// @return - The degree of filtering to be applied (see filter_ret).
131 filter_ret filter() const;
133 /// hasFROperands - Returns true if any operand is a FR operand.
134 bool hasFROperands() const;
136 /// typeFromString - Translates an operand type from the string provided in
137 /// the LLVM tables to an OperandType for use in the operand specifier.
139 /// @param s - The string, as extracted by calling Rec->getName()
140 /// on a CodeGenInstruction::OperandInfo.
141 /// @param isSSE - Indicates whether the instruction is an SSE
142 /// instruction. For SSE instructions, immediates are
143 /// fixed-size rather than being affected by the
144 /// mandatory OpSize prefix.
145 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
146 /// prefix. If it does, 32-bit register operands stay
147 /// 32-bit regardless of the operand size.
148 /// @param hasOpSizePrefix Indicates whether the instruction has an OpSize
149 /// prefix. If it does not, then 16-bit register
150 /// operands stay 16-bit.
151 /// @return - The operand's type.
152 static OperandType typeFromString(const std::string& s,
155 bool hasOpSizePrefix);
157 /// immediateEncodingFromString - Translates an immediate encoding from the
158 /// string provided in the LLVM tables to an OperandEncoding for use in
159 /// the operand specifier.
161 /// @param s - See typeFromString().
162 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
163 /// prefix. If it does not, then 16-bit immediate
164 /// operands stay 16-bit.
165 /// @return - The operand's encoding.
166 static OperandEncoding immediateEncodingFromString(const std::string &s,
167 bool hasOpSizePrefix);
169 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
170 /// handles operands that are in the REG field of the ModR/M byte.
171 static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
172 bool hasOpSizePrefix);
174 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
175 /// handles operands that are in the REG field of the ModR/M byte.
176 static OperandEncoding roRegisterEncodingFromString(const std::string &s,
177 bool hasOpSizePrefix);
178 static OperandEncoding memoryEncodingFromString(const std::string &s,
179 bool hasOpSizePrefix);
180 static OperandEncoding relocationEncodingFromString(const std::string &s,
181 bool hasOpSizePrefix);
182 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
183 bool hasOpSizePrefix);
184 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
185 bool HasOpSizePrefix);
186 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
187 bool HasOpSizePrefix);
189 /// handleOperand - Converts a single operand from the LLVM table format to
190 /// the emitted table format, handling any duplicate operands it encounters
191 /// and then one non-duplicate.
193 /// @param optional - Determines whether to assert that the
195 /// @param operandIndex - The index into the generated operand table.
196 /// Incremented by this function one or more
197 /// times to reflect possible duplicate
199 /// @param physicalOperandIndex - The index of the current operand into the
200 /// set of non-duplicate ('physical') operands.
201 /// Incremented by this function once.
202 /// @param numPhysicalOperands - The number of non-duplicate operands in the
204 /// @param operandMapping - The operand mapping, which has an entry for
205 /// each operand that indicates whether it is a
206 /// duplicate, and of what.
207 void handleOperand(bool optional,
208 unsigned &operandIndex,
209 unsigned &physicalOperandIndex,
210 unsigned &numPhysicalOperands,
211 const unsigned *operandMapping,
212 OperandEncoding (*encodingFromString)
214 bool hasOpSizePrefix));
216 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
217 /// filters out many instructions, at various points in decoding we
218 /// determine that the instruction should not actually be decodable. In
219 /// particular, MMX MOV instructions aren't emitted, but they're only
220 /// identified during operand parsing.
222 /// @return - true if at this point we believe the instruction should be
223 /// emitted; false if not. This will return false if filter() returns false
224 /// once emitInstructionSpecifier() has been called.
225 bool shouldBeEmitted() const {
226 return ShouldBeEmitted;
229 /// emitInstructionSpecifier - Loads the instruction specifier for the current
230 /// instruction into a DisassemblerTables.
232 void emitInstructionSpecifier();
234 /// emitDecodePath - Populates the proper fields in the decode tables
235 /// corresponding to the decode paths for this instruction.
237 /// \param tables The DisassemblerTables to populate with the decode
238 /// decode information for the current instruction.
239 void emitDecodePath(DisassemblerTables &tables) const;
241 /// Constructor - Initializes a RecognizableInstr with the appropriate fields
242 /// from a CodeGenInstruction.
244 /// \param tables The DisassemblerTables that the specifier will be added to.
245 /// \param insn The CodeGenInstruction to extract information from.
246 /// \param uid The unique ID of the current instruction.
247 RecognizableInstr(DisassemblerTables &tables,
248 const CodeGenInstruction &insn,
251 /// processInstr - Accepts a CodeGenInstruction and loads decode information
252 /// for it into a DisassemblerTables if appropriate.
254 /// \param tables The DiassemblerTables to be populated with decode
256 /// \param insn The CodeGenInstruction to be used as a source for this
258 /// \param uid The unique ID of the instruction.
259 static void processInstr(DisassemblerTables &tables,
260 const CodeGenInstruction &insn,
264 } // namespace X86Disassembler