virt/kvm/arm/vgic-v3.c

   1 /*
   2  * Copyright (C) 2013 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/kvm.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/irqchip/arm-gic-v3.h>
  28
  29 #include <asm/kvm_emulate.h>
  30 #include <asm/kvm_arm.h>
  31 #include <asm/kvm_mmu.h>
  32
  33 /* These are for GICv2 emulation only */
  34 #define GICH_LR_VIRTUALID               (0x3ffUL << 0)
  35 #define GICH_LR_PHYSID_CPUID_SHIFT      (10)
  36 #define GICH_LR_PHYSID_CPUID            (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
  37 #define ICH_LR_VIRTUALID_MASK           (BIT_ULL(32) - 1)
  38
  39 static u32 ich_vtr_el2;
  40
  41 static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
  42 {
  43         struct vgic_lr lr_desc;
  44         u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[VGIC_V3_LR_INDEX(lr)];
  45
  46         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
  47                 lr_desc.irq = val & ICH_LR_VIRTUALID_MASK;
  48         else
  49                 lr_desc.irq = val & GICH_LR_VIRTUALID;
  50
  51         lr_desc.source = 0;
  52         if (lr_desc.irq <= 15 &&
  53             vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
  54                 lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
  55
  56         lr_desc.state = 0;
  57
  58         if (val & ICH_LR_PENDING_BIT)
  59                 lr_desc.state |= LR_STATE_PENDING;
  60         if (val & ICH_LR_ACTIVE_BIT)
  61                 lr_desc.state |= LR_STATE_ACTIVE;
  62         if (val & ICH_LR_EOI)
  63                 lr_desc.state |= LR_EOI_INT;
  64         if (val & ICH_LR_HW) {
  65                 lr_desc.state |= LR_HW;
  66                 lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
  67         }
  68
  69         return lr_desc;
  70 }
  71
  72 static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
  73                            struct vgic_lr lr_desc)
  74 {
  75         u64 lr_val;
  76
  77         lr_val = lr_desc.irq;
  78
  79         /*
  80          * Currently all guest IRQs are Group1, as Group0 would result
  81          * in a FIQ in the guest, which it wouldn't expect.
  82          * Eventually we want to make this configurable, so we may revisit
  83          * this in the future.
  84          */
  85         switch (vcpu->kvm->arch.vgic.vgic_model) {
  86         case KVM_DEV_TYPE_ARM_VGIC_V3:
  87                 lr_val |= ICH_LR_GROUP;
  88                 break;
  89         case  KVM_DEV_TYPE_ARM_VGIC_V2:
  90                 if (lr_desc.irq < VGIC_NR_SGIS)
  91                         lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
  92                 break;
  93         default:
  94                 BUG();
  95         }
  96
  97         if (lr_desc.state & LR_STATE_PENDING)
  98                 lr_val |= ICH_LR_PENDING_BIT;
  99         if (lr_desc.state & LR_STATE_ACTIVE)
 100                 lr_val |= ICH_LR_ACTIVE_BIT;
 101         if (lr_desc.state & LR_EOI_INT)
 102                 lr_val |= ICH_LR_EOI;
 103         if (lr_desc.state & LR_HW) {
 104                 lr_val |= ICH_LR_HW;
 105                 lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
 106         }
 107
 108         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[VGIC_V3_LR_INDEX(lr)] = lr_val;
 109
 110         if (!(lr_desc.state & LR_STATE_MASK))
 111                 vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U << lr);
 112         else
 113                 vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr &= ~(1U << lr);
 114 }
 115
 116 static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu)
 117 {
 118         return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr;
 119 }
 120
 121 static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu)
 122 {
 123         return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr;
 124 }
 125
 126 static void vgic_v3_clear_eisr(struct kvm_vcpu *vcpu)
 127 {
 128         vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr = 0;
 129 }
 130
 131 static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu)
 132 {
 133         u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr;
 134         u32 ret = 0;
 135
 136         if (misr & ICH_MISR_EOI)
 137                 ret |= INT_STATUS_EOI;
 138         if (misr & ICH_MISR_U)
 139                 ret |= INT_STATUS_UNDERFLOW;
 140
 141         return ret;
 142 }
 143
 144 static void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 145 {
 146         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
 147
 148         vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
 149         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 150         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 151         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 152 }
 153
 154 static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu)
 155 {
 156         vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr |= ICH_HCR_UIE;
 157 }
 158
 159 static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu)
 160 {
 161         vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE;
 162 }
 163
 164 static void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 165 {
 166         u32 vmcr;
 167
 168         vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
 169         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 170         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 171         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 172
 173         vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
 174 }
 175
 176 static void vgic_v3_enable(struct kvm_vcpu *vcpu)
 177 {
 178         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 179
 180         /*
 181          * By forcing VMCR to zero, the GIC will restore the binary
 182          * points to their reset values. Anything else resets to zero
 183          * anyway.
 184          */
 185         vgic_v3->vgic_vmcr = 0;
 186         vgic_v3->vgic_elrsr = ~0;
 187
 188         /*
 189          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 190          * way, so we force SRE to 1 to demonstrate this to the guest.
 191          * This goes with the spec allowing the value to be RAO/WI.
 192          */
 193         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
 194                 vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
 195         else
 196                 vgic_v3->vgic_sre = 0;
 197
 198         /* Get the show on the road... */
 199         vgic_v3->vgic_hcr = ICH_HCR_EN;
 200 }
 201
 202 static const struct vgic_ops vgic_v3_ops = {
 203         .get_lr                 = vgic_v3_get_lr,
 204         .set_lr                 = vgic_v3_set_lr,
 205         .get_elrsr              = vgic_v3_get_elrsr,
 206         .get_eisr               = vgic_v3_get_eisr,
 207         .clear_eisr             = vgic_v3_clear_eisr,
 208         .get_interrupt_status   = vgic_v3_get_interrupt_status,
 209         .enable_underflow       = vgic_v3_enable_underflow,
 210         .disable_underflow      = vgic_v3_disable_underflow,
 211         .get_vmcr               = vgic_v3_get_vmcr,
 212         .set_vmcr               = vgic_v3_set_vmcr,
 213         .enable                 = vgic_v3_enable,
 214 };
 215
 216 static struct vgic_params vgic_v3_params;
 217
 218 /**
 219  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 220  * @node:       pointer to the DT node
 221  * @ops:        address of a pointer to the GICv3 operations
 222  * @params:     address of a pointer to HW-specific parameters
 223  *
 224  * Returns 0 if a GICv3 has been found, with the low level operations
 225  * in *ops and the HW parameters in *params. Returns an error code
 226  * otherwise.
 227  */
 228 int vgic_v3_probe(struct device_node *vgic_node,
 229                   const struct vgic_ops **ops,
 230                   const struct vgic_params **params)
 231 {
 232         int ret = 0;
 233         u32 gicv_idx;
 234         struct resource vcpu_res;
 235         struct vgic_params *vgic = &vgic_v3_params;
 236
 237         vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0);
 238         if (!vgic->maint_irq) {
 239                 kvm_err("error getting vgic maintenance irq from DT\n");
 240                 ret = -ENXIO;
 241                 goto out;
 242         }
 243
 244         ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 245
 246         /*
 247          * The ListRegs field is 5 bits, but there is a architectural
 248          * maximum of 16 list registers. Just ignore bit 4...
 249          */
 250         vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1;
 251         vgic->can_emulate_gicv2 = false;
 252
 253         if (of_property_read_u32(vgic_node, "#redistributor-regions", &gicv_idx))
 254                 gicv_idx = 1;
 255
 256         gicv_idx += 3; /* Also skip GICD, GICC, GICH */
 257         if (of_address_to_resource(vgic_node, gicv_idx, &vcpu_res)) {
 258                 kvm_info("GICv3: no GICV resource entry\n");
 259                 vgic->vcpu_base = 0;
 260         } else if (!PAGE_ALIGNED(vcpu_res.start)) {
 261                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 262                         (unsigned long long)vcpu_res.start);
 263                 vgic->vcpu_base = 0;
 264         } else if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
 265                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 266                         (unsigned long long)resource_size(&vcpu_res),
 267                         PAGE_SIZE);
 268                 vgic->vcpu_base = 0;
 269         } else {
 270                 vgic->vcpu_base = vcpu_res.start;
 271                 vgic->can_emulate_gicv2 = true;
 272                 kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
 273                                         KVM_DEV_TYPE_ARM_VGIC_V2);
 274         }
 275         if (vgic->vcpu_base == 0)
 276                 kvm_info("disabling GICv2 emulation\n");
 277         kvm_register_device_ops(&kvm_arm_vgic_v3_ops, KVM_DEV_TYPE_ARM_VGIC_V3);
 278
 279         vgic->vctrl_base = NULL;
 280         vgic->type = VGIC_V3;
 281         vgic->max_gic_vcpus = VGIC_V3_MAX_CPUS;
 282
 283         kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
 284                  vcpu_res.start, vgic->maint_irq);
 285
 286         *ops = &vgic_v3_ops;
 287         *params = vgic;
 288
 289 out:
 290         of_node_put(vgic_node);
 291         return ret;
 292 }