virt/kvm/arm/vgic-v3.c

   1 /*
   2  * Copyright (C) 2013 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/kvm.h>
  20 #include <linux/kvm_host.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/irqchip/arm-gic-v3.h>
  28
  29 #include <asm/kvm_emulate.h>
  30 #include <asm/kvm_arm.h>
  31 #include <asm/kvm_asm.h>
  32 #include <asm/kvm_mmu.h>
  33
  34 /* These are for GICv2 emulation only */
  35 #define GICH_LR_VIRTUALID               (0x3ffUL << 0)
  36 #define GICH_LR_PHYSID_CPUID_SHIFT      (10)
  37 #define GICH_LR_PHYSID_CPUID            (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
  38 #define ICH_LR_VIRTUALID_MASK           (BIT_ULL(32) - 1)
  39
  40 static u32 ich_vtr_el2;
  41
  42 static struct vgic_lr vgic_v3_get_lr(const struct kvm_vcpu *vcpu, int lr)
  43 {
  44         struct vgic_lr lr_desc;
  45         u64 val = vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[VGIC_V3_LR_INDEX(lr)];
  46
  47         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
  48                 lr_desc.irq = val & ICH_LR_VIRTUALID_MASK;
  49         else
  50                 lr_desc.irq = val & GICH_LR_VIRTUALID;
  51
  52         lr_desc.source = 0;
  53         if (lr_desc.irq <= 15 &&
  54             vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
  55                 lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
  56
  57         lr_desc.state = 0;
  58
  59         if (val & ICH_LR_PENDING_BIT)
  60                 lr_desc.state |= LR_STATE_PENDING;
  61         if (val & ICH_LR_ACTIVE_BIT)
  62                 lr_desc.state |= LR_STATE_ACTIVE;
  63         if (val & ICH_LR_EOI)
  64                 lr_desc.state |= LR_EOI_INT;
  65         if (val & ICH_LR_HW) {
  66                 lr_desc.state |= LR_HW;
  67                 lr_desc.hwirq = (val >> ICH_LR_PHYS_ID_SHIFT) & GENMASK(9, 0);
  68         }
  69
  70         return lr_desc;
  71 }
  72
  73 static void vgic_v3_set_lr(struct kvm_vcpu *vcpu, int lr,
  74                            struct vgic_lr lr_desc)
  75 {
  76         u64 lr_val;
  77
  78         lr_val = lr_desc.irq;
  79
  80         /*
  81          * Currently all guest IRQs are Group1, as Group0 would result
  82          * in a FIQ in the guest, which it wouldn't expect.
  83          * Eventually we want to make this configurable, so we may revisit
  84          * this in the future.
  85          */
  86         switch (vcpu->kvm->arch.vgic.vgic_model) {
  87         case KVM_DEV_TYPE_ARM_VGIC_V3:
  88                 lr_val |= ICH_LR_GROUP;
  89                 break;
  90         case  KVM_DEV_TYPE_ARM_VGIC_V2:
  91                 if (lr_desc.irq < VGIC_NR_SGIS)
  92                         lr_val |= (u32)lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT;
  93                 break;
  94         default:
  95                 BUG();
  96         }
  97
  98         if (lr_desc.state & LR_STATE_PENDING)
  99                 lr_val |= ICH_LR_PENDING_BIT;
 100         if (lr_desc.state & LR_STATE_ACTIVE)
 101                 lr_val |= ICH_LR_ACTIVE_BIT;
 102         if (lr_desc.state & LR_EOI_INT)
 103                 lr_val |= ICH_LR_EOI;
 104         if (lr_desc.state & LR_HW) {
 105                 lr_val |= ICH_LR_HW;
 106                 lr_val |= ((u64)lr_desc.hwirq) << ICH_LR_PHYS_ID_SHIFT;
 107         }
 108
 109         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[VGIC_V3_LR_INDEX(lr)] = lr_val;
 110
 111         if (!(lr_desc.state & LR_STATE_MASK))
 112                 vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr |= (1U << lr);
 113         else
 114                 vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr &= ~(1U << lr);
 115 }
 116
 117 static u64 vgic_v3_get_elrsr(const struct kvm_vcpu *vcpu)
 118 {
 119         return vcpu->arch.vgic_cpu.vgic_v3.vgic_elrsr;
 120 }
 121
 122 static u64 vgic_v3_get_eisr(const struct kvm_vcpu *vcpu)
 123 {
 124         return vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr;
 125 }
 126
 127 static void vgic_v3_clear_eisr(struct kvm_vcpu *vcpu)
 128 {
 129         vcpu->arch.vgic_cpu.vgic_v3.vgic_eisr = 0;
 130 }
 131
 132 static u32 vgic_v3_get_interrupt_status(const struct kvm_vcpu *vcpu)
 133 {
 134         u32 misr = vcpu->arch.vgic_cpu.vgic_v3.vgic_misr;
 135         u32 ret = 0;
 136
 137         if (misr & ICH_MISR_EOI)
 138                 ret |= INT_STATUS_EOI;
 139         if (misr & ICH_MISR_U)
 140                 ret |= INT_STATUS_UNDERFLOW;
 141
 142         return ret;
 143 }
 144
 145 static void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 146 {
 147         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
 148
 149         vmcrp->ctlr = (vmcr & ICH_VMCR_CTLR_MASK) >> ICH_VMCR_CTLR_SHIFT;
 150         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 151         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 152         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 153 }
 154
 155 static void vgic_v3_enable_underflow(struct kvm_vcpu *vcpu)
 156 {
 157         vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr |= ICH_HCR_UIE;
 158 }
 159
 160 static void vgic_v3_disable_underflow(struct kvm_vcpu *vcpu)
 161 {
 162         vcpu->arch.vgic_cpu.vgic_v3.vgic_hcr &= ~ICH_HCR_UIE;
 163 }
 164
 165 static void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 166 {
 167         u32 vmcr;
 168
 169         vmcr  = (vmcrp->ctlr << ICH_VMCR_CTLR_SHIFT) & ICH_VMCR_CTLR_MASK;
 170         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 171         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 172         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 173
 174         vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
 175 }
 176
 177 static void vgic_v3_enable(struct kvm_vcpu *vcpu)
 178 {
 179         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 180
 181         /*
 182          * By forcing VMCR to zero, the GIC will restore the binary
 183          * points to their reset values. Anything else resets to zero
 184          * anyway.
 185          */
 186         vgic_v3->vgic_vmcr = 0;
 187         vgic_v3->vgic_elrsr = ~0;
 188
 189         /*
 190          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 191          * way, so we force SRE to 1 to demonstrate this to the guest.
 192          * This goes with the spec allowing the value to be RAO/WI.
 193          */
 194         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)
 195                 vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
 196         else
 197                 vgic_v3->vgic_sre = 0;
 198
 199         /* Get the show on the road... */
 200         vgic_v3->vgic_hcr = ICH_HCR_EN;
 201 }
 202
 203 static const struct vgic_ops vgic_v3_ops = {
 204         .get_lr                 = vgic_v3_get_lr,
 205         .set_lr                 = vgic_v3_set_lr,
 206         .get_elrsr              = vgic_v3_get_elrsr,
 207         .get_eisr               = vgic_v3_get_eisr,
 208         .clear_eisr             = vgic_v3_clear_eisr,
 209         .get_interrupt_status   = vgic_v3_get_interrupt_status,
 210         .enable_underflow       = vgic_v3_enable_underflow,
 211         .disable_underflow      = vgic_v3_disable_underflow,
 212         .get_vmcr               = vgic_v3_get_vmcr,
 213         .set_vmcr               = vgic_v3_set_vmcr,
 214         .enable                 = vgic_v3_enable,
 215 };
 216
 217 static struct vgic_params vgic_v3_params;
 218
 219 /**
 220  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 221  * @node:       pointer to the DT node
 222  * @ops:        address of a pointer to the GICv3 operations
 223  * @params:     address of a pointer to HW-specific parameters
 224  *
 225  * Returns 0 if a GICv3 has been found, with the low level operations
 226  * in *ops and the HW parameters in *params. Returns an error code
 227  * otherwise.
 228  */
 229 int vgic_v3_probe(struct device_node *vgic_node,
 230                   const struct vgic_ops **ops,
 231                   const struct vgic_params **params)
 232 {
 233         int ret = 0;
 234         u32 gicv_idx;
 235         struct resource vcpu_res;
 236         struct vgic_params *vgic = &vgic_v3_params;
 237
 238         vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0);
 239         if (!vgic->maint_irq) {
 240                 kvm_err("error getting vgic maintenance irq from DT\n");
 241                 ret = -ENXIO;
 242                 goto out;
 243         }
 244
 245         ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 246
 247         /*
 248          * The ListRegs field is 5 bits, but there is a architectural
 249          * maximum of 16 list registers. Just ignore bit 4...
 250          */
 251         vgic->nr_lr = (ich_vtr_el2 & 0xf) + 1;
 252         vgic->can_emulate_gicv2 = false;
 253
 254         if (of_property_read_u32(vgic_node, "#redistributor-regions", &gicv_idx))
 255                 gicv_idx = 1;
 256
 257         gicv_idx += 3; /* Also skip GICD, GICC, GICH */
 258         if (of_address_to_resource(vgic_node, gicv_idx, &vcpu_res)) {
 259                 kvm_info("GICv3: no GICV resource entry\n");
 260                 vgic->vcpu_base = 0;
 261         } else if (!PAGE_ALIGNED(vcpu_res.start)) {
 262                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 263                         (unsigned long long)vcpu_res.start);
 264                 vgic->vcpu_base = 0;
 265         } else if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
 266                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 267                         (unsigned long long)resource_size(&vcpu_res),
 268                         PAGE_SIZE);
 269                 vgic->vcpu_base = 0;
 270         } else {
 271                 vgic->vcpu_base = vcpu_res.start;
 272                 vgic->can_emulate_gicv2 = true;
 273                 kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
 274                                         KVM_DEV_TYPE_ARM_VGIC_V2);
 275         }
 276         if (vgic->vcpu_base == 0)
 277                 kvm_info("disabling GICv2 emulation\n");
 278         kvm_register_device_ops(&kvm_arm_vgic_v3_ops, KVM_DEV_TYPE_ARM_VGIC_V3);
 279
 280         vgic->vctrl_base = NULL;
 281         vgic->type = VGIC_V3;
 282         vgic->max_gic_vcpus = VGIC_V3_MAX_CPUS;
 283
 284         kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
 285                  vcpu_res.start, vgic->maint_irq);
 286
 287         *ops = &vgic_v3_ops;
 288         *params = vgic;
 289
 290 out:
 291         of_node_put(vgic_node);
 292         return ret;
 293 }