2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/rculist.h>
28 #include <linux/uaccess.h>
30 #include <asm/kvm_emulate.h>
31 #include <asm/kvm_arm.h>
32 #include <asm/kvm_mmu.h>
33 #include <trace/events/kvm.h>
35 #include <kvm/iodev.h>
38 * How the whole thing works (courtesy of Christoffer Dall):
40 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
41 * something is pending on the CPU interface.
42 * - Interrupts that are pending on the distributor are stored on the
43 * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
44 * ioctls and guest mmio ops, and other in-kernel peripherals such as the
46 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
48 * - To calculate the oracle, we need info for each cpu from
49 * compute_pending_for_cpu, which considers:
50 * - PPI: dist->irq_pending & dist->irq_enable
51 * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
52 * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
53 * registers, stored on each vcpu. We only keep one bit of
54 * information per interrupt, making sure that only one vcpu can
55 * accept the interrupt.
56 * - If any of the above state changes, we must recalculate the oracle.
57 * - The same is true when injecting an interrupt, except that we only
58 * consider a single interrupt at a time. The irq_spi_cpu array
59 * contains the target CPU for each SPI.
61 * The handling of level interrupts adds some extra complexity. We
62 * need to track when the interrupt has been EOIed, so we can sample
63 * the 'line' again. This is achieved as such:
65 * - When a level interrupt is moved onto a vcpu, the corresponding
66 * bit in irq_queued is set. As long as this bit is set, the line
67 * will be ignored for further interrupts. The interrupt is injected
68 * into the vcpu with the GICH_LR_EOI bit set (generate a
69 * maintenance interrupt on EOI).
70 * - When the interrupt is EOIed, the maintenance interrupt fires,
71 * and clears the corresponding bit in irq_queued. This allows the
72 * interrupt line to be sampled again.
73 * - Note that level-triggered interrupts can also be set to pending from
74 * writes to GICD_ISPENDRn and lowering the external input line does not
75 * cause the interrupt to become inactive in such a situation.
76 * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
77 * inactive as long as the external input line is held high.
80 * Initialization rules: there are multiple stages to the vgic
81 * initialization, both for the distributor and the CPU interfaces.
85 * - kvm_vgic_early_init(): initialization of static data that doesn't
86 * depend on any sizing information or emulation type. No allocation
89 * - vgic_init(): allocation and initialization of the generic data
90 * structures that depend on sizing information (number of CPUs,
91 * number of interrupts). Also initializes the vcpu specific data
92 * structures. Can be executed lazily for GICv2.
93 * [to be renamed to kvm_vgic_init??]
97 * - kvm_vgic_cpu_early_init(): initialization of static data that
98 * doesn't depend on any sizing information or emulation type. No
99 * allocation is allowed there.
104 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
105 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu);
106 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr);
107 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);
108 static struct irq_phys_map *vgic_irq_map_search(struct kvm_vcpu *vcpu,
111 static const struct vgic_ops *vgic_ops;
112 static const struct vgic_params *vgic;
114 static void add_sgi_source(struct kvm_vcpu *vcpu, int irq, int source)
116 vcpu->kvm->arch.vgic.vm_ops.add_sgi_source(vcpu, irq, source);
119 static bool queue_sgi(struct kvm_vcpu *vcpu, int irq)
121 return vcpu->kvm->arch.vgic.vm_ops.queue_sgi(vcpu, irq);
124 int kvm_vgic_map_resources(struct kvm *kvm)
126 return kvm->arch.vgic.vm_ops.map_resources(kvm, vgic);
130 * struct vgic_bitmap contains a bitmap made of unsigned longs, but
131 * extracts u32s out of them.
133 * This does not work on 64-bit BE systems, because the bitmap access
134 * will store two consecutive 32-bit words with the higher-addressed
135 * register's bits at the lower index and the lower-addressed register's
136 * bits at the higher index.
138 * Therefore, swizzle the register index when accessing the 32-bit word
139 * registers to access the right register's value.
141 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
142 #define REG_OFFSET_SWIZZLE 1
144 #define REG_OFFSET_SWIZZLE 0
147 static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs)
151 nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS);
153 b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL);
157 b->shared = b->private + nr_cpus;
162 static void vgic_free_bitmap(struct vgic_bitmap *b)
170 * Call this function to convert a u64 value to an unsigned long * bitmask
171 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
173 * Warning: Calling this function may modify *val.
175 static unsigned long *u64_to_bitmask(u64 *val)
177 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
178 *val = (*val >> 32) | (*val << 32);
180 return (unsigned long *)val;
183 u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset)
187 return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE;
189 return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE);
192 static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
195 if (irq < VGIC_NR_PRIVATE_IRQS)
196 return test_bit(irq, x->private + cpuid);
198 return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared);
201 void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
206 if (irq < VGIC_NR_PRIVATE_IRQS) {
207 reg = x->private + cpuid;
210 irq -= VGIC_NR_PRIVATE_IRQS;
219 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
221 return x->private + cpuid;
224 unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
229 static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs)
233 size = nr_cpus * VGIC_NR_PRIVATE_IRQS;
234 size += nr_irqs - VGIC_NR_PRIVATE_IRQS;
236 x->private = kzalloc(size, GFP_KERNEL);
240 x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32);
244 static void vgic_free_bytemap(struct vgic_bytemap *b)
251 u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
255 if (offset < VGIC_NR_PRIVATE_IRQS) {
257 offset += cpuid * VGIC_NR_PRIVATE_IRQS;
260 offset -= VGIC_NR_PRIVATE_IRQS;
263 return reg + (offset / sizeof(u32));
266 #define VGIC_CFG_LEVEL 0
267 #define VGIC_CFG_EDGE 1
269 static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
271 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
274 irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
275 return irq_val == VGIC_CFG_EDGE;
278 static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
280 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
282 return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
285 static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq)
287 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
289 return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq);
292 static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
294 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
296 return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
299 static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq)
301 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
303 vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1);
306 static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq)
308 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
310 vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0);
313 static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
315 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
317 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
320 static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
322 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
324 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
327 static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq)
329 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
331 return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq);
334 static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq)
336 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
338 vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1);
341 static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq)
343 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
345 vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0);
348 static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq)
350 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
352 return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq);
355 static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq)
357 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
359 vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0);
362 static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
364 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
366 return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq);
369 void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq)
371 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
373 vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1);
376 void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq)
378 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
380 vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0);
383 static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
385 if (irq < VGIC_NR_PRIVATE_IRQS)
386 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
388 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
389 vcpu->arch.vgic_cpu.pending_shared);
392 void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
394 if (irq < VGIC_NR_PRIVATE_IRQS)
395 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
397 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
398 vcpu->arch.vgic_cpu.pending_shared);
401 static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq)
403 return !vgic_irq_is_queued(vcpu, irq);
407 * vgic_reg_access - access vgic register
408 * @mmio: pointer to the data describing the mmio access
409 * @reg: pointer to the virtual backing of vgic distributor data
410 * @offset: least significant 2 bits used for word offset
411 * @mode: ACCESS_ mode (see defines above)
413 * Helper to make vgic register access easier using one of the access
414 * modes defined for vgic register access
415 * (read,raz,write-ignored,setbit,clearbit,write)
417 void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
418 phys_addr_t offset, int mode)
420 int word_offset = (offset & 3) * 8;
421 u32 mask = (1UL << (mmio->len * 8)) - 1;
425 * Any alignment fault should have been delivered to the guest
426 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
432 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
436 if (mmio->is_write) {
437 u32 data = mmio_data_read(mmio, mask) << word_offset;
438 switch (ACCESS_WRITE_MASK(mode)) {
439 case ACCESS_WRITE_IGNORED:
442 case ACCESS_WRITE_SETBIT:
446 case ACCESS_WRITE_CLEARBIT:
450 case ACCESS_WRITE_VALUE:
451 regval = (regval & ~(mask << word_offset)) | data;
456 switch (ACCESS_READ_MASK(mode)) {
457 case ACCESS_READ_RAZ:
461 case ACCESS_READ_VALUE:
462 mmio_data_write(mmio, mask, regval >> word_offset);
467 bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
470 vgic_reg_access(mmio, NULL, offset,
471 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
475 bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
476 phys_addr_t offset, int vcpu_id, int access)
479 int mode = ACCESS_READ_VALUE | access;
480 struct kvm_vcpu *target_vcpu = kvm_get_vcpu(kvm, vcpu_id);
482 reg = vgic_bitmap_get_reg(&kvm->arch.vgic.irq_enabled, vcpu_id, offset);
483 vgic_reg_access(mmio, reg, offset, mode);
484 if (mmio->is_write) {
485 if (access & ACCESS_WRITE_CLEARBIT) {
486 if (offset < 4) /* Force SGI enabled */
488 vgic_retire_disabled_irqs(target_vcpu);
490 vgic_update_state(kvm);
497 bool vgic_handle_set_pending_reg(struct kvm *kvm,
498 struct kvm_exit_mmio *mmio,
499 phys_addr_t offset, int vcpu_id)
503 int mode = ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT;
504 struct vgic_dist *dist = &kvm->arch.vgic;
506 reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu_id, offset);
507 level_mask = (~(*reg));
509 /* Mark both level and edge triggered irqs as pending */
510 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset);
512 vgic_reg_access(mmio, reg, offset, mode);
514 if (mmio->is_write) {
515 /* Set the soft-pending flag only for level-triggered irqs */
516 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
518 vgic_reg_access(mmio, reg, offset, mode);
521 /* Ignore writes to SGIs */
524 *reg |= orig & 0xffff;
527 vgic_update_state(kvm);
534 bool vgic_handle_clear_pending_reg(struct kvm *kvm,
535 struct kvm_exit_mmio *mmio,
536 phys_addr_t offset, int vcpu_id)
540 int mode = ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT;
541 struct vgic_dist *dist = &kvm->arch.vgic;
543 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset);
545 vgic_reg_access(mmio, reg, offset, mode);
546 if (mmio->is_write) {
547 /* Re-set level triggered level-active interrupts */
548 level_active = vgic_bitmap_get_reg(&dist->irq_level,
550 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset);
551 *reg |= *level_active;
553 /* Ignore writes to SGIs */
556 *reg |= orig & 0xffff;
559 /* Clear soft-pending flags */
560 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
562 vgic_reg_access(mmio, reg, offset, mode);
564 vgic_update_state(kvm);
570 bool vgic_handle_set_active_reg(struct kvm *kvm,
571 struct kvm_exit_mmio *mmio,
572 phys_addr_t offset, int vcpu_id)
575 struct vgic_dist *dist = &kvm->arch.vgic;
577 reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset);
578 vgic_reg_access(mmio, reg, offset,
579 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
581 if (mmio->is_write) {
582 vgic_update_state(kvm);
589 bool vgic_handle_clear_active_reg(struct kvm *kvm,
590 struct kvm_exit_mmio *mmio,
591 phys_addr_t offset, int vcpu_id)
594 struct vgic_dist *dist = &kvm->arch.vgic;
596 reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset);
597 vgic_reg_access(mmio, reg, offset,
598 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
600 if (mmio->is_write) {
601 vgic_update_state(kvm);
608 static u32 vgic_cfg_expand(u16 val)
614 * Turn a 16bit value like abcd...mnop into a 32bit word
615 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
617 for (i = 0; i < 16; i++)
618 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
623 static u16 vgic_cfg_compress(u32 val)
629 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
630 * abcd...mnop which is what we really care about.
632 for (i = 0; i < 16; i++)
633 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
639 * The distributor uses 2 bits per IRQ for the CFG register, but the
640 * LSB is always 0. As such, we only keep the upper bit, and use the
641 * two above functions to compress/expand the bits
643 bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio,
653 val = vgic_cfg_expand(val);
654 vgic_reg_access(mmio, &val, offset,
655 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
656 if (mmio->is_write) {
658 *reg = ~0U; /* Force PPIs/SGIs to 1 */
662 val = vgic_cfg_compress(val);
667 *reg &= 0xffff << 16;
676 * vgic_unqueue_irqs - move pending/active IRQs from LRs to the distributor
677 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
679 * Move any IRQs that have already been assigned to LRs back to the
680 * emulated distributor state so that the complete emulated state can be read
681 * from the main emulation structures without investigating the LRs.
683 void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
685 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
688 for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
689 struct vgic_lr lr = vgic_get_lr(vcpu, i);
692 * There are three options for the state bits:
696 * 11: pending and active
698 BUG_ON(!(lr.state & LR_STATE_MASK));
700 /* Reestablish SGI source for pending and active IRQs */
701 if (lr.irq < VGIC_NR_SGIS)
702 add_sgi_source(vcpu, lr.irq, lr.source);
705 * If the LR holds an active (10) or a pending and active (11)
706 * interrupt then move the active state to the
707 * distributor tracking bit.
709 if (lr.state & LR_STATE_ACTIVE) {
710 vgic_irq_set_active(vcpu, lr.irq);
711 lr.state &= ~LR_STATE_ACTIVE;
715 * Reestablish the pending state on the distributor and the
716 * CPU interface. It may have already been pending, but that
717 * is fine, then we are only setting a few bits that were
720 if (lr.state & LR_STATE_PENDING) {
721 vgic_dist_irq_set_pending(vcpu, lr.irq);
722 lr.state &= ~LR_STATE_PENDING;
725 vgic_set_lr(vcpu, i, lr);
728 * Mark the LR as free for other use.
730 BUG_ON(lr.state & LR_STATE_MASK);
731 vgic_retire_lr(i, lr.irq, vcpu);
732 vgic_irq_clear_queued(vcpu, lr.irq);
734 /* Finally update the VGIC state. */
735 vgic_update_state(vcpu->kvm);
740 struct vgic_io_range *vgic_find_range(const struct vgic_io_range *ranges,
741 int len, gpa_t offset)
743 while (ranges->len) {
744 if (offset >= ranges->base &&
745 (offset + len) <= (ranges->base + ranges->len))
753 static bool vgic_validate_access(const struct vgic_dist *dist,
754 const struct vgic_io_range *range,
755 unsigned long offset)
759 if (!range->bits_per_irq)
760 return true; /* Not an irq-based access */
762 irq = offset * 8 / range->bits_per_irq;
763 if (irq >= dist->nr_irqs)
770 * Call the respective handler function for the given range.
771 * We split up any 64 bit accesses into two consecutive 32 bit
772 * handler calls and merge the result afterwards.
773 * We do this in a little endian fashion regardless of the host's
774 * or guest's endianness, because the GIC is always LE and the rest of
775 * the code (vgic_reg_access) also puts it in a LE fashion already.
776 * At this point we have already identified the handle function, so
777 * range points to that one entry and offset is relative to this.
779 static bool call_range_handler(struct kvm_vcpu *vcpu,
780 struct kvm_exit_mmio *mmio,
781 unsigned long offset,
782 const struct vgic_io_range *range)
784 struct kvm_exit_mmio mmio32;
787 if (likely(mmio->len <= 4))
788 return range->handle_mmio(vcpu, mmio, offset);
791 * Any access bigger than 4 bytes (that we currently handle in KVM)
792 * is actually 8 bytes long, caused by a 64-bit access
796 mmio32.is_write = mmio->is_write;
797 mmio32.private = mmio->private;
799 mmio32.phys_addr = mmio->phys_addr + 4;
800 mmio32.data = &((u32 *)mmio->data)[1];
801 ret = range->handle_mmio(vcpu, &mmio32, offset + 4);
803 mmio32.phys_addr = mmio->phys_addr;
804 mmio32.data = &((u32 *)mmio->data)[0];
805 ret |= range->handle_mmio(vcpu, &mmio32, offset);
811 * vgic_handle_mmio_access - handle an in-kernel MMIO access
812 * This is called by the read/write KVM IO device wrappers below.
813 * @vcpu: pointer to the vcpu performing the access
814 * @this: pointer to the KVM IO device in charge
815 * @addr: guest physical address of the access
816 * @len: size of the access
817 * @val: pointer to the data region
818 * @is_write: read or write access
820 * returns true if the MMIO access could be performed
822 static int vgic_handle_mmio_access(struct kvm_vcpu *vcpu,
823 struct kvm_io_device *this, gpa_t addr,
824 int len, void *val, bool is_write)
826 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
827 struct vgic_io_device *iodev = container_of(this,
828 struct vgic_io_device, dev);
829 struct kvm_run *run = vcpu->run;
830 const struct vgic_io_range *range;
831 struct kvm_exit_mmio mmio;
835 offset = addr - iodev->addr;
836 range = vgic_find_range(iodev->reg_ranges, len, offset);
837 if (unlikely(!range || !range->handle_mmio)) {
838 pr_warn("Unhandled access %d %08llx %d\n", is_write, addr, len);
842 mmio.phys_addr = addr;
844 mmio.is_write = is_write;
846 mmio.private = iodev->redist_vcpu;
848 spin_lock(&dist->lock);
849 offset -= range->base;
850 if (vgic_validate_access(dist, range, offset)) {
851 updated_state = call_range_handler(vcpu, &mmio, offset, range);
855 updated_state = false;
857 spin_unlock(&dist->lock);
858 run->mmio.is_write = is_write;
860 run->mmio.phys_addr = addr;
861 memcpy(run->mmio.data, val, len);
863 kvm_handle_mmio_return(vcpu, run);
866 vgic_kick_vcpus(vcpu->kvm);
871 static int vgic_handle_mmio_read(struct kvm_vcpu *vcpu,
872 struct kvm_io_device *this,
873 gpa_t addr, int len, void *val)
875 return vgic_handle_mmio_access(vcpu, this, addr, len, val, false);
878 static int vgic_handle_mmio_write(struct kvm_vcpu *vcpu,
879 struct kvm_io_device *this,
880 gpa_t addr, int len, const void *val)
882 return vgic_handle_mmio_access(vcpu, this, addr, len, (void *)val,
886 struct kvm_io_device_ops vgic_io_ops = {
887 .read = vgic_handle_mmio_read,
888 .write = vgic_handle_mmio_write,
892 * vgic_register_kvm_io_dev - register VGIC register frame on the KVM I/O bus
893 * @kvm: The VM structure pointer
894 * @base: The (guest) base address for the register frame
895 * @len: Length of the register frame window
896 * @ranges: Describing the handler functions for each register
897 * @redist_vcpu_id: The VCPU ID to pass on to the handlers on call
898 * @iodev: Points to memory to be passed on to the handler
900 * @iodev stores the parameters of this function to be usable by the handler
901 * respectively the dispatcher function (since the KVM I/O bus framework lacks
902 * an opaque parameter). Initialization is done in this function, but the
903 * reference should be valid and unique for the whole VGIC lifetime.
904 * If the register frame is not mapped for a specific VCPU, pass -1 to
907 int vgic_register_kvm_io_dev(struct kvm *kvm, gpa_t base, int len,
908 const struct vgic_io_range *ranges,
910 struct vgic_io_device *iodev)
912 struct kvm_vcpu *vcpu = NULL;
915 if (redist_vcpu_id >= 0)
916 vcpu = kvm_get_vcpu(kvm, redist_vcpu_id);
920 iodev->reg_ranges = ranges;
921 iodev->redist_vcpu = vcpu;
923 kvm_iodevice_init(&iodev->dev, &vgic_io_ops);
925 mutex_lock(&kvm->slots_lock);
927 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, base, len,
929 mutex_unlock(&kvm->slots_lock);
931 /* Mark the iodev as invalid if registration fails. */
933 iodev->dev.ops = NULL;
938 static int vgic_nr_shared_irqs(struct vgic_dist *dist)
940 return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS;
943 static int compute_active_for_cpu(struct kvm_vcpu *vcpu)
945 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
946 unsigned long *active, *enabled, *act_percpu, *act_shared;
947 unsigned long active_private, active_shared;
948 int nr_shared = vgic_nr_shared_irqs(dist);
951 vcpu_id = vcpu->vcpu_id;
952 act_percpu = vcpu->arch.vgic_cpu.active_percpu;
953 act_shared = vcpu->arch.vgic_cpu.active_shared;
955 active = vgic_bitmap_get_cpu_map(&dist->irq_active, vcpu_id);
956 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
957 bitmap_and(act_percpu, active, enabled, VGIC_NR_PRIVATE_IRQS);
959 active = vgic_bitmap_get_shared_map(&dist->irq_active);
960 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
961 bitmap_and(act_shared, active, enabled, nr_shared);
962 bitmap_and(act_shared, act_shared,
963 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
966 active_private = find_first_bit(act_percpu, VGIC_NR_PRIVATE_IRQS);
967 active_shared = find_first_bit(act_shared, nr_shared);
969 return (active_private < VGIC_NR_PRIVATE_IRQS ||
970 active_shared < nr_shared);
973 static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
975 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
976 unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
977 unsigned long pending_private, pending_shared;
978 int nr_shared = vgic_nr_shared_irqs(dist);
981 vcpu_id = vcpu->vcpu_id;
982 pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
983 pend_shared = vcpu->arch.vgic_cpu.pending_shared;
985 pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id);
986 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
987 bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
989 pending = vgic_bitmap_get_shared_map(&dist->irq_pending);
990 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
991 bitmap_and(pend_shared, pending, enabled, nr_shared);
992 bitmap_and(pend_shared, pend_shared,
993 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
996 pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
997 pending_shared = find_first_bit(pend_shared, nr_shared);
998 return (pending_private < VGIC_NR_PRIVATE_IRQS ||
999 pending_shared < vgic_nr_shared_irqs(dist));
1003 * Update the interrupt state and determine which CPUs have pending
1004 * or active interrupts. Must be called with distributor lock held.
1006 void vgic_update_state(struct kvm *kvm)
1008 struct vgic_dist *dist = &kvm->arch.vgic;
1009 struct kvm_vcpu *vcpu;
1012 if (!dist->enabled) {
1013 set_bit(0, dist->irq_pending_on_cpu);
1017 kvm_for_each_vcpu(c, vcpu, kvm) {
1018 if (compute_pending_for_cpu(vcpu))
1019 set_bit(c, dist->irq_pending_on_cpu);
1021 if (compute_active_for_cpu(vcpu))
1022 set_bit(c, dist->irq_active_on_cpu);
1024 clear_bit(c, dist->irq_active_on_cpu);
1028 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr)
1030 return vgic_ops->get_lr(vcpu, lr);
1033 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr,
1036 vgic_ops->set_lr(vcpu, lr, vlr);
1039 static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1042 vgic_ops->sync_lr_elrsr(vcpu, lr, vlr);
1045 static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu)
1047 return vgic_ops->get_elrsr(vcpu);
1050 static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu)
1052 return vgic_ops->get_eisr(vcpu);
1055 static inline void vgic_clear_eisr(struct kvm_vcpu *vcpu)
1057 vgic_ops->clear_eisr(vcpu);
1060 static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu)
1062 return vgic_ops->get_interrupt_status(vcpu);
1065 static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu)
1067 vgic_ops->enable_underflow(vcpu);
1070 static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu)
1072 vgic_ops->disable_underflow(vcpu);
1075 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1077 vgic_ops->get_vmcr(vcpu, vmcr);
1080 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1082 vgic_ops->set_vmcr(vcpu, vmcr);
1085 static inline void vgic_enable(struct kvm_vcpu *vcpu)
1087 vgic_ops->enable(vcpu);
1090 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu)
1092 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1093 struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr);
1096 vgic_set_lr(vcpu, lr_nr, vlr);
1097 clear_bit(lr_nr, vgic_cpu->lr_used);
1098 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1099 vgic_sync_lr_elrsr(vcpu, lr_nr, vlr);
1103 * An interrupt may have been disabled after being made pending on the
1104 * CPU interface (the classic case is a timer running while we're
1105 * rebooting the guest - the interrupt would kick as soon as the CPU
1106 * interface gets enabled, with deadly consequences).
1108 * The solution is to examine already active LRs, and check the
1109 * interrupt is still enabled. If not, just retire it.
1111 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
1113 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1116 for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) {
1117 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1119 if (!vgic_irq_is_enabled(vcpu, vlr.irq)) {
1120 vgic_retire_lr(lr, vlr.irq, vcpu);
1121 if (vgic_irq_is_queued(vcpu, vlr.irq))
1122 vgic_irq_clear_queued(vcpu, vlr.irq);
1127 static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq,
1128 int lr_nr, struct vgic_lr vlr)
1130 if (vgic_irq_is_active(vcpu, irq)) {
1131 vlr.state |= LR_STATE_ACTIVE;
1132 kvm_debug("Set active, clear distributor: 0x%x\n", vlr.state);
1133 vgic_irq_clear_active(vcpu, irq);
1134 vgic_update_state(vcpu->kvm);
1135 } else if (vgic_dist_irq_is_pending(vcpu, irq)) {
1136 vlr.state |= LR_STATE_PENDING;
1137 kvm_debug("Set pending: 0x%x\n", vlr.state);
1140 if (!vgic_irq_is_edge(vcpu, irq))
1141 vlr.state |= LR_EOI_INT;
1143 if (vlr.irq >= VGIC_NR_SGIS) {
1144 struct irq_phys_map *map;
1145 map = vgic_irq_map_search(vcpu, irq);
1148 * If we have a mapping, and the virtual interrupt is
1149 * being injected, then we must set the state to
1150 * active in the physical world. Otherwise the
1151 * physical interrupt will fire and the guest will
1152 * exit before processing the virtual interrupt.
1157 BUG_ON(!map->active);
1158 vlr.hwirq = map->phys_irq;
1160 vlr.state &= ~LR_EOI_INT;
1162 ret = irq_set_irqchip_state(map->irq,
1163 IRQCHIP_STATE_ACTIVE,
1168 * Make sure we're not going to sample this
1169 * again, as a HW-backed interrupt cannot be
1170 * in the PENDING_ACTIVE stage.
1172 vgic_irq_set_queued(vcpu, irq);
1176 vgic_set_lr(vcpu, lr_nr, vlr);
1177 vgic_sync_lr_elrsr(vcpu, lr_nr, vlr);
1181 * Queue an interrupt to a CPU virtual interface. Return true on success,
1182 * or false if it wasn't possible to queue it.
1183 * sgi_source must be zero for any non-SGI interrupts.
1185 bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
1187 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1188 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1192 /* Sanitize the input... */
1193 BUG_ON(sgi_source_id & ~7);
1194 BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
1195 BUG_ON(irq >= dist->nr_irqs);
1197 kvm_debug("Queue IRQ%d\n", irq);
1199 lr = vgic_cpu->vgic_irq_lr_map[irq];
1201 /* Do we have an active interrupt for the same CPUID? */
1202 if (lr != LR_EMPTY) {
1203 vlr = vgic_get_lr(vcpu, lr);
1204 if (vlr.source == sgi_source_id) {
1205 kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq);
1206 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
1207 vgic_queue_irq_to_lr(vcpu, irq, lr, vlr);
1212 /* Try to use another LR for this interrupt */
1213 lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
1215 if (lr >= vgic->nr_lr)
1218 kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
1219 vgic_cpu->vgic_irq_lr_map[irq] = lr;
1220 set_bit(lr, vgic_cpu->lr_used);
1223 vlr.source = sgi_source_id;
1225 vgic_queue_irq_to_lr(vcpu, irq, lr, vlr);
1230 static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
1232 if (!vgic_can_sample_irq(vcpu, irq))
1233 return true; /* level interrupt, already queued */
1235 if (vgic_queue_irq(vcpu, 0, irq)) {
1236 if (vgic_irq_is_edge(vcpu, irq)) {
1237 vgic_dist_irq_clear_pending(vcpu, irq);
1238 vgic_cpu_irq_clear(vcpu, irq);
1240 vgic_irq_set_queued(vcpu, irq);
1250 * Fill the list registers with pending interrupts before running the
1253 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1255 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1256 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1257 unsigned long *pa_percpu, *pa_shared;
1260 int nr_shared = vgic_nr_shared_irqs(dist);
1262 vcpu_id = vcpu->vcpu_id;
1264 pa_percpu = vcpu->arch.vgic_cpu.pend_act_percpu;
1265 pa_shared = vcpu->arch.vgic_cpu.pend_act_shared;
1267 bitmap_or(pa_percpu, vgic_cpu->pending_percpu, vgic_cpu->active_percpu,
1268 VGIC_NR_PRIVATE_IRQS);
1269 bitmap_or(pa_shared, vgic_cpu->pending_shared, vgic_cpu->active_shared,
1272 * We may not have any pending interrupt, or the interrupts
1273 * may have been serviced from another vcpu. In all cases,
1276 if (!kvm_vgic_vcpu_pending_irq(vcpu) && !kvm_vgic_vcpu_active_irq(vcpu))
1280 for_each_set_bit(i, pa_percpu, VGIC_NR_SGIS) {
1281 if (!queue_sgi(vcpu, i))
1286 for_each_set_bit_from(i, pa_percpu, VGIC_NR_PRIVATE_IRQS) {
1287 if (!vgic_queue_hwirq(vcpu, i))
1292 for_each_set_bit(i, pa_shared, nr_shared) {
1293 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
1302 vgic_enable_underflow(vcpu);
1304 vgic_disable_underflow(vcpu);
1306 * We're about to run this VCPU, and we've consumed
1307 * everything the distributor had in store for
1308 * us. Claim we don't have anything pending. We'll
1309 * adjust that if needed while exiting.
1311 clear_bit(vcpu_id, dist->irq_pending_on_cpu);
1315 static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1317 u32 status = vgic_get_interrupt_status(vcpu);
1318 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1319 bool level_pending = false;
1320 struct kvm *kvm = vcpu->kvm;
1322 kvm_debug("STATUS = %08x\n", status);
1324 if (status & INT_STATUS_EOI) {
1326 * Some level interrupts have been EOIed. Clear their
1329 u64 eisr = vgic_get_eisr(vcpu);
1330 unsigned long *eisr_ptr = u64_to_bitmask(&eisr);
1333 for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) {
1334 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1335 WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq));
1337 spin_lock(&dist->lock);
1338 vgic_irq_clear_queued(vcpu, vlr.irq);
1339 WARN_ON(vlr.state & LR_STATE_MASK);
1341 vgic_set_lr(vcpu, lr, vlr);
1344 * If the IRQ was EOIed it was also ACKed and we we
1345 * therefore assume we can clear the soft pending
1346 * state (should it had been set) for this interrupt.
1348 * Note: if the IRQ soft pending state was set after
1349 * the IRQ was acked, it actually shouldn't be
1350 * cleared, but we have no way of knowing that unless
1351 * we start trapping ACKs when the soft-pending state
1354 vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq);
1357 * kvm_notify_acked_irq calls kvm_set_irq()
1358 * to reset the IRQ level. Need to release the
1359 * lock for kvm_set_irq to grab it.
1361 spin_unlock(&dist->lock);
1363 kvm_notify_acked_irq(kvm, 0,
1364 vlr.irq - VGIC_NR_PRIVATE_IRQS);
1365 spin_lock(&dist->lock);
1367 /* Any additional pending interrupt? */
1368 if (vgic_dist_irq_get_level(vcpu, vlr.irq)) {
1369 vgic_cpu_irq_set(vcpu, vlr.irq);
1370 level_pending = true;
1372 vgic_dist_irq_clear_pending(vcpu, vlr.irq);
1373 vgic_cpu_irq_clear(vcpu, vlr.irq);
1376 spin_unlock(&dist->lock);
1379 * Despite being EOIed, the LR may not have
1380 * been marked as empty.
1382 vgic_sync_lr_elrsr(vcpu, lr, vlr);
1386 if (status & INT_STATUS_UNDERFLOW)
1387 vgic_disable_underflow(vcpu);
1390 * In the next iterations of the vcpu loop, if we sync the vgic state
1391 * after flushing it, but before entering the guest (this happens for
1392 * pending signals and vmid rollovers), then make sure we don't pick
1393 * up any old maintenance interrupts here.
1395 vgic_clear_eisr(vcpu);
1397 return level_pending;
1401 * Save the physical active state, and reset it to inactive.
1403 * Return 1 if HW interrupt went from active to inactive, and 0 otherwise.
1405 static int vgic_sync_hwirq(struct kvm_vcpu *vcpu, struct vgic_lr vlr)
1407 struct irq_phys_map *map;
1410 if (!(vlr.state & LR_HW))
1413 map = vgic_irq_map_search(vcpu, vlr.irq);
1414 BUG_ON(!map || !map->active);
1416 ret = irq_get_irqchip_state(map->irq,
1417 IRQCHIP_STATE_ACTIVE,
1423 ret = irq_set_irqchip_state(map->irq,
1424 IRQCHIP_STATE_ACTIVE,
1433 /* Sync back the VGIC state after a guest run */
1434 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1436 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1437 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1439 unsigned long *elrsr_ptr;
1443 level_pending = vgic_process_maintenance(vcpu);
1444 elrsr = vgic_get_elrsr(vcpu);
1445 elrsr_ptr = u64_to_bitmask(&elrsr);
1447 /* Deal with HW interrupts, and clear mappings for empty LRs */
1448 for (lr = 0; lr < vgic->nr_lr; lr++) {
1451 if (!test_bit(lr, vgic_cpu->lr_used))
1454 vlr = vgic_get_lr(vcpu, lr);
1455 if (vgic_sync_hwirq(vcpu, vlr)) {
1457 * So this is a HW interrupt that the guest
1458 * EOI-ed. Clean the LR state and allow the
1459 * interrupt to be sampled again.
1463 vgic_set_lr(vcpu, lr, vlr);
1464 vgic_irq_clear_queued(vcpu, vlr.irq);
1465 set_bit(lr, elrsr_ptr);
1468 if (!test_bit(lr, elrsr_ptr))
1471 clear_bit(lr, vgic_cpu->lr_used);
1473 BUG_ON(vlr.irq >= dist->nr_irqs);
1474 vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY;
1477 /* Check if we still have something up our sleeve... */
1478 pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr);
1479 if (level_pending || pending < vgic->nr_lr)
1480 set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
1483 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1485 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1487 if (!irqchip_in_kernel(vcpu->kvm))
1490 spin_lock(&dist->lock);
1491 __kvm_vgic_flush_hwstate(vcpu);
1492 spin_unlock(&dist->lock);
1495 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1497 if (!irqchip_in_kernel(vcpu->kvm))
1500 __kvm_vgic_sync_hwstate(vcpu);
1503 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1505 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1507 if (!irqchip_in_kernel(vcpu->kvm))
1510 return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
1513 int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu)
1515 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1517 if (!irqchip_in_kernel(vcpu->kvm))
1520 return test_bit(vcpu->vcpu_id, dist->irq_active_on_cpu);
1524 void vgic_kick_vcpus(struct kvm *kvm)
1526 struct kvm_vcpu *vcpu;
1530 * We've injected an interrupt, time to find out who deserves
1533 kvm_for_each_vcpu(c, vcpu, kvm) {
1534 if (kvm_vgic_vcpu_pending_irq(vcpu))
1535 kvm_vcpu_kick(vcpu);
1539 static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1541 int edge_triggered = vgic_irq_is_edge(vcpu, irq);
1544 * Only inject an interrupt if:
1545 * - edge triggered and we have a rising edge
1546 * - level triggered and we change level
1548 if (edge_triggered) {
1549 int state = vgic_dist_irq_is_pending(vcpu, irq);
1550 return level > state;
1552 int state = vgic_dist_irq_get_level(vcpu, irq);
1553 return level != state;
1557 static int vgic_update_irq_pending(struct kvm *kvm, int cpuid,
1558 struct irq_phys_map *map,
1559 unsigned int irq_num, bool level)
1561 struct vgic_dist *dist = &kvm->arch.vgic;
1562 struct kvm_vcpu *vcpu;
1563 int edge_triggered, level_triggered;
1565 bool ret = true, can_inject = true;
1567 if (irq_num >= min(kvm->arch.vgic.nr_irqs, 1020))
1570 spin_lock(&dist->lock);
1572 vcpu = kvm_get_vcpu(kvm, cpuid);
1573 edge_triggered = vgic_irq_is_edge(vcpu, irq_num);
1574 level_triggered = !edge_triggered;
1576 if (!vgic_validate_injection(vcpu, irq_num, level)) {
1581 if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1582 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1583 if (cpuid == VCPU_NOT_ALLOCATED) {
1584 /* Pretend we use CPU0, and prevent injection */
1588 vcpu = kvm_get_vcpu(kvm, cpuid);
1591 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1594 if (level_triggered)
1595 vgic_dist_irq_set_level(vcpu, irq_num);
1596 vgic_dist_irq_set_pending(vcpu, irq_num);
1598 if (level_triggered) {
1599 vgic_dist_irq_clear_level(vcpu, irq_num);
1600 if (!vgic_dist_irq_soft_pend(vcpu, irq_num))
1601 vgic_dist_irq_clear_pending(vcpu, irq_num);
1608 enabled = vgic_irq_is_enabled(vcpu, irq_num);
1610 if (!enabled || !can_inject) {
1615 if (!vgic_can_sample_irq(vcpu, irq_num)) {
1617 * Level interrupt in progress, will be picked up
1625 vgic_cpu_irq_set(vcpu, irq_num);
1626 set_bit(cpuid, dist->irq_pending_on_cpu);
1630 spin_unlock(&dist->lock);
1633 /* kick the specified vcpu */
1634 kvm_vcpu_kick(kvm_get_vcpu(kvm, cpuid));
1640 static int vgic_lazy_init(struct kvm *kvm)
1644 if (unlikely(!vgic_initialized(kvm))) {
1646 * We only provide the automatic initialization of the VGIC
1647 * for the legacy case of a GICv2. Any other type must
1648 * be explicitly initialized once setup with the respective
1651 if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2)
1654 mutex_lock(&kvm->lock);
1655 ret = vgic_init(kvm);
1656 mutex_unlock(&kvm->lock);
1663 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1664 * @kvm: The VM structure pointer
1665 * @cpuid: The CPU for PPIs
1666 * @irq_num: The IRQ number that is assigned to the device. This IRQ
1667 * must not be mapped to a HW interrupt.
1668 * @level: Edge-triggered: true: to trigger the interrupt
1669 * false: to ignore the call
1670 * Level-sensitive true: raise the input signal
1671 * false: lower the input signal
1673 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1674 * level-sensitive interrupts. You can think of the level parameter as 1
1675 * being HIGH and 0 being LOW and all devices being active-HIGH.
1677 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1680 struct irq_phys_map *map;
1683 ret = vgic_lazy_init(kvm);
1687 map = vgic_irq_map_search(kvm_get_vcpu(kvm, cpuid), irq_num);
1691 return vgic_update_irq_pending(kvm, cpuid, NULL, irq_num, level);
1695 * kvm_vgic_inject_mapped_irq - Inject a physically mapped IRQ to the vgic
1696 * @kvm: The VM structure pointer
1697 * @cpuid: The CPU for PPIs
1698 * @map: Pointer to a irq_phys_map structure describing the mapping
1699 * @level: Edge-triggered: true: to trigger the interrupt
1700 * false: to ignore the call
1701 * Level-sensitive true: raise the input signal
1702 * false: lower the input signal
1704 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1705 * level-sensitive interrupts. You can think of the level parameter as 1
1706 * being HIGH and 0 being LOW and all devices being active-HIGH.
1708 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid,
1709 struct irq_phys_map *map, bool level)
1713 ret = vgic_lazy_init(kvm);
1717 return vgic_update_irq_pending(kvm, cpuid, map, map->virt_irq, level);
1720 static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1723 * We cannot rely on the vgic maintenance interrupt to be
1724 * delivered synchronously. This means we can only use it to
1725 * exit the VM, and we perform the handling of EOIed
1726 * interrupts on the exit path (see vgic_process_maintenance).
1731 static struct list_head *vgic_get_irq_phys_map_list(struct kvm_vcpu *vcpu,
1734 if (virt_irq < VGIC_NR_PRIVATE_IRQS)
1735 return &vcpu->arch.vgic_cpu.irq_phys_map_list;
1737 return &vcpu->kvm->arch.vgic.irq_phys_map_list;
1741 * kvm_vgic_map_phys_irq - map a virtual IRQ to a physical IRQ
1742 * @vcpu: The VCPU pointer
1743 * @virt_irq: The virtual irq number
1744 * @irq: The Linux IRQ number
1746 * Establish a mapping between a guest visible irq (@virt_irq) and a
1747 * Linux irq (@irq). On injection, @virt_irq will be associated with
1748 * the physical interrupt represented by @irq. This mapping can be
1749 * established multiple times as long as the parameters are the same.
1751 * Returns a valid pointer on success, and an error pointer otherwise
1753 struct irq_phys_map *kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu,
1754 int virt_irq, int irq)
1756 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1757 struct list_head *root = vgic_get_irq_phys_map_list(vcpu, virt_irq);
1758 struct irq_phys_map *map;
1759 struct irq_phys_map_entry *entry;
1760 struct irq_desc *desc;
1761 struct irq_data *data;
1764 desc = irq_to_desc(irq);
1766 kvm_err("%s: no interrupt descriptor\n", __func__);
1767 return ERR_PTR(-EINVAL);
1770 data = irq_desc_get_irq_data(desc);
1771 while (data->parent_data)
1772 data = data->parent_data;
1774 phys_irq = data->hwirq;
1776 /* Create a new mapping */
1777 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1779 return ERR_PTR(-ENOMEM);
1781 spin_lock(&dist->irq_phys_map_lock);
1783 /* Try to match an existing mapping */
1784 map = vgic_irq_map_search(vcpu, virt_irq);
1786 /* Make sure this mapping matches */
1787 if (map->phys_irq != phys_irq ||
1789 map = ERR_PTR(-EINVAL);
1791 /* Found an existing, valid mapping */
1796 map->virt_irq = virt_irq;
1797 map->phys_irq = phys_irq;
1800 list_add_tail_rcu(&entry->entry, root);
1803 spin_unlock(&dist->irq_phys_map_lock);
1804 /* If we've found a hit in the existing list, free the useless
1806 if (IS_ERR(map) || map != &entry->map)
1811 static struct irq_phys_map *vgic_irq_map_search(struct kvm_vcpu *vcpu,
1814 struct list_head *root = vgic_get_irq_phys_map_list(vcpu, virt_irq);
1815 struct irq_phys_map_entry *entry;
1816 struct irq_phys_map *map;
1820 list_for_each_entry_rcu(entry, root, entry) {
1822 if (map->virt_irq == virt_irq) {
1833 static void vgic_free_phys_irq_map_rcu(struct rcu_head *rcu)
1835 struct irq_phys_map_entry *entry;
1837 entry = container_of(rcu, struct irq_phys_map_entry, rcu);
1842 * kvm_vgic_get_phys_irq_active - Return the active state of a mapped IRQ
1844 * Return the logical active state of a mapped interrupt. This doesn't
1845 * necessarily reflects the current HW state.
1847 bool kvm_vgic_get_phys_irq_active(struct irq_phys_map *map)
1854 * kvm_vgic_set_phys_irq_active - Set the active state of a mapped IRQ
1856 * Set the logical active state of a mapped interrupt. This doesn't
1857 * immediately affects the HW state.
1859 void kvm_vgic_set_phys_irq_active(struct irq_phys_map *map, bool active)
1862 map->active = active;
1866 * kvm_vgic_unmap_phys_irq - Remove a virtual to physical IRQ mapping
1867 * @vcpu: The VCPU pointer
1868 * @map: The pointer to a mapping obtained through kvm_vgic_map_phys_irq
1870 * Remove an existing mapping between virtual and physical interrupts.
1872 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, struct irq_phys_map *map)
1874 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1875 struct irq_phys_map_entry *entry;
1876 struct list_head *root;
1881 root = vgic_get_irq_phys_map_list(vcpu, map->virt_irq);
1883 spin_lock(&dist->irq_phys_map_lock);
1885 list_for_each_entry(entry, root, entry) {
1886 if (&entry->map == map) {
1887 list_del_rcu(&entry->entry);
1888 call_rcu(&entry->rcu, vgic_free_phys_irq_map_rcu);
1893 spin_unlock(&dist->irq_phys_map_lock);
1898 static void vgic_destroy_irq_phys_map(struct kvm *kvm, struct list_head *root)
1900 struct vgic_dist *dist = &kvm->arch.vgic;
1901 struct irq_phys_map_entry *entry;
1903 spin_lock(&dist->irq_phys_map_lock);
1905 list_for_each_entry(entry, root, entry) {
1906 list_del_rcu(&entry->entry);
1907 call_rcu(&entry->rcu, vgic_free_phys_irq_map_rcu);
1910 spin_unlock(&dist->irq_phys_map_lock);
1913 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
1915 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1917 kfree(vgic_cpu->pending_shared);
1918 kfree(vgic_cpu->active_shared);
1919 kfree(vgic_cpu->pend_act_shared);
1920 kfree(vgic_cpu->vgic_irq_lr_map);
1921 vgic_destroy_irq_phys_map(vcpu->kvm, &vgic_cpu->irq_phys_map_list);
1922 vgic_cpu->pending_shared = NULL;
1923 vgic_cpu->active_shared = NULL;
1924 vgic_cpu->pend_act_shared = NULL;
1925 vgic_cpu->vgic_irq_lr_map = NULL;
1928 static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs)
1930 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1932 int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8;
1933 vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL);
1934 vgic_cpu->active_shared = kzalloc(sz, GFP_KERNEL);
1935 vgic_cpu->pend_act_shared = kzalloc(sz, GFP_KERNEL);
1936 vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL);
1938 if (!vgic_cpu->pending_shared
1939 || !vgic_cpu->active_shared
1940 || !vgic_cpu->pend_act_shared
1941 || !vgic_cpu->vgic_irq_lr_map) {
1942 kvm_vgic_vcpu_destroy(vcpu);
1946 memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs);
1949 * Store the number of LRs per vcpu, so we don't have to go
1950 * all the way to the distributor structure to find out. Only
1951 * assembly code should use this one.
1953 vgic_cpu->nr_lr = vgic->nr_lr;
1959 * kvm_vgic_vcpu_early_init - Earliest possible per-vcpu vgic init stage
1961 * No memory allocation should be performed here, only static init.
1963 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu)
1965 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1966 INIT_LIST_HEAD(&vgic_cpu->irq_phys_map_list);
1970 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
1972 * The host's GIC naturally limits the maximum amount of VCPUs a guest
1975 int kvm_vgic_get_max_vcpus(void)
1977 return vgic->max_gic_vcpus;
1980 void kvm_vgic_destroy(struct kvm *kvm)
1982 struct vgic_dist *dist = &kvm->arch.vgic;
1983 struct kvm_vcpu *vcpu;
1986 kvm_for_each_vcpu(i, vcpu, kvm)
1987 kvm_vgic_vcpu_destroy(vcpu);
1989 vgic_free_bitmap(&dist->irq_enabled);
1990 vgic_free_bitmap(&dist->irq_level);
1991 vgic_free_bitmap(&dist->irq_pending);
1992 vgic_free_bitmap(&dist->irq_soft_pend);
1993 vgic_free_bitmap(&dist->irq_queued);
1994 vgic_free_bitmap(&dist->irq_cfg);
1995 vgic_free_bytemap(&dist->irq_priority);
1996 if (dist->irq_spi_target) {
1997 for (i = 0; i < dist->nr_cpus; i++)
1998 vgic_free_bitmap(&dist->irq_spi_target[i]);
2000 kfree(dist->irq_sgi_sources);
2001 kfree(dist->irq_spi_cpu);
2002 kfree(dist->irq_spi_mpidr);
2003 kfree(dist->irq_spi_target);
2004 kfree(dist->irq_pending_on_cpu);
2005 kfree(dist->irq_active_on_cpu);
2006 vgic_destroy_irq_phys_map(kvm, &dist->irq_phys_map_list);
2007 dist->irq_sgi_sources = NULL;
2008 dist->irq_spi_cpu = NULL;
2009 dist->irq_spi_target = NULL;
2010 dist->irq_pending_on_cpu = NULL;
2011 dist->irq_active_on_cpu = NULL;
2016 * Allocate and initialize the various data structures. Must be called
2017 * with kvm->lock held!
2019 int vgic_init(struct kvm *kvm)
2021 struct vgic_dist *dist = &kvm->arch.vgic;
2022 struct kvm_vcpu *vcpu;
2023 int nr_cpus, nr_irqs;
2024 int ret, i, vcpu_id;
2026 if (vgic_initialized(kvm))
2029 nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus);
2030 if (!nr_cpus) /* No vcpus? Can't be good... */
2034 * If nobody configured the number of interrupts, use the
2038 dist->nr_irqs = VGIC_NR_IRQS_LEGACY;
2040 nr_irqs = dist->nr_irqs;
2042 ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs);
2043 ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs);
2044 ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs);
2045 ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs);
2046 ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs);
2047 ret |= vgic_init_bitmap(&dist->irq_active, nr_cpus, nr_irqs);
2048 ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs);
2049 ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs);
2054 dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL);
2055 dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL);
2056 dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus,
2058 dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long),
2060 dist->irq_active_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long),
2062 if (!dist->irq_sgi_sources ||
2063 !dist->irq_spi_cpu ||
2064 !dist->irq_spi_target ||
2065 !dist->irq_pending_on_cpu ||
2066 !dist->irq_active_on_cpu) {
2071 for (i = 0; i < nr_cpus; i++)
2072 ret |= vgic_init_bitmap(&dist->irq_spi_target[i],
2078 ret = kvm->arch.vgic.vm_ops.init_model(kvm);
2082 kvm_for_each_vcpu(vcpu_id, vcpu, kvm) {
2083 ret = vgic_vcpu_init_maps(vcpu, nr_irqs);
2085 kvm_err("VGIC: Failed to allocate vcpu memory\n");
2089 for (i = 0; i < dist->nr_irqs; i++) {
2090 if (i < VGIC_NR_PPIS)
2091 vgic_bitmap_set_irq_val(&dist->irq_enabled,
2092 vcpu->vcpu_id, i, 1);
2093 if (i < VGIC_NR_PRIVATE_IRQS)
2094 vgic_bitmap_set_irq_val(&dist->irq_cfg,
2104 kvm_vgic_destroy(kvm);
2109 static int init_vgic_model(struct kvm *kvm, int type)
2112 case KVM_DEV_TYPE_ARM_VGIC_V2:
2113 vgic_v2_init_emulation(kvm);
2115 #ifdef CONFIG_ARM_GIC_V3
2116 case KVM_DEV_TYPE_ARM_VGIC_V3:
2117 vgic_v3_init_emulation(kvm);
2124 if (atomic_read(&kvm->online_vcpus) > kvm->arch.max_vcpus)
2131 * kvm_vgic_early_init - Earliest possible vgic initialization stage
2133 * No memory allocation should be performed here, only static init.
2135 void kvm_vgic_early_init(struct kvm *kvm)
2137 spin_lock_init(&kvm->arch.vgic.lock);
2138 spin_lock_init(&kvm->arch.vgic.irq_phys_map_lock);
2139 INIT_LIST_HEAD(&kvm->arch.vgic.irq_phys_map_list);
2142 int kvm_vgic_create(struct kvm *kvm, u32 type)
2144 int i, vcpu_lock_idx = -1, ret;
2145 struct kvm_vcpu *vcpu;
2147 mutex_lock(&kvm->lock);
2149 if (irqchip_in_kernel(kvm)) {
2155 * This function is also called by the KVM_CREATE_IRQCHIP handler,
2156 * which had no chance yet to check the availability of the GICv2
2157 * emulation. So check this here again. KVM_CREATE_DEVICE does
2158 * the proper checks already.
2160 if (type == KVM_DEV_TYPE_ARM_VGIC_V2 && !vgic->can_emulate_gicv2) {
2166 * Any time a vcpu is run, vcpu_load is called which tries to grab the
2167 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
2168 * that no other VCPUs are run while we create the vgic.
2171 kvm_for_each_vcpu(i, vcpu, kvm) {
2172 if (!mutex_trylock(&vcpu->mutex))
2177 kvm_for_each_vcpu(i, vcpu, kvm) {
2178 if (vcpu->arch.has_run_once)
2183 ret = init_vgic_model(kvm, type);
2187 kvm->arch.vgic.in_kernel = true;
2188 kvm->arch.vgic.vgic_model = type;
2189 kvm->arch.vgic.vctrl_base = vgic->vctrl_base;
2190 kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
2191 kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
2192 kvm->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF;
2195 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
2196 vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
2197 mutex_unlock(&vcpu->mutex);
2201 mutex_unlock(&kvm->lock);
2205 static int vgic_ioaddr_overlap(struct kvm *kvm)
2207 phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
2208 phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
2210 if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
2212 if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
2213 (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
2218 static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
2219 phys_addr_t addr, phys_addr_t size)
2223 if (addr & ~KVM_PHYS_MASK)
2226 if (addr & (SZ_4K - 1))
2229 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
2231 if (addr + size < addr)
2235 ret = vgic_ioaddr_overlap(kvm);
2237 *ioaddr = VGIC_ADDR_UNDEF;
2243 * kvm_vgic_addr - set or get vgic VM base addresses
2244 * @kvm: pointer to the vm struct
2245 * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX
2246 * @addr: pointer to address value
2247 * @write: if true set the address in the VM address space, if false read the
2250 * Set or get the vgic base addresses for the distributor and the virtual CPU
2251 * interface in the VM physical address space. These addresses are properties
2252 * of the emulated core/SoC and therefore user space initially knows this
2255 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
2258 struct vgic_dist *vgic = &kvm->arch.vgic;
2260 phys_addr_t *addr_ptr, block_size;
2261 phys_addr_t alignment;
2263 mutex_lock(&kvm->lock);
2265 case KVM_VGIC_V2_ADDR_TYPE_DIST:
2266 type_needed = KVM_DEV_TYPE_ARM_VGIC_V2;
2267 addr_ptr = &vgic->vgic_dist_base;
2268 block_size = KVM_VGIC_V2_DIST_SIZE;
2271 case KVM_VGIC_V2_ADDR_TYPE_CPU:
2272 type_needed = KVM_DEV_TYPE_ARM_VGIC_V2;
2273 addr_ptr = &vgic->vgic_cpu_base;
2274 block_size = KVM_VGIC_V2_CPU_SIZE;
2277 #ifdef CONFIG_ARM_GIC_V3
2278 case KVM_VGIC_V3_ADDR_TYPE_DIST:
2279 type_needed = KVM_DEV_TYPE_ARM_VGIC_V3;
2280 addr_ptr = &vgic->vgic_dist_base;
2281 block_size = KVM_VGIC_V3_DIST_SIZE;
2284 case KVM_VGIC_V3_ADDR_TYPE_REDIST:
2285 type_needed = KVM_DEV_TYPE_ARM_VGIC_V3;
2286 addr_ptr = &vgic->vgic_redist_base;
2287 block_size = KVM_VGIC_V3_REDIST_SIZE;
2296 if (vgic->vgic_model != type_needed) {
2302 if (!IS_ALIGNED(*addr, alignment))
2305 r = vgic_ioaddr_assign(kvm, addr_ptr, *addr,
2312 mutex_unlock(&kvm->lock);
2316 int vgic_set_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2320 switch (attr->group) {
2321 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2322 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2324 unsigned long type = (unsigned long)attr->attr;
2326 if (copy_from_user(&addr, uaddr, sizeof(addr)))
2329 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
2330 return (r == -ENODEV) ? -ENXIO : r;
2332 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
2333 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2337 if (get_user(val, uaddr))
2342 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
2343 * - at most 1024 interrupts
2344 * - a multiple of 32 interrupts
2346 if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
2347 val > VGIC_MAX_IRQS ||
2351 mutex_lock(&dev->kvm->lock);
2353 if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_irqs)
2356 dev->kvm->arch.vgic.nr_irqs = val;
2358 mutex_unlock(&dev->kvm->lock);
2362 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
2363 switch (attr->attr) {
2364 case KVM_DEV_ARM_VGIC_CTRL_INIT:
2365 r = vgic_init(dev->kvm);
2375 int vgic_get_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2379 switch (attr->group) {
2380 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2381 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2383 unsigned long type = (unsigned long)attr->attr;
2385 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
2387 return (r == -ENODEV) ? -ENXIO : r;
2389 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2393 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
2394 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2396 r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr);
2405 int vgic_has_attr_regs(const struct vgic_io_range *ranges, phys_addr_t offset)
2407 if (vgic_find_range(ranges, 4, offset))
2413 static void vgic_init_maintenance_interrupt(void *info)
2415 enable_percpu_irq(vgic->maint_irq, 0);
2418 static int vgic_cpu_notify(struct notifier_block *self,
2419 unsigned long action, void *cpu)
2423 case CPU_STARTING_FROZEN:
2424 vgic_init_maintenance_interrupt(NULL);
2427 case CPU_DYING_FROZEN:
2428 disable_percpu_irq(vgic->maint_irq);
2435 static struct notifier_block vgic_cpu_nb = {
2436 .notifier_call = vgic_cpu_notify,
2439 static const struct of_device_id vgic_ids[] = {
2440 { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, },
2441 { .compatible = "arm,cortex-a7-gic", .data = vgic_v2_probe, },
2442 { .compatible = "arm,gic-400", .data = vgic_v2_probe, },
2443 { .compatible = "arm,gic-v3", .data = vgic_v3_probe, },
2447 int kvm_vgic_hyp_init(void)
2449 const struct of_device_id *matched_id;
2450 const int (*vgic_probe)(struct device_node *,const struct vgic_ops **,
2451 const struct vgic_params **);
2452 struct device_node *vgic_node;
2455 vgic_node = of_find_matching_node_and_match(NULL,
2456 vgic_ids, &matched_id);
2458 kvm_err("error: no compatible GIC node found\n");
2462 vgic_probe = matched_id->data;
2463 ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
2467 ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler,
2468 "vgic", kvm_get_running_vcpus());
2470 kvm_err("Cannot register interrupt %d\n", vgic->maint_irq);
2474 ret = __register_cpu_notifier(&vgic_cpu_nb);
2476 kvm_err("Cannot register vgic CPU notifier\n");
2480 on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
2485 free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus());
2489 int kvm_irq_map_gsi(struct kvm *kvm,
2490 struct kvm_kernel_irq_routing_entry *entries,
2496 int kvm_irq_map_chip_pin(struct kvm *kvm, unsigned irqchip, unsigned pin)
2501 int kvm_set_irq(struct kvm *kvm, int irq_source_id,
2502 u32 irq, int level, bool line_status)
2504 unsigned int spi = irq + VGIC_NR_PRIVATE_IRQS;
2506 trace_kvm_set_irq(irq, level, irq_source_id);
2508 BUG_ON(!vgic_initialized(kvm));
2510 return kvm_vgic_inject_irq(kvm, 0, spi, level);
2513 /* MSI not implemented yet */
2514 int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
2515 struct kvm *kvm, int irq_source_id,
2516 int level, bool line_status)