2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/uaccess.h>
29 #include <asm/kvm_emulate.h>
30 #include <asm/kvm_arm.h>
31 #include <asm/kvm_mmu.h>
32 #include <trace/events/kvm.h>
34 #include <kvm/iodev.h>
37 * How the whole thing works (courtesy of Christoffer Dall):
39 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
40 * something is pending on the CPU interface.
41 * - Interrupts that are pending on the distributor are stored on the
42 * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
43 * ioctls and guest mmio ops, and other in-kernel peripherals such as the
45 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
47 * - To calculate the oracle, we need info for each cpu from
48 * compute_pending_for_cpu, which considers:
49 * - PPI: dist->irq_pending & dist->irq_enable
50 * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
51 * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
52 * registers, stored on each vcpu. We only keep one bit of
53 * information per interrupt, making sure that only one vcpu can
54 * accept the interrupt.
55 * - If any of the above state changes, we must recalculate the oracle.
56 * - The same is true when injecting an interrupt, except that we only
57 * consider a single interrupt at a time. The irq_spi_cpu array
58 * contains the target CPU for each SPI.
60 * The handling of level interrupts adds some extra complexity. We
61 * need to track when the interrupt has been EOIed, so we can sample
62 * the 'line' again. This is achieved as such:
64 * - When a level interrupt is moved onto a vcpu, the corresponding
65 * bit in irq_queued is set. As long as this bit is set, the line
66 * will be ignored for further interrupts. The interrupt is injected
67 * into the vcpu with the GICH_LR_EOI bit set (generate a
68 * maintenance interrupt on EOI).
69 * - When the interrupt is EOIed, the maintenance interrupt fires,
70 * and clears the corresponding bit in irq_queued. This allows the
71 * interrupt line to be sampled again.
72 * - Note that level-triggered interrupts can also be set to pending from
73 * writes to GICD_ISPENDRn and lowering the external input line does not
74 * cause the interrupt to become inactive in such a situation.
75 * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
76 * inactive as long as the external input line is held high.
81 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
82 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu);
83 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr);
84 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);
86 static const struct vgic_ops *vgic_ops;
87 static const struct vgic_params *vgic;
89 static void add_sgi_source(struct kvm_vcpu *vcpu, int irq, int source)
91 vcpu->kvm->arch.vgic.vm_ops.add_sgi_source(vcpu, irq, source);
94 static bool queue_sgi(struct kvm_vcpu *vcpu, int irq)
96 return vcpu->kvm->arch.vgic.vm_ops.queue_sgi(vcpu, irq);
99 int kvm_vgic_map_resources(struct kvm *kvm)
101 return kvm->arch.vgic.vm_ops.map_resources(kvm, vgic);
105 * struct vgic_bitmap contains a bitmap made of unsigned longs, but
106 * extracts u32s out of them.
108 * This does not work on 64-bit BE systems, because the bitmap access
109 * will store two consecutive 32-bit words with the higher-addressed
110 * register's bits at the lower index and the lower-addressed register's
111 * bits at the higher index.
113 * Therefore, swizzle the register index when accessing the 32-bit word
114 * registers to access the right register's value.
116 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
117 #define REG_OFFSET_SWIZZLE 1
119 #define REG_OFFSET_SWIZZLE 0
122 static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs)
126 nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS);
128 b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL);
132 b->shared = b->private + nr_cpus;
137 static void vgic_free_bitmap(struct vgic_bitmap *b)
145 * Call this function to convert a u64 value to an unsigned long * bitmask
146 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
148 * Warning: Calling this function may modify *val.
150 static unsigned long *u64_to_bitmask(u64 *val)
152 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
153 *val = (*val >> 32) | (*val << 32);
155 return (unsigned long *)val;
158 u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset)
162 return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE;
164 return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE);
167 static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
170 if (irq < VGIC_NR_PRIVATE_IRQS)
171 return test_bit(irq, x->private + cpuid);
173 return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared);
176 void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
181 if (irq < VGIC_NR_PRIVATE_IRQS) {
182 reg = x->private + cpuid;
185 irq -= VGIC_NR_PRIVATE_IRQS;
194 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
196 return x->private + cpuid;
199 unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
204 static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs)
208 size = nr_cpus * VGIC_NR_PRIVATE_IRQS;
209 size += nr_irqs - VGIC_NR_PRIVATE_IRQS;
211 x->private = kzalloc(size, GFP_KERNEL);
215 x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32);
219 static void vgic_free_bytemap(struct vgic_bytemap *b)
226 u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
230 if (offset < VGIC_NR_PRIVATE_IRQS) {
232 offset += cpuid * VGIC_NR_PRIVATE_IRQS;
235 offset -= VGIC_NR_PRIVATE_IRQS;
238 return reg + (offset / sizeof(u32));
241 #define VGIC_CFG_LEVEL 0
242 #define VGIC_CFG_EDGE 1
244 static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
246 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
249 irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
250 return irq_val == VGIC_CFG_EDGE;
253 static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
255 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
257 return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
260 static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq)
262 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
264 return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq);
267 static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
269 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
271 return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
274 static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq)
276 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
278 vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1);
281 static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq)
283 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
285 vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0);
288 static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
290 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
292 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
295 static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
297 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
299 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
302 static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq)
304 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
306 return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq);
309 static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq)
311 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
313 vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1);
316 static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq)
318 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
320 vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0);
323 static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq)
325 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
327 return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq);
330 static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq)
332 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
334 vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0);
337 static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
339 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
341 return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq);
344 void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq)
346 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
348 vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1);
351 void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq)
353 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
355 vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0);
358 static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
360 if (irq < VGIC_NR_PRIVATE_IRQS)
361 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
363 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
364 vcpu->arch.vgic_cpu.pending_shared);
367 void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
369 if (irq < VGIC_NR_PRIVATE_IRQS)
370 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
372 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
373 vcpu->arch.vgic_cpu.pending_shared);
376 static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq)
378 return !vgic_irq_is_queued(vcpu, irq);
382 * vgic_reg_access - access vgic register
383 * @mmio: pointer to the data describing the mmio access
384 * @reg: pointer to the virtual backing of vgic distributor data
385 * @offset: least significant 2 bits used for word offset
386 * @mode: ACCESS_ mode (see defines above)
388 * Helper to make vgic register access easier using one of the access
389 * modes defined for vgic register access
390 * (read,raz,write-ignored,setbit,clearbit,write)
392 void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
393 phys_addr_t offset, int mode)
395 int word_offset = (offset & 3) * 8;
396 u32 mask = (1UL << (mmio->len * 8)) - 1;
400 * Any alignment fault should have been delivered to the guest
401 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
407 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
411 if (mmio->is_write) {
412 u32 data = mmio_data_read(mmio, mask) << word_offset;
413 switch (ACCESS_WRITE_MASK(mode)) {
414 case ACCESS_WRITE_IGNORED:
417 case ACCESS_WRITE_SETBIT:
421 case ACCESS_WRITE_CLEARBIT:
425 case ACCESS_WRITE_VALUE:
426 regval = (regval & ~(mask << word_offset)) | data;
431 switch (ACCESS_READ_MASK(mode)) {
432 case ACCESS_READ_RAZ:
436 case ACCESS_READ_VALUE:
437 mmio_data_write(mmio, mask, regval >> word_offset);
442 bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
445 vgic_reg_access(mmio, NULL, offset,
446 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
450 bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
451 phys_addr_t offset, int vcpu_id, int access)
454 int mode = ACCESS_READ_VALUE | access;
455 struct kvm_vcpu *target_vcpu = kvm_get_vcpu(kvm, vcpu_id);
457 reg = vgic_bitmap_get_reg(&kvm->arch.vgic.irq_enabled, vcpu_id, offset);
458 vgic_reg_access(mmio, reg, offset, mode);
459 if (mmio->is_write) {
460 if (access & ACCESS_WRITE_CLEARBIT) {
461 if (offset < 4) /* Force SGI enabled */
463 vgic_retire_disabled_irqs(target_vcpu);
465 vgic_update_state(kvm);
472 bool vgic_handle_set_pending_reg(struct kvm *kvm,
473 struct kvm_exit_mmio *mmio,
474 phys_addr_t offset, int vcpu_id)
478 int mode = ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT;
479 struct vgic_dist *dist = &kvm->arch.vgic;
481 reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu_id, offset);
482 level_mask = (~(*reg));
484 /* Mark both level and edge triggered irqs as pending */
485 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset);
487 vgic_reg_access(mmio, reg, offset, mode);
489 if (mmio->is_write) {
490 /* Set the soft-pending flag only for level-triggered irqs */
491 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
493 vgic_reg_access(mmio, reg, offset, mode);
496 /* Ignore writes to SGIs */
499 *reg |= orig & 0xffff;
502 vgic_update_state(kvm);
509 bool vgic_handle_clear_pending_reg(struct kvm *kvm,
510 struct kvm_exit_mmio *mmio,
511 phys_addr_t offset, int vcpu_id)
515 int mode = ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT;
516 struct vgic_dist *dist = &kvm->arch.vgic;
518 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset);
520 vgic_reg_access(mmio, reg, offset, mode);
521 if (mmio->is_write) {
522 /* Re-set level triggered level-active interrupts */
523 level_active = vgic_bitmap_get_reg(&dist->irq_level,
525 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu_id, offset);
526 *reg |= *level_active;
528 /* Ignore writes to SGIs */
531 *reg |= orig & 0xffff;
534 /* Clear soft-pending flags */
535 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
537 vgic_reg_access(mmio, reg, offset, mode);
539 vgic_update_state(kvm);
545 bool vgic_handle_set_active_reg(struct kvm *kvm,
546 struct kvm_exit_mmio *mmio,
547 phys_addr_t offset, int vcpu_id)
550 struct vgic_dist *dist = &kvm->arch.vgic;
552 reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset);
553 vgic_reg_access(mmio, reg, offset,
554 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
556 if (mmio->is_write) {
557 vgic_update_state(kvm);
564 bool vgic_handle_clear_active_reg(struct kvm *kvm,
565 struct kvm_exit_mmio *mmio,
566 phys_addr_t offset, int vcpu_id)
569 struct vgic_dist *dist = &kvm->arch.vgic;
571 reg = vgic_bitmap_get_reg(&dist->irq_active, vcpu_id, offset);
572 vgic_reg_access(mmio, reg, offset,
573 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
575 if (mmio->is_write) {
576 vgic_update_state(kvm);
583 static u32 vgic_cfg_expand(u16 val)
589 * Turn a 16bit value like abcd...mnop into a 32bit word
590 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
592 for (i = 0; i < 16; i++)
593 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
598 static u16 vgic_cfg_compress(u32 val)
604 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
605 * abcd...mnop which is what we really care about.
607 for (i = 0; i < 16; i++)
608 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
614 * The distributor uses 2 bits per IRQ for the CFG register, but the
615 * LSB is always 0. As such, we only keep the upper bit, and use the
616 * two above functions to compress/expand the bits
618 bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio,
628 val = vgic_cfg_expand(val);
629 vgic_reg_access(mmio, &val, offset,
630 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
631 if (mmio->is_write) {
633 *reg = ~0U; /* Force PPIs/SGIs to 1 */
637 val = vgic_cfg_compress(val);
642 *reg &= 0xffff << 16;
651 * vgic_unqueue_irqs - move pending/active IRQs from LRs to the distributor
652 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
654 * Move any IRQs that have already been assigned to LRs back to the
655 * emulated distributor state so that the complete emulated state can be read
656 * from the main emulation structures without investigating the LRs.
658 void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
660 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
663 for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
664 struct vgic_lr lr = vgic_get_lr(vcpu, i);
667 * There are three options for the state bits:
671 * 11: pending and active
673 BUG_ON(!(lr.state & LR_STATE_MASK));
675 /* Reestablish SGI source for pending and active IRQs */
676 if (lr.irq < VGIC_NR_SGIS)
677 add_sgi_source(vcpu, lr.irq, lr.source);
680 * If the LR holds an active (10) or a pending and active (11)
681 * interrupt then move the active state to the
682 * distributor tracking bit.
684 if (lr.state & LR_STATE_ACTIVE) {
685 vgic_irq_set_active(vcpu, lr.irq);
686 lr.state &= ~LR_STATE_ACTIVE;
690 * Reestablish the pending state on the distributor and the
691 * CPU interface. It may have already been pending, but that
692 * is fine, then we are only setting a few bits that were
695 if (lr.state & LR_STATE_PENDING) {
696 vgic_dist_irq_set_pending(vcpu, lr.irq);
697 lr.state &= ~LR_STATE_PENDING;
700 vgic_set_lr(vcpu, i, lr);
703 * Mark the LR as free for other use.
705 BUG_ON(lr.state & LR_STATE_MASK);
706 vgic_retire_lr(i, lr.irq, vcpu);
707 vgic_irq_clear_queued(vcpu, lr.irq);
709 /* Finally update the VGIC state. */
710 vgic_update_state(vcpu->kvm);
715 struct vgic_io_range *vgic_find_range(const struct vgic_io_range *ranges,
716 int len, gpa_t offset)
718 while (ranges->len) {
719 if (offset >= ranges->base &&
720 (offset + len) <= (ranges->base + ranges->len))
728 static bool vgic_validate_access(const struct vgic_dist *dist,
729 const struct vgic_io_range *range,
730 unsigned long offset)
734 if (!range->bits_per_irq)
735 return true; /* Not an irq-based access */
737 irq = offset * 8 / range->bits_per_irq;
738 if (irq >= dist->nr_irqs)
745 * Call the respective handler function for the given range.
746 * We split up any 64 bit accesses into two consecutive 32 bit
747 * handler calls and merge the result afterwards.
748 * We do this in a little endian fashion regardless of the host's
749 * or guest's endianness, because the GIC is always LE and the rest of
750 * the code (vgic_reg_access) also puts it in a LE fashion already.
751 * At this point we have already identified the handle function, so
752 * range points to that one entry and offset is relative to this.
754 static bool call_range_handler(struct kvm_vcpu *vcpu,
755 struct kvm_exit_mmio *mmio,
756 unsigned long offset,
757 const struct vgic_io_range *range)
759 struct kvm_exit_mmio mmio32;
762 if (likely(mmio->len <= 4))
763 return range->handle_mmio(vcpu, mmio, offset);
766 * Any access bigger than 4 bytes (that we currently handle in KVM)
767 * is actually 8 bytes long, caused by a 64-bit access
771 mmio32.is_write = mmio->is_write;
772 mmio32.private = mmio->private;
774 mmio32.phys_addr = mmio->phys_addr + 4;
775 mmio32.data = &((u32 *)mmio->data)[1];
776 ret = range->handle_mmio(vcpu, &mmio32, offset + 4);
778 mmio32.phys_addr = mmio->phys_addr;
779 mmio32.data = &((u32 *)mmio->data)[0];
780 ret |= range->handle_mmio(vcpu, &mmio32, offset);
786 * vgic_handle_mmio_access - handle an in-kernel MMIO access
787 * This is called by the read/write KVM IO device wrappers below.
788 * @vcpu: pointer to the vcpu performing the access
789 * @this: pointer to the KVM IO device in charge
790 * @addr: guest physical address of the access
791 * @len: size of the access
792 * @val: pointer to the data region
793 * @is_write: read or write access
795 * returns true if the MMIO access could be performed
797 static int vgic_handle_mmio_access(struct kvm_vcpu *vcpu,
798 struct kvm_io_device *this, gpa_t addr,
799 int len, void *val, bool is_write)
801 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
802 struct vgic_io_device *iodev = container_of(this,
803 struct vgic_io_device, dev);
804 struct kvm_run *run = vcpu->run;
805 const struct vgic_io_range *range;
806 struct kvm_exit_mmio mmio;
810 offset = addr - iodev->addr;
811 range = vgic_find_range(iodev->reg_ranges, len, offset);
812 if (unlikely(!range || !range->handle_mmio)) {
813 pr_warn("Unhandled access %d %08llx %d\n", is_write, addr, len);
817 mmio.phys_addr = addr;
819 mmio.is_write = is_write;
821 mmio.private = iodev->redist_vcpu;
823 spin_lock(&dist->lock);
824 offset -= range->base;
825 if (vgic_validate_access(dist, range, offset)) {
826 updated_state = call_range_handler(vcpu, &mmio, offset, range);
830 updated_state = false;
832 spin_unlock(&dist->lock);
833 run->mmio.is_write = is_write;
835 run->mmio.phys_addr = addr;
836 memcpy(run->mmio.data, val, len);
838 kvm_handle_mmio_return(vcpu, run);
841 vgic_kick_vcpus(vcpu->kvm);
846 static int vgic_handle_mmio_read(struct kvm_vcpu *vcpu,
847 struct kvm_io_device *this,
848 gpa_t addr, int len, void *val)
850 return vgic_handle_mmio_access(vcpu, this, addr, len, val, false);
853 static int vgic_handle_mmio_write(struct kvm_vcpu *vcpu,
854 struct kvm_io_device *this,
855 gpa_t addr, int len, const void *val)
857 return vgic_handle_mmio_access(vcpu, this, addr, len, (void *)val,
861 struct kvm_io_device_ops vgic_io_ops = {
862 .read = vgic_handle_mmio_read,
863 .write = vgic_handle_mmio_write,
867 * vgic_register_kvm_io_dev - register VGIC register frame on the KVM I/O bus
868 * @kvm: The VM structure pointer
869 * @base: The (guest) base address for the register frame
870 * @len: Length of the register frame window
871 * @ranges: Describing the handler functions for each register
872 * @redist_vcpu_id: The VCPU ID to pass on to the handlers on call
873 * @iodev: Points to memory to be passed on to the handler
875 * @iodev stores the parameters of this function to be usable by the handler
876 * respectively the dispatcher function (since the KVM I/O bus framework lacks
877 * an opaque parameter). Initialization is done in this function, but the
878 * reference should be valid and unique for the whole VGIC lifetime.
879 * If the register frame is not mapped for a specific VCPU, pass -1 to
882 int vgic_register_kvm_io_dev(struct kvm *kvm, gpa_t base, int len,
883 const struct vgic_io_range *ranges,
885 struct vgic_io_device *iodev)
887 struct kvm_vcpu *vcpu = NULL;
890 if (redist_vcpu_id >= 0)
891 vcpu = kvm_get_vcpu(kvm, redist_vcpu_id);
895 iodev->reg_ranges = ranges;
896 iodev->redist_vcpu = vcpu;
898 kvm_iodevice_init(&iodev->dev, &vgic_io_ops);
900 mutex_lock(&kvm->slots_lock);
902 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, base, len,
904 mutex_unlock(&kvm->slots_lock);
906 /* Mark the iodev as invalid if registration fails. */
908 iodev->dev.ops = NULL;
913 static int vgic_nr_shared_irqs(struct vgic_dist *dist)
915 return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS;
918 static int compute_active_for_cpu(struct kvm_vcpu *vcpu)
920 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
921 unsigned long *active, *enabled, *act_percpu, *act_shared;
922 unsigned long active_private, active_shared;
923 int nr_shared = vgic_nr_shared_irqs(dist);
926 vcpu_id = vcpu->vcpu_id;
927 act_percpu = vcpu->arch.vgic_cpu.active_percpu;
928 act_shared = vcpu->arch.vgic_cpu.active_shared;
930 active = vgic_bitmap_get_cpu_map(&dist->irq_active, vcpu_id);
931 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
932 bitmap_and(act_percpu, active, enabled, VGIC_NR_PRIVATE_IRQS);
934 active = vgic_bitmap_get_shared_map(&dist->irq_active);
935 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
936 bitmap_and(act_shared, active, enabled, nr_shared);
937 bitmap_and(act_shared, act_shared,
938 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
941 active_private = find_first_bit(act_percpu, VGIC_NR_PRIVATE_IRQS);
942 active_shared = find_first_bit(act_shared, nr_shared);
944 return (active_private < VGIC_NR_PRIVATE_IRQS ||
945 active_shared < nr_shared);
948 static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
950 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
951 unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
952 unsigned long pending_private, pending_shared;
953 int nr_shared = vgic_nr_shared_irqs(dist);
956 vcpu_id = vcpu->vcpu_id;
957 pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
958 pend_shared = vcpu->arch.vgic_cpu.pending_shared;
960 pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id);
961 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
962 bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
964 pending = vgic_bitmap_get_shared_map(&dist->irq_pending);
965 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
966 bitmap_and(pend_shared, pending, enabled, nr_shared);
967 bitmap_and(pend_shared, pend_shared,
968 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
971 pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
972 pending_shared = find_first_bit(pend_shared, nr_shared);
973 return (pending_private < VGIC_NR_PRIVATE_IRQS ||
974 pending_shared < vgic_nr_shared_irqs(dist));
978 * Update the interrupt state and determine which CPUs have pending
979 * or active interrupts. Must be called with distributor lock held.
981 void vgic_update_state(struct kvm *kvm)
983 struct vgic_dist *dist = &kvm->arch.vgic;
984 struct kvm_vcpu *vcpu;
987 if (!dist->enabled) {
988 set_bit(0, dist->irq_pending_on_cpu);
992 kvm_for_each_vcpu(c, vcpu, kvm) {
993 if (compute_pending_for_cpu(vcpu))
994 set_bit(c, dist->irq_pending_on_cpu);
996 if (compute_active_for_cpu(vcpu))
997 set_bit(c, dist->irq_active_on_cpu);
999 clear_bit(c, dist->irq_active_on_cpu);
1003 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr)
1005 return vgic_ops->get_lr(vcpu, lr);
1008 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr,
1011 vgic_ops->set_lr(vcpu, lr, vlr);
1014 static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1017 vgic_ops->sync_lr_elrsr(vcpu, lr, vlr);
1020 static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu)
1022 return vgic_ops->get_elrsr(vcpu);
1025 static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu)
1027 return vgic_ops->get_eisr(vcpu);
1030 static inline void vgic_clear_eisr(struct kvm_vcpu *vcpu)
1032 vgic_ops->clear_eisr(vcpu);
1035 static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu)
1037 return vgic_ops->get_interrupt_status(vcpu);
1040 static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu)
1042 vgic_ops->enable_underflow(vcpu);
1045 static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu)
1047 vgic_ops->disable_underflow(vcpu);
1050 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1052 vgic_ops->get_vmcr(vcpu, vmcr);
1055 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1057 vgic_ops->set_vmcr(vcpu, vmcr);
1060 static inline void vgic_enable(struct kvm_vcpu *vcpu)
1062 vgic_ops->enable(vcpu);
1065 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu)
1067 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1068 struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr);
1071 vgic_set_lr(vcpu, lr_nr, vlr);
1072 clear_bit(lr_nr, vgic_cpu->lr_used);
1073 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1074 vgic_sync_lr_elrsr(vcpu, lr_nr, vlr);
1078 * An interrupt may have been disabled after being made pending on the
1079 * CPU interface (the classic case is a timer running while we're
1080 * rebooting the guest - the interrupt would kick as soon as the CPU
1081 * interface gets enabled, with deadly consequences).
1083 * The solution is to examine already active LRs, and check the
1084 * interrupt is still enabled. If not, just retire it.
1086 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
1088 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1091 for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) {
1092 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1094 if (!vgic_irq_is_enabled(vcpu, vlr.irq)) {
1095 vgic_retire_lr(lr, vlr.irq, vcpu);
1096 if (vgic_irq_is_queued(vcpu, vlr.irq))
1097 vgic_irq_clear_queued(vcpu, vlr.irq);
1102 static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq,
1103 int lr_nr, struct vgic_lr vlr)
1105 if (vgic_irq_is_active(vcpu, irq)) {
1106 vlr.state |= LR_STATE_ACTIVE;
1107 kvm_debug("Set active, clear distributor: 0x%x\n", vlr.state);
1108 vgic_irq_clear_active(vcpu, irq);
1109 vgic_update_state(vcpu->kvm);
1110 } else if (vgic_dist_irq_is_pending(vcpu, irq)) {
1111 vlr.state |= LR_STATE_PENDING;
1112 kvm_debug("Set pending: 0x%x\n", vlr.state);
1115 if (!vgic_irq_is_edge(vcpu, irq))
1116 vlr.state |= LR_EOI_INT;
1118 vgic_set_lr(vcpu, lr_nr, vlr);
1119 vgic_sync_lr_elrsr(vcpu, lr_nr, vlr);
1123 * Queue an interrupt to a CPU virtual interface. Return true on success,
1124 * or false if it wasn't possible to queue it.
1125 * sgi_source must be zero for any non-SGI interrupts.
1127 bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
1129 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1130 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1134 /* Sanitize the input... */
1135 BUG_ON(sgi_source_id & ~7);
1136 BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
1137 BUG_ON(irq >= dist->nr_irqs);
1139 kvm_debug("Queue IRQ%d\n", irq);
1141 lr = vgic_cpu->vgic_irq_lr_map[irq];
1143 /* Do we have an active interrupt for the same CPUID? */
1144 if (lr != LR_EMPTY) {
1145 vlr = vgic_get_lr(vcpu, lr);
1146 if (vlr.source == sgi_source_id) {
1147 kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq);
1148 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
1149 vgic_queue_irq_to_lr(vcpu, irq, lr, vlr);
1154 /* Try to use another LR for this interrupt */
1155 lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
1157 if (lr >= vgic->nr_lr)
1160 kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
1161 vgic_cpu->vgic_irq_lr_map[irq] = lr;
1162 set_bit(lr, vgic_cpu->lr_used);
1165 vlr.source = sgi_source_id;
1167 vgic_queue_irq_to_lr(vcpu, irq, lr, vlr);
1172 static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
1174 if (!vgic_can_sample_irq(vcpu, irq))
1175 return true; /* level interrupt, already queued */
1177 if (vgic_queue_irq(vcpu, 0, irq)) {
1178 if (vgic_irq_is_edge(vcpu, irq)) {
1179 vgic_dist_irq_clear_pending(vcpu, irq);
1180 vgic_cpu_irq_clear(vcpu, irq);
1182 vgic_irq_set_queued(vcpu, irq);
1192 * Fill the list registers with pending interrupts before running the
1195 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1197 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1198 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1199 unsigned long *pa_percpu, *pa_shared;
1202 int nr_shared = vgic_nr_shared_irqs(dist);
1204 vcpu_id = vcpu->vcpu_id;
1206 pa_percpu = vcpu->arch.vgic_cpu.pend_act_percpu;
1207 pa_shared = vcpu->arch.vgic_cpu.pend_act_shared;
1209 bitmap_or(pa_percpu, vgic_cpu->pending_percpu, vgic_cpu->active_percpu,
1210 VGIC_NR_PRIVATE_IRQS);
1211 bitmap_or(pa_shared, vgic_cpu->pending_shared, vgic_cpu->active_shared,
1214 * We may not have any pending interrupt, or the interrupts
1215 * may have been serviced from another vcpu. In all cases,
1218 if (!kvm_vgic_vcpu_pending_irq(vcpu) && !kvm_vgic_vcpu_active_irq(vcpu))
1222 for_each_set_bit(i, pa_percpu, VGIC_NR_SGIS) {
1223 if (!queue_sgi(vcpu, i))
1228 for_each_set_bit_from(i, pa_percpu, VGIC_NR_PRIVATE_IRQS) {
1229 if (!vgic_queue_hwirq(vcpu, i))
1234 for_each_set_bit(i, pa_shared, nr_shared) {
1235 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
1244 vgic_enable_underflow(vcpu);
1246 vgic_disable_underflow(vcpu);
1248 * We're about to run this VCPU, and we've consumed
1249 * everything the distributor had in store for
1250 * us. Claim we don't have anything pending. We'll
1251 * adjust that if needed while exiting.
1253 clear_bit(vcpu_id, dist->irq_pending_on_cpu);
1257 static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1259 u32 status = vgic_get_interrupt_status(vcpu);
1260 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1261 bool level_pending = false;
1262 struct kvm *kvm = vcpu->kvm;
1264 kvm_debug("STATUS = %08x\n", status);
1266 if (status & INT_STATUS_EOI) {
1268 * Some level interrupts have been EOIed. Clear their
1271 u64 eisr = vgic_get_eisr(vcpu);
1272 unsigned long *eisr_ptr = u64_to_bitmask(&eisr);
1275 for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) {
1276 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1277 WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq));
1279 spin_lock(&dist->lock);
1280 vgic_irq_clear_queued(vcpu, vlr.irq);
1281 WARN_ON(vlr.state & LR_STATE_MASK);
1283 vgic_set_lr(vcpu, lr, vlr);
1286 * If the IRQ was EOIed it was also ACKed and we we
1287 * therefore assume we can clear the soft pending
1288 * state (should it had been set) for this interrupt.
1290 * Note: if the IRQ soft pending state was set after
1291 * the IRQ was acked, it actually shouldn't be
1292 * cleared, but we have no way of knowing that unless
1293 * we start trapping ACKs when the soft-pending state
1296 vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq);
1299 * kvm_notify_acked_irq calls kvm_set_irq()
1300 * to reset the IRQ level. Need to release the
1301 * lock for kvm_set_irq to grab it.
1303 spin_unlock(&dist->lock);
1305 kvm_notify_acked_irq(kvm, 0,
1306 vlr.irq - VGIC_NR_PRIVATE_IRQS);
1307 spin_lock(&dist->lock);
1309 /* Any additional pending interrupt? */
1310 if (vgic_dist_irq_get_level(vcpu, vlr.irq)) {
1311 vgic_cpu_irq_set(vcpu, vlr.irq);
1312 level_pending = true;
1314 vgic_dist_irq_clear_pending(vcpu, vlr.irq);
1315 vgic_cpu_irq_clear(vcpu, vlr.irq);
1318 spin_unlock(&dist->lock);
1321 * Despite being EOIed, the LR may not have
1322 * been marked as empty.
1324 vgic_sync_lr_elrsr(vcpu, lr, vlr);
1328 if (status & INT_STATUS_UNDERFLOW)
1329 vgic_disable_underflow(vcpu);
1332 * In the next iterations of the vcpu loop, if we sync the vgic state
1333 * after flushing it, but before entering the guest (this happens for
1334 * pending signals and vmid rollovers), then make sure we don't pick
1335 * up any old maintenance interrupts here.
1337 vgic_clear_eisr(vcpu);
1339 return level_pending;
1342 /* Sync back the VGIC state after a guest run */
1343 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1345 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1346 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1348 unsigned long *elrsr_ptr;
1352 level_pending = vgic_process_maintenance(vcpu);
1353 elrsr = vgic_get_elrsr(vcpu);
1354 elrsr_ptr = u64_to_bitmask(&elrsr);
1356 /* Clear mappings for empty LRs */
1357 for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) {
1360 if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
1363 vlr = vgic_get_lr(vcpu, lr);
1365 BUG_ON(vlr.irq >= dist->nr_irqs);
1366 vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY;
1369 /* Check if we still have something up our sleeve... */
1370 pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr);
1371 if (level_pending || pending < vgic->nr_lr)
1372 set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
1375 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1377 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1379 if (!irqchip_in_kernel(vcpu->kvm))
1382 spin_lock(&dist->lock);
1383 __kvm_vgic_flush_hwstate(vcpu);
1384 spin_unlock(&dist->lock);
1387 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1389 if (!irqchip_in_kernel(vcpu->kvm))
1392 __kvm_vgic_sync_hwstate(vcpu);
1395 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1397 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1399 if (!irqchip_in_kernel(vcpu->kvm))
1402 return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
1405 int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu)
1407 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1409 if (!irqchip_in_kernel(vcpu->kvm))
1412 return test_bit(vcpu->vcpu_id, dist->irq_active_on_cpu);
1416 void vgic_kick_vcpus(struct kvm *kvm)
1418 struct kvm_vcpu *vcpu;
1422 * We've injected an interrupt, time to find out who deserves
1425 kvm_for_each_vcpu(c, vcpu, kvm) {
1426 if (kvm_vgic_vcpu_pending_irq(vcpu))
1427 kvm_vcpu_kick(vcpu);
1431 static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1433 int edge_triggered = vgic_irq_is_edge(vcpu, irq);
1436 * Only inject an interrupt if:
1437 * - edge triggered and we have a rising edge
1438 * - level triggered and we change level
1440 if (edge_triggered) {
1441 int state = vgic_dist_irq_is_pending(vcpu, irq);
1442 return level > state;
1444 int state = vgic_dist_irq_get_level(vcpu, irq);
1445 return level != state;
1449 static int vgic_update_irq_pending(struct kvm *kvm, int cpuid,
1450 unsigned int irq_num, bool level)
1452 struct vgic_dist *dist = &kvm->arch.vgic;
1453 struct kvm_vcpu *vcpu;
1454 int edge_triggered, level_triggered;
1456 bool ret = true, can_inject = true;
1458 spin_lock(&dist->lock);
1460 vcpu = kvm_get_vcpu(kvm, cpuid);
1461 edge_triggered = vgic_irq_is_edge(vcpu, irq_num);
1462 level_triggered = !edge_triggered;
1464 if (!vgic_validate_injection(vcpu, irq_num, level)) {
1469 if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1470 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1471 if (cpuid == VCPU_NOT_ALLOCATED) {
1472 /* Pretend we use CPU0, and prevent injection */
1476 vcpu = kvm_get_vcpu(kvm, cpuid);
1479 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1482 if (level_triggered)
1483 vgic_dist_irq_set_level(vcpu, irq_num);
1484 vgic_dist_irq_set_pending(vcpu, irq_num);
1486 if (level_triggered) {
1487 vgic_dist_irq_clear_level(vcpu, irq_num);
1488 if (!vgic_dist_irq_soft_pend(vcpu, irq_num))
1489 vgic_dist_irq_clear_pending(vcpu, irq_num);
1496 enabled = vgic_irq_is_enabled(vcpu, irq_num);
1498 if (!enabled || !can_inject) {
1503 if (!vgic_can_sample_irq(vcpu, irq_num)) {
1505 * Level interrupt in progress, will be picked up
1513 vgic_cpu_irq_set(vcpu, irq_num);
1514 set_bit(cpuid, dist->irq_pending_on_cpu);
1518 spin_unlock(&dist->lock);
1520 return ret ? cpuid : -EINVAL;
1524 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1525 * @kvm: The VM structure pointer
1526 * @cpuid: The CPU for PPIs
1527 * @irq_num: The IRQ number that is assigned to the device
1528 * @level: Edge-triggered: true: to trigger the interrupt
1529 * false: to ignore the call
1530 * Level-sensitive true: activates an interrupt
1531 * false: deactivates an interrupt
1533 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1534 * level-sensitive interrupts. You can think of the level parameter as 1
1535 * being HIGH and 0 being LOW and all devices being active-HIGH.
1537 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1543 if (unlikely(!vgic_initialized(kvm))) {
1545 * We only provide the automatic initialization of the VGIC
1546 * for the legacy case of a GICv2. Any other type must
1547 * be explicitly initialized once setup with the respective
1550 if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2) {
1554 mutex_lock(&kvm->lock);
1555 ret = vgic_init(kvm);
1556 mutex_unlock(&kvm->lock);
1562 if (irq_num >= min(kvm->arch.vgic.nr_irqs, 1020))
1565 vcpu_id = vgic_update_irq_pending(kvm, cpuid, irq_num, level);
1567 /* kick the specified vcpu */
1568 kvm_vcpu_kick(kvm_get_vcpu(kvm, vcpu_id));
1575 static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1578 * We cannot rely on the vgic maintenance interrupt to be
1579 * delivered synchronously. This means we can only use it to
1580 * exit the VM, and we perform the handling of EOIed
1581 * interrupts on the exit path (see vgic_process_maintenance).
1586 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
1588 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1590 kfree(vgic_cpu->pending_shared);
1591 kfree(vgic_cpu->active_shared);
1592 kfree(vgic_cpu->pend_act_shared);
1593 kfree(vgic_cpu->vgic_irq_lr_map);
1594 vgic_cpu->pending_shared = NULL;
1595 vgic_cpu->active_shared = NULL;
1596 vgic_cpu->pend_act_shared = NULL;
1597 vgic_cpu->vgic_irq_lr_map = NULL;
1600 static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs)
1602 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1604 int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8;
1605 vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL);
1606 vgic_cpu->active_shared = kzalloc(sz, GFP_KERNEL);
1607 vgic_cpu->pend_act_shared = kzalloc(sz, GFP_KERNEL);
1608 vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL);
1610 if (!vgic_cpu->pending_shared
1611 || !vgic_cpu->active_shared
1612 || !vgic_cpu->pend_act_shared
1613 || !vgic_cpu->vgic_irq_lr_map) {
1614 kvm_vgic_vcpu_destroy(vcpu);
1618 memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs);
1621 * Store the number of LRs per vcpu, so we don't have to go
1622 * all the way to the distributor structure to find out. Only
1623 * assembly code should use this one.
1625 vgic_cpu->nr_lr = vgic->nr_lr;
1631 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
1633 * The host's GIC naturally limits the maximum amount of VCPUs a guest
1636 int kvm_vgic_get_max_vcpus(void)
1638 return vgic->max_gic_vcpus;
1641 void kvm_vgic_destroy(struct kvm *kvm)
1643 struct vgic_dist *dist = &kvm->arch.vgic;
1644 struct kvm_vcpu *vcpu;
1647 kvm_for_each_vcpu(i, vcpu, kvm)
1648 kvm_vgic_vcpu_destroy(vcpu);
1650 vgic_free_bitmap(&dist->irq_enabled);
1651 vgic_free_bitmap(&dist->irq_level);
1652 vgic_free_bitmap(&dist->irq_pending);
1653 vgic_free_bitmap(&dist->irq_soft_pend);
1654 vgic_free_bitmap(&dist->irq_queued);
1655 vgic_free_bitmap(&dist->irq_cfg);
1656 vgic_free_bytemap(&dist->irq_priority);
1657 if (dist->irq_spi_target) {
1658 for (i = 0; i < dist->nr_cpus; i++)
1659 vgic_free_bitmap(&dist->irq_spi_target[i]);
1661 kfree(dist->irq_sgi_sources);
1662 kfree(dist->irq_spi_cpu);
1663 kfree(dist->irq_spi_mpidr);
1664 kfree(dist->irq_spi_target);
1665 kfree(dist->irq_pending_on_cpu);
1666 kfree(dist->irq_active_on_cpu);
1667 dist->irq_sgi_sources = NULL;
1668 dist->irq_spi_cpu = NULL;
1669 dist->irq_spi_target = NULL;
1670 dist->irq_pending_on_cpu = NULL;
1671 dist->irq_active_on_cpu = NULL;
1676 * Allocate and initialize the various data structures. Must be called
1677 * with kvm->lock held!
1679 int vgic_init(struct kvm *kvm)
1681 struct vgic_dist *dist = &kvm->arch.vgic;
1682 struct kvm_vcpu *vcpu;
1683 int nr_cpus, nr_irqs;
1684 int ret, i, vcpu_id;
1686 if (vgic_initialized(kvm))
1689 nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus);
1690 if (!nr_cpus) /* No vcpus? Can't be good... */
1694 * If nobody configured the number of interrupts, use the
1698 dist->nr_irqs = VGIC_NR_IRQS_LEGACY;
1700 nr_irqs = dist->nr_irqs;
1702 ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs);
1703 ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs);
1704 ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs);
1705 ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs);
1706 ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs);
1707 ret |= vgic_init_bitmap(&dist->irq_active, nr_cpus, nr_irqs);
1708 ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs);
1709 ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs);
1714 dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL);
1715 dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL);
1716 dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus,
1718 dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long),
1720 dist->irq_active_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long),
1722 if (!dist->irq_sgi_sources ||
1723 !dist->irq_spi_cpu ||
1724 !dist->irq_spi_target ||
1725 !dist->irq_pending_on_cpu ||
1726 !dist->irq_active_on_cpu) {
1731 for (i = 0; i < nr_cpus; i++)
1732 ret |= vgic_init_bitmap(&dist->irq_spi_target[i],
1738 ret = kvm->arch.vgic.vm_ops.init_model(kvm);
1742 kvm_for_each_vcpu(vcpu_id, vcpu, kvm) {
1743 ret = vgic_vcpu_init_maps(vcpu, nr_irqs);
1745 kvm_err("VGIC: Failed to allocate vcpu memory\n");
1749 for (i = 0; i < dist->nr_irqs; i++) {
1750 if (i < VGIC_NR_PPIS)
1751 vgic_bitmap_set_irq_val(&dist->irq_enabled,
1752 vcpu->vcpu_id, i, 1);
1753 if (i < VGIC_NR_PRIVATE_IRQS)
1754 vgic_bitmap_set_irq_val(&dist->irq_cfg,
1764 kvm_vgic_destroy(kvm);
1769 static int init_vgic_model(struct kvm *kvm, int type)
1772 case KVM_DEV_TYPE_ARM_VGIC_V2:
1773 vgic_v2_init_emulation(kvm);
1775 #ifdef CONFIG_ARM_GIC_V3
1776 case KVM_DEV_TYPE_ARM_VGIC_V3:
1777 vgic_v3_init_emulation(kvm);
1784 if (atomic_read(&kvm->online_vcpus) > kvm->arch.max_vcpus)
1790 int kvm_vgic_create(struct kvm *kvm, u32 type)
1792 int i, vcpu_lock_idx = -1, ret;
1793 struct kvm_vcpu *vcpu;
1795 mutex_lock(&kvm->lock);
1797 if (irqchip_in_kernel(kvm)) {
1803 * This function is also called by the KVM_CREATE_IRQCHIP handler,
1804 * which had no chance yet to check the availability of the GICv2
1805 * emulation. So check this here again. KVM_CREATE_DEVICE does
1806 * the proper checks already.
1808 if (type == KVM_DEV_TYPE_ARM_VGIC_V2 && !vgic->can_emulate_gicv2) {
1814 * Any time a vcpu is run, vcpu_load is called which tries to grab the
1815 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
1816 * that no other VCPUs are run while we create the vgic.
1819 kvm_for_each_vcpu(i, vcpu, kvm) {
1820 if (!mutex_trylock(&vcpu->mutex))
1825 kvm_for_each_vcpu(i, vcpu, kvm) {
1826 if (vcpu->arch.has_run_once)
1831 ret = init_vgic_model(kvm, type);
1835 spin_lock_init(&kvm->arch.vgic.lock);
1836 kvm->arch.vgic.in_kernel = true;
1837 kvm->arch.vgic.vgic_model = type;
1838 kvm->arch.vgic.vctrl_base = vgic->vctrl_base;
1839 kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
1840 kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
1841 kvm->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF;
1844 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
1845 vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
1846 mutex_unlock(&vcpu->mutex);
1850 mutex_unlock(&kvm->lock);
1854 static int vgic_ioaddr_overlap(struct kvm *kvm)
1856 phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
1857 phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
1859 if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
1861 if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
1862 (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
1867 static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
1868 phys_addr_t addr, phys_addr_t size)
1872 if (addr & ~KVM_PHYS_MASK)
1875 if (addr & (SZ_4K - 1))
1878 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
1880 if (addr + size < addr)
1884 ret = vgic_ioaddr_overlap(kvm);
1886 *ioaddr = VGIC_ADDR_UNDEF;
1892 * kvm_vgic_addr - set or get vgic VM base addresses
1893 * @kvm: pointer to the vm struct
1894 * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX
1895 * @addr: pointer to address value
1896 * @write: if true set the address in the VM address space, if false read the
1899 * Set or get the vgic base addresses for the distributor and the virtual CPU
1900 * interface in the VM physical address space. These addresses are properties
1901 * of the emulated core/SoC and therefore user space initially knows this
1904 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
1907 struct vgic_dist *vgic = &kvm->arch.vgic;
1909 phys_addr_t *addr_ptr, block_size;
1910 phys_addr_t alignment;
1912 mutex_lock(&kvm->lock);
1914 case KVM_VGIC_V2_ADDR_TYPE_DIST:
1915 type_needed = KVM_DEV_TYPE_ARM_VGIC_V2;
1916 addr_ptr = &vgic->vgic_dist_base;
1917 block_size = KVM_VGIC_V2_DIST_SIZE;
1920 case KVM_VGIC_V2_ADDR_TYPE_CPU:
1921 type_needed = KVM_DEV_TYPE_ARM_VGIC_V2;
1922 addr_ptr = &vgic->vgic_cpu_base;
1923 block_size = KVM_VGIC_V2_CPU_SIZE;
1926 #ifdef CONFIG_ARM_GIC_V3
1927 case KVM_VGIC_V3_ADDR_TYPE_DIST:
1928 type_needed = KVM_DEV_TYPE_ARM_VGIC_V3;
1929 addr_ptr = &vgic->vgic_dist_base;
1930 block_size = KVM_VGIC_V3_DIST_SIZE;
1933 case KVM_VGIC_V3_ADDR_TYPE_REDIST:
1934 type_needed = KVM_DEV_TYPE_ARM_VGIC_V3;
1935 addr_ptr = &vgic->vgic_redist_base;
1936 block_size = KVM_VGIC_V3_REDIST_SIZE;
1945 if (vgic->vgic_model != type_needed) {
1951 if (!IS_ALIGNED(*addr, alignment))
1954 r = vgic_ioaddr_assign(kvm, addr_ptr, *addr,
1961 mutex_unlock(&kvm->lock);
1965 int vgic_set_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
1969 switch (attr->group) {
1970 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
1971 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
1973 unsigned long type = (unsigned long)attr->attr;
1975 if (copy_from_user(&addr, uaddr, sizeof(addr)))
1978 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
1979 return (r == -ENODEV) ? -ENXIO : r;
1981 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
1982 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
1986 if (get_user(val, uaddr))
1991 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
1992 * - at most 1024 interrupts
1993 * - a multiple of 32 interrupts
1995 if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
1996 val > VGIC_MAX_IRQS ||
2000 mutex_lock(&dev->kvm->lock);
2002 if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_irqs)
2005 dev->kvm->arch.vgic.nr_irqs = val;
2007 mutex_unlock(&dev->kvm->lock);
2011 case KVM_DEV_ARM_VGIC_GRP_CTRL: {
2012 switch (attr->attr) {
2013 case KVM_DEV_ARM_VGIC_CTRL_INIT:
2014 r = vgic_init(dev->kvm);
2024 int vgic_get_common_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2028 switch (attr->group) {
2029 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2030 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2032 unsigned long type = (unsigned long)attr->attr;
2034 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
2036 return (r == -ENODEV) ? -ENXIO : r;
2038 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2042 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
2043 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2045 r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr);
2054 int vgic_has_attr_regs(const struct vgic_io_range *ranges, phys_addr_t offset)
2056 if (vgic_find_range(ranges, 4, offset))
2062 static void vgic_init_maintenance_interrupt(void *info)
2064 enable_percpu_irq(vgic->maint_irq, 0);
2067 static int vgic_cpu_notify(struct notifier_block *self,
2068 unsigned long action, void *cpu)
2072 case CPU_STARTING_FROZEN:
2073 vgic_init_maintenance_interrupt(NULL);
2076 case CPU_DYING_FROZEN:
2077 disable_percpu_irq(vgic->maint_irq);
2084 static struct notifier_block vgic_cpu_nb = {
2085 .notifier_call = vgic_cpu_notify,
2088 static const struct of_device_id vgic_ids[] = {
2089 { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, },
2090 { .compatible = "arm,cortex-a7-gic", .data = vgic_v2_probe, },
2091 { .compatible = "arm,gic-400", .data = vgic_v2_probe, },
2092 { .compatible = "arm,gic-v3", .data = vgic_v3_probe, },
2096 int kvm_vgic_hyp_init(void)
2098 const struct of_device_id *matched_id;
2099 const int (*vgic_probe)(struct device_node *,const struct vgic_ops **,
2100 const struct vgic_params **);
2101 struct device_node *vgic_node;
2104 vgic_node = of_find_matching_node_and_match(NULL,
2105 vgic_ids, &matched_id);
2107 kvm_err("error: no compatible GIC node found\n");
2111 vgic_probe = matched_id->data;
2112 ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
2116 ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler,
2117 "vgic", kvm_get_running_vcpus());
2119 kvm_err("Cannot register interrupt %d\n", vgic->maint_irq);
2123 ret = __register_cpu_notifier(&vgic_cpu_nb);
2125 kvm_err("Cannot register vgic CPU notifier\n");
2129 on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
2134 free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus());
2138 int kvm_irq_map_gsi(struct kvm *kvm,
2139 struct kvm_kernel_irq_routing_entry *entries,
2145 int kvm_irq_map_chip_pin(struct kvm *kvm, unsigned irqchip, unsigned pin)
2150 int kvm_set_irq(struct kvm *kvm, int irq_source_id,
2151 u32 irq, int level, bool line_status)
2153 unsigned int spi = irq + VGIC_NR_PRIVATE_IRQS;
2155 trace_kvm_set_irq(irq, level, irq_source_id);
2157 BUG_ON(!vgic_initialized(kvm));
2159 return kvm_vgic_inject_irq(kvm, 0, spi, level);
2162 /* MSI not implemented yet */
2163 int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
2164 struct kvm *kvm, int irq_source_id,
2165 int level, bool line_status)