2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/uaccess.h>
29 #include <linux/irqchip/arm-gic.h>
31 #include <asm/kvm_emulate.h>
32 #include <asm/kvm_arm.h>
33 #include <asm/kvm_mmu.h>
36 * How the whole thing works (courtesy of Christoffer Dall):
38 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
39 * something is pending
40 * - VGIC pending interrupts are stored on the vgic.irq_state vgic
41 * bitmap (this bitmap is updated by both user land ioctls and guest
42 * mmio ops, and other in-kernel peripherals such as the
43 * arch. timers) and indicate the 'wire' state.
44 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
46 * - To calculate the oracle, we need info for each cpu from
47 * compute_pending_for_cpu, which considers:
48 * - PPI: dist->irq_state & dist->irq_enable
49 * - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
50 * - irq_spi_target is a 'formatted' version of the GICD_ICFGR
51 * registers, stored on each vcpu. We only keep one bit of
52 * information per interrupt, making sure that only one vcpu can
53 * accept the interrupt.
54 * - The same is true when injecting an interrupt, except that we only
55 * consider a single interrupt at a time. The irq_spi_cpu array
56 * contains the target CPU for each SPI.
58 * The handling of level interrupts adds some extra complexity. We
59 * need to track when the interrupt has been EOIed, so we can sample
60 * the 'line' again. This is achieved as such:
62 * - When a level interrupt is moved onto a vcpu, the corresponding
63 * bit in irq_active is set. As long as this bit is set, the line
64 * will be ignored for further interrupts. The interrupt is injected
65 * into the vcpu with the GICH_LR_EOI bit set (generate a
66 * maintenance interrupt on EOI).
67 * - When the interrupt is EOIed, the maintenance interrupt fires,
68 * and clears the corresponding bit in irq_active. This allow the
69 * interrupt line to be sampled again.
72 #define VGIC_ADDR_UNDEF (-1)
73 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
75 #define PRODUCT_ID_KVM 0x4b /* ASCII code K */
76 #define IMPLEMENTER_ARM 0x43b
77 #define GICC_ARCH_VERSION_V2 0x2
79 #define ACCESS_READ_VALUE (1 << 0)
80 #define ACCESS_READ_RAZ (0 << 0)
81 #define ACCESS_READ_MASK(x) ((x) & (1 << 0))
82 #define ACCESS_WRITE_IGNORED (0 << 1)
83 #define ACCESS_WRITE_SETBIT (1 << 1)
84 #define ACCESS_WRITE_CLEARBIT (2 << 1)
85 #define ACCESS_WRITE_VALUE (3 << 1)
86 #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
88 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
89 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu);
90 static void vgic_update_state(struct kvm *kvm);
91 static void vgic_kick_vcpus(struct kvm *kvm);
92 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
93 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr);
94 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);
95 static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
96 static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
98 static const struct vgic_ops *vgic_ops;
99 static const struct vgic_params *vgic;
102 * struct vgic_bitmap contains unions that provide two views of
103 * the same data. In one case it is an array of registers of
104 * u32's, and in the other case it is a bitmap of unsigned
107 * This does not work on 64-bit BE systems, because the bitmap access
108 * will store two consecutive 32-bit words with the higher-addressed
109 * register's bits at the lower index and the lower-addressed register's
110 * bits at the higher index.
112 * Therefore, swizzle the register index when accessing the 32-bit word
113 * registers to access the right register's value.
115 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
116 #define REG_OFFSET_SWIZZLE 1
118 #define REG_OFFSET_SWIZZLE 0
121 static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
122 int cpuid, u32 offset)
126 return x->percpu[cpuid].reg + (offset ^ REG_OFFSET_SWIZZLE);
128 return x->shared.reg + ((offset - 1) ^ REG_OFFSET_SWIZZLE);
131 static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
134 if (irq < VGIC_NR_PRIVATE_IRQS)
135 return test_bit(irq, x->percpu[cpuid].reg_ul);
137 return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
140 static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
145 if (irq < VGIC_NR_PRIVATE_IRQS) {
146 reg = x->percpu[cpuid].reg_ul;
148 reg = x->shared.reg_ul;
149 irq -= VGIC_NR_PRIVATE_IRQS;
158 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
160 if (unlikely(cpuid >= VGIC_MAX_CPUS))
162 return x->percpu[cpuid].reg_ul;
165 static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
167 return x->shared.reg_ul;
170 static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
173 BUG_ON(offset > (VGIC_NR_IRQS / 4));
175 return x->percpu[cpuid] + offset;
177 return x->shared + offset - 8;
180 #define VGIC_CFG_LEVEL 0
181 #define VGIC_CFG_EDGE 1
183 static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
185 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
188 irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
189 return irq_val == VGIC_CFG_EDGE;
192 static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
194 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
196 return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
199 static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
201 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
203 return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
206 static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
208 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
210 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
213 static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
215 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
217 vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
220 static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
222 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
224 return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
227 static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
229 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
231 vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
234 static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
236 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
238 vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
241 static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
243 if (irq < VGIC_NR_PRIVATE_IRQS)
244 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
246 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
247 vcpu->arch.vgic_cpu.pending_shared);
250 static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
252 if (irq < VGIC_NR_PRIVATE_IRQS)
253 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
255 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
256 vcpu->arch.vgic_cpu.pending_shared);
259 static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
261 return le32_to_cpu(*((u32 *)mmio->data)) & mask;
264 static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
266 *((u32 *)mmio->data) = cpu_to_le32(value) & mask;
270 * vgic_reg_access - access vgic register
271 * @mmio: pointer to the data describing the mmio access
272 * @reg: pointer to the virtual backing of vgic distributor data
273 * @offset: least significant 2 bits used for word offset
274 * @mode: ACCESS_ mode (see defines above)
276 * Helper to make vgic register access easier using one of the access
277 * modes defined for vgic register access
278 * (read,raz,write-ignored,setbit,clearbit,write)
280 static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
281 phys_addr_t offset, int mode)
283 int word_offset = (offset & 3) * 8;
284 u32 mask = (1UL << (mmio->len * 8)) - 1;
288 * Any alignment fault should have been delivered to the guest
289 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
295 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
299 if (mmio->is_write) {
300 u32 data = mmio_data_read(mmio, mask) << word_offset;
301 switch (ACCESS_WRITE_MASK(mode)) {
302 case ACCESS_WRITE_IGNORED:
305 case ACCESS_WRITE_SETBIT:
309 case ACCESS_WRITE_CLEARBIT:
313 case ACCESS_WRITE_VALUE:
314 regval = (regval & ~(mask << word_offset)) | data;
319 switch (ACCESS_READ_MASK(mode)) {
320 case ACCESS_READ_RAZ:
324 case ACCESS_READ_VALUE:
325 mmio_data_write(mmio, mask, regval >> word_offset);
330 static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
331 struct kvm_exit_mmio *mmio, phys_addr_t offset)
334 u32 word_offset = offset & 3;
336 switch (offset & ~3) {
337 case 0: /* GICD_CTLR */
338 reg = vcpu->kvm->arch.vgic.enabled;
339 vgic_reg_access(mmio, ®, word_offset,
340 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
341 if (mmio->is_write) {
342 vcpu->kvm->arch.vgic.enabled = reg & 1;
343 vgic_update_state(vcpu->kvm);
348 case 4: /* GICD_TYPER */
349 reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
350 reg |= (VGIC_NR_IRQS >> 5) - 1;
351 vgic_reg_access(mmio, ®, word_offset,
352 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
355 case 8: /* GICD_IIDR */
356 reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
357 vgic_reg_access(mmio, ®, word_offset,
358 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
365 static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
366 struct kvm_exit_mmio *mmio, phys_addr_t offset)
368 vgic_reg_access(mmio, NULL, offset,
369 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
373 static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
374 struct kvm_exit_mmio *mmio,
377 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
378 vcpu->vcpu_id, offset);
379 vgic_reg_access(mmio, reg, offset,
380 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
381 if (mmio->is_write) {
382 vgic_update_state(vcpu->kvm);
389 static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
390 struct kvm_exit_mmio *mmio,
393 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
394 vcpu->vcpu_id, offset);
395 vgic_reg_access(mmio, reg, offset,
396 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
397 if (mmio->is_write) {
398 if (offset < 4) /* Force SGI enabled */
400 vgic_retire_disabled_irqs(vcpu);
401 vgic_update_state(vcpu->kvm);
408 static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
409 struct kvm_exit_mmio *mmio,
412 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
413 vcpu->vcpu_id, offset);
414 vgic_reg_access(mmio, reg, offset,
415 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
416 if (mmio->is_write) {
417 vgic_update_state(vcpu->kvm);
424 static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
425 struct kvm_exit_mmio *mmio,
428 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
429 vcpu->vcpu_id, offset);
430 vgic_reg_access(mmio, reg, offset,
431 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
432 if (mmio->is_write) {
433 vgic_update_state(vcpu->kvm);
440 static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
441 struct kvm_exit_mmio *mmio,
444 u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
445 vcpu->vcpu_id, offset);
446 vgic_reg_access(mmio, reg, offset,
447 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
451 #define GICD_ITARGETSR_SIZE 32
452 #define GICD_CPUTARGETS_BITS 8
453 #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
454 static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
456 struct vgic_dist *dist = &kvm->arch.vgic;
460 irq -= VGIC_NR_PRIVATE_IRQS;
462 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
463 val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8);
468 static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
470 struct vgic_dist *dist = &kvm->arch.vgic;
471 struct kvm_vcpu *vcpu;
476 irq -= VGIC_NR_PRIVATE_IRQS;
479 * Pick the LSB in each byte. This ensures we target exactly
480 * one vcpu per IRQ. If the byte is null, assume we target
483 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
484 int shift = i * GICD_CPUTARGETS_BITS;
485 target = ffs((val >> shift) & 0xffU);
486 target = target ? (target - 1) : 0;
487 dist->irq_spi_cpu[irq + i] = target;
488 kvm_for_each_vcpu(c, vcpu, kvm) {
489 bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
491 set_bit(irq + i, bmap);
493 clear_bit(irq + i, bmap);
498 static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
499 struct kvm_exit_mmio *mmio,
504 /* We treat the banked interrupts targets as read-only */
506 u32 roreg = 1 << vcpu->vcpu_id;
508 roreg |= roreg << 16;
510 vgic_reg_access(mmio, &roreg, offset,
511 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
515 reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
516 vgic_reg_access(mmio, ®, offset,
517 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
518 if (mmio->is_write) {
519 vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
520 vgic_update_state(vcpu->kvm);
527 static u32 vgic_cfg_expand(u16 val)
533 * Turn a 16bit value like abcd...mnop into a 32bit word
534 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
536 for (i = 0; i < 16; i++)
537 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
542 static u16 vgic_cfg_compress(u32 val)
548 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
549 * abcd...mnop which is what we really care about.
551 for (i = 0; i < 16; i++)
552 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
558 * The distributor uses 2 bits per IRQ for the CFG register, but the
559 * LSB is always 0. As such, we only keep the upper bit, and use the
560 * two above functions to compress/expand the bits
562 static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
563 struct kvm_exit_mmio *mmio, phys_addr_t offset)
568 reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
569 vcpu->vcpu_id, offset >> 1);
576 val = vgic_cfg_expand(val);
577 vgic_reg_access(mmio, &val, offset,
578 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
579 if (mmio->is_write) {
581 *reg = ~0U; /* Force PPIs/SGIs to 1 */
585 val = vgic_cfg_compress(val);
590 *reg &= 0xffff << 16;
598 static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
599 struct kvm_exit_mmio *mmio, phys_addr_t offset)
602 vgic_reg_access(mmio, ®, offset,
603 ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
604 if (mmio->is_write) {
605 vgic_dispatch_sgi(vcpu, reg);
606 vgic_update_state(vcpu->kvm);
614 * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
615 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
617 * Move any pending IRQs that have already been assigned to LRs back to the
618 * emulated distributor state so that the complete emulated state can be read
619 * from the main emulation structures without investigating the LRs.
621 * Note that IRQs in the active state in the LRs get their pending state moved
622 * to the distributor but the active state stays in the LRs, because we don't
623 * track the active state on the distributor side.
625 static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
627 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
628 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
629 int vcpu_id = vcpu->vcpu_id;
632 for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
633 struct vgic_lr lr = vgic_get_lr(vcpu, i);
636 * There are three options for the state bits:
640 * 11: pending and active
642 * If the LR holds only an active interrupt (not pending) then
643 * just leave it alone.
645 if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE)
649 * Reestablish the pending state on the distributor and the
650 * CPU interface. It may have already been pending, but that
651 * is fine, then we are only setting a few bits that were
654 vgic_dist_irq_set(vcpu, lr.irq);
655 if (lr.irq < VGIC_NR_SGIS)
656 dist->irq_sgi_sources[vcpu_id][lr.irq] |= 1 << lr.source;
657 lr.state &= ~LR_STATE_PENDING;
658 vgic_set_lr(vcpu, i, lr);
661 * If there's no state left on the LR (it could still be
662 * active), then the LR does not hold any useful info and can
663 * be marked as free for other use.
665 if (!(lr.state & LR_STATE_MASK))
666 vgic_retire_lr(i, lr.irq, vcpu);
668 /* Finally update the VGIC state. */
669 vgic_update_state(vcpu->kvm);
673 /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
674 static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
675 struct kvm_exit_mmio *mmio,
678 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
680 int min_sgi = (offset & ~0x3) * 4;
681 int max_sgi = min_sgi + 3;
682 int vcpu_id = vcpu->vcpu_id;
685 /* Copy source SGIs from distributor side */
686 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
687 int shift = 8 * (sgi - min_sgi);
688 reg |= (u32)dist->irq_sgi_sources[vcpu_id][sgi] << shift;
691 mmio_data_write(mmio, ~0, reg);
695 static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
696 struct kvm_exit_mmio *mmio,
697 phys_addr_t offset, bool set)
699 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
701 int min_sgi = (offset & ~0x3) * 4;
702 int max_sgi = min_sgi + 3;
703 int vcpu_id = vcpu->vcpu_id;
705 bool updated = false;
707 reg = mmio_data_read(mmio, ~0);
709 /* Clear pending SGIs on the distributor */
710 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
711 u8 mask = reg >> (8 * (sgi - min_sgi));
713 if ((dist->irq_sgi_sources[vcpu_id][sgi] & mask) != mask)
715 dist->irq_sgi_sources[vcpu_id][sgi] |= mask;
717 if (dist->irq_sgi_sources[vcpu_id][sgi] & mask)
719 dist->irq_sgi_sources[vcpu_id][sgi] &= ~mask;
724 vgic_update_state(vcpu->kvm);
729 static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu,
730 struct kvm_exit_mmio *mmio,
734 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
736 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true);
739 static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
740 struct kvm_exit_mmio *mmio,
744 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
746 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false);
750 * I would have liked to use the kvm_bus_io_*() API instead, but it
751 * cannot cope with banked registers (only the VM pointer is passed
752 * around, and we need the vcpu). One of these days, someone please
758 bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
762 static const struct mmio_range vgic_dist_ranges[] = {
764 .base = GIC_DIST_CTRL,
766 .handle_mmio = handle_mmio_misc,
769 .base = GIC_DIST_IGROUP,
770 .len = VGIC_NR_IRQS / 8,
771 .handle_mmio = handle_mmio_raz_wi,
774 .base = GIC_DIST_ENABLE_SET,
775 .len = VGIC_NR_IRQS / 8,
776 .handle_mmio = handle_mmio_set_enable_reg,
779 .base = GIC_DIST_ENABLE_CLEAR,
780 .len = VGIC_NR_IRQS / 8,
781 .handle_mmio = handle_mmio_clear_enable_reg,
784 .base = GIC_DIST_PENDING_SET,
785 .len = VGIC_NR_IRQS / 8,
786 .handle_mmio = handle_mmio_set_pending_reg,
789 .base = GIC_DIST_PENDING_CLEAR,
790 .len = VGIC_NR_IRQS / 8,
791 .handle_mmio = handle_mmio_clear_pending_reg,
794 .base = GIC_DIST_ACTIVE_SET,
795 .len = VGIC_NR_IRQS / 8,
796 .handle_mmio = handle_mmio_raz_wi,
799 .base = GIC_DIST_ACTIVE_CLEAR,
800 .len = VGIC_NR_IRQS / 8,
801 .handle_mmio = handle_mmio_raz_wi,
804 .base = GIC_DIST_PRI,
806 .handle_mmio = handle_mmio_priority_reg,
809 .base = GIC_DIST_TARGET,
811 .handle_mmio = handle_mmio_target_reg,
814 .base = GIC_DIST_CONFIG,
815 .len = VGIC_NR_IRQS / 4,
816 .handle_mmio = handle_mmio_cfg_reg,
819 .base = GIC_DIST_SOFTINT,
821 .handle_mmio = handle_mmio_sgi_reg,
824 .base = GIC_DIST_SGI_PENDING_CLEAR,
826 .handle_mmio = handle_mmio_sgi_clear,
829 .base = GIC_DIST_SGI_PENDING_SET,
831 .handle_mmio = handle_mmio_sgi_set,
837 struct mmio_range *find_matching_range(const struct mmio_range *ranges,
838 struct kvm_exit_mmio *mmio,
841 const struct mmio_range *r = ranges;
844 if (offset >= r->base &&
845 (offset + mmio->len) <= (r->base + r->len))
854 * vgic_handle_mmio - handle an in-kernel MMIO access
855 * @vcpu: pointer to the vcpu performing the access
856 * @run: pointer to the kvm_run structure
857 * @mmio: pointer to the data describing the access
859 * returns true if the MMIO access has been performed in kernel space,
860 * and false if it needs to be emulated in user space.
862 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
863 struct kvm_exit_mmio *mmio)
865 const struct mmio_range *range;
866 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
867 unsigned long base = dist->vgic_dist_base;
869 unsigned long offset;
871 if (!irqchip_in_kernel(vcpu->kvm) ||
872 mmio->phys_addr < base ||
873 (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
876 /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
878 kvm_inject_dabt(vcpu, mmio->phys_addr);
882 offset = mmio->phys_addr - base;
883 range = find_matching_range(vgic_dist_ranges, mmio, offset);
884 if (unlikely(!range || !range->handle_mmio)) {
885 pr_warn("Unhandled access %d %08llx %d\n",
886 mmio->is_write, mmio->phys_addr, mmio->len);
890 spin_lock(&vcpu->kvm->arch.vgic.lock);
891 offset = mmio->phys_addr - range->base - base;
892 updated_state = range->handle_mmio(vcpu, mmio, offset);
893 spin_unlock(&vcpu->kvm->arch.vgic.lock);
894 kvm_prepare_mmio(run, mmio);
895 kvm_handle_mmio_return(vcpu, run);
898 vgic_kick_vcpus(vcpu->kvm);
903 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
905 struct kvm *kvm = vcpu->kvm;
906 struct vgic_dist *dist = &kvm->arch.vgic;
907 int nrcpus = atomic_read(&kvm->online_vcpus);
909 int sgi, mode, c, vcpu_id;
911 vcpu_id = vcpu->vcpu_id;
914 target_cpus = (reg >> 16) & 0xff;
915 mode = (reg >> 24) & 3;
924 target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
928 target_cpus = 1 << vcpu_id;
932 kvm_for_each_vcpu(c, vcpu, kvm) {
933 if (target_cpus & 1) {
934 /* Flag the SGI as pending */
935 vgic_dist_irq_set(vcpu, sgi);
936 dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
937 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
944 static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
946 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
947 unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
948 unsigned long pending_private, pending_shared;
951 vcpu_id = vcpu->vcpu_id;
952 pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
953 pend_shared = vcpu->arch.vgic_cpu.pending_shared;
955 pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
956 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
957 bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
959 pending = vgic_bitmap_get_shared_map(&dist->irq_state);
960 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
961 bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
962 bitmap_and(pend_shared, pend_shared,
963 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
964 VGIC_NR_SHARED_IRQS);
966 pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
967 pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
968 return (pending_private < VGIC_NR_PRIVATE_IRQS ||
969 pending_shared < VGIC_NR_SHARED_IRQS);
973 * Update the interrupt state and determine which CPUs have pending
974 * interrupts. Must be called with distributor lock held.
976 static void vgic_update_state(struct kvm *kvm)
978 struct vgic_dist *dist = &kvm->arch.vgic;
979 struct kvm_vcpu *vcpu;
982 if (!dist->enabled) {
983 set_bit(0, &dist->irq_pending_on_cpu);
987 kvm_for_each_vcpu(c, vcpu, kvm) {
988 if (compute_pending_for_cpu(vcpu)) {
989 pr_debug("CPU%d has pending interrupts\n", c);
990 set_bit(c, &dist->irq_pending_on_cpu);
995 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr)
997 return vgic_ops->get_lr(vcpu, lr);
1000 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr,
1003 vgic_ops->set_lr(vcpu, lr, vlr);
1006 static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1009 vgic_ops->sync_lr_elrsr(vcpu, lr, vlr);
1012 static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu)
1014 return vgic_ops->get_elrsr(vcpu);
1017 static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu)
1019 return vgic_ops->get_eisr(vcpu);
1022 static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu)
1024 return vgic_ops->get_interrupt_status(vcpu);
1027 static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu)
1029 vgic_ops->enable_underflow(vcpu);
1032 static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu)
1034 vgic_ops->disable_underflow(vcpu);
1037 static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1039 vgic_ops->get_vmcr(vcpu, vmcr);
1042 static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1044 vgic_ops->set_vmcr(vcpu, vmcr);
1047 static inline void vgic_enable(struct kvm_vcpu *vcpu)
1049 vgic_ops->enable(vcpu);
1052 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu)
1054 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1055 struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr);
1058 vgic_set_lr(vcpu, lr_nr, vlr);
1059 clear_bit(lr_nr, vgic_cpu->lr_used);
1060 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1064 * An interrupt may have been disabled after being made pending on the
1065 * CPU interface (the classic case is a timer running while we're
1066 * rebooting the guest - the interrupt would kick as soon as the CPU
1067 * interface gets enabled, with deadly consequences).
1069 * The solution is to examine already active LRs, and check the
1070 * interrupt is still enabled. If not, just retire it.
1072 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
1074 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1077 for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) {
1078 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1080 if (!vgic_irq_is_enabled(vcpu, vlr.irq)) {
1081 vgic_retire_lr(lr, vlr.irq, vcpu);
1082 if (vgic_irq_is_active(vcpu, vlr.irq))
1083 vgic_irq_clear_active(vcpu, vlr.irq);
1089 * Queue an interrupt to a CPU virtual interface. Return true on success,
1090 * or false if it wasn't possible to queue it.
1092 static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
1094 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1098 /* Sanitize the input... */
1099 BUG_ON(sgi_source_id & ~7);
1100 BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
1101 BUG_ON(irq >= VGIC_NR_IRQS);
1103 kvm_debug("Queue IRQ%d\n", irq);
1105 lr = vgic_cpu->vgic_irq_lr_map[irq];
1107 /* Do we have an active interrupt for the same CPUID? */
1108 if (lr != LR_EMPTY) {
1109 vlr = vgic_get_lr(vcpu, lr);
1110 if (vlr.source == sgi_source_id) {
1111 kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq);
1112 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
1113 vlr.state |= LR_STATE_PENDING;
1114 vgic_set_lr(vcpu, lr, vlr);
1119 /* Try to use another LR for this interrupt */
1120 lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
1122 if (lr >= vgic->nr_lr)
1125 kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
1126 vgic_cpu->vgic_irq_lr_map[irq] = lr;
1127 set_bit(lr, vgic_cpu->lr_used);
1130 vlr.source = sgi_source_id;
1131 vlr.state = LR_STATE_PENDING;
1132 if (!vgic_irq_is_edge(vcpu, irq))
1133 vlr.state |= LR_EOI_INT;
1135 vgic_set_lr(vcpu, lr, vlr);
1140 static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
1142 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1143 unsigned long sources;
1144 int vcpu_id = vcpu->vcpu_id;
1147 sources = dist->irq_sgi_sources[vcpu_id][irq];
1149 for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
1150 if (vgic_queue_irq(vcpu, c, irq))
1151 clear_bit(c, &sources);
1154 dist->irq_sgi_sources[vcpu_id][irq] = sources;
1157 * If the sources bitmap has been cleared it means that we
1158 * could queue all the SGIs onto link registers (see the
1159 * clear_bit above), and therefore we are done with them in
1160 * our emulated gic and can get rid of them.
1163 vgic_dist_irq_clear(vcpu, irq);
1164 vgic_cpu_irq_clear(vcpu, irq);
1171 static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
1173 if (vgic_irq_is_active(vcpu, irq))
1174 return true; /* level interrupt, already queued */
1176 if (vgic_queue_irq(vcpu, 0, irq)) {
1177 if (vgic_irq_is_edge(vcpu, irq)) {
1178 vgic_dist_irq_clear(vcpu, irq);
1179 vgic_cpu_irq_clear(vcpu, irq);
1181 vgic_irq_set_active(vcpu, irq);
1191 * Fill the list registers with pending interrupts before running the
1194 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1196 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1197 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1201 vcpu_id = vcpu->vcpu_id;
1204 * We may not have any pending interrupt, or the interrupts
1205 * may have been serviced from another vcpu. In all cases,
1208 if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
1209 pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
1214 for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
1215 if (!vgic_queue_sgi(vcpu, i))
1220 for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
1221 if (!vgic_queue_hwirq(vcpu, i))
1226 for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
1227 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
1233 vgic_enable_underflow(vcpu);
1235 vgic_disable_underflow(vcpu);
1237 * We're about to run this VCPU, and we've consumed
1238 * everything the distributor had in store for
1239 * us. Claim we don't have anything pending. We'll
1240 * adjust that if needed while exiting.
1242 clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
1246 static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1248 u32 status = vgic_get_interrupt_status(vcpu);
1249 bool level_pending = false;
1251 kvm_debug("STATUS = %08x\n", status);
1253 if (status & INT_STATUS_EOI) {
1255 * Some level interrupts have been EOIed. Clear their
1258 u64 eisr = vgic_get_eisr(vcpu);
1259 unsigned long *eisr_ptr = (unsigned long *)&eisr;
1262 for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) {
1263 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1265 vgic_irq_clear_active(vcpu, vlr.irq);
1266 WARN_ON(vlr.state & LR_STATE_MASK);
1268 vgic_set_lr(vcpu, lr, vlr);
1270 /* Any additional pending interrupt? */
1271 if (vgic_dist_irq_is_pending(vcpu, vlr.irq)) {
1272 vgic_cpu_irq_set(vcpu, vlr.irq);
1273 level_pending = true;
1275 vgic_cpu_irq_clear(vcpu, vlr.irq);
1279 * Despite being EOIed, the LR may not have
1280 * been marked as empty.
1282 vgic_sync_lr_elrsr(vcpu, lr, vlr);
1286 if (status & INT_STATUS_UNDERFLOW)
1287 vgic_disable_underflow(vcpu);
1289 return level_pending;
1293 * Sync back the VGIC state after a guest run. The distributor lock is
1294 * needed so we don't get preempted in the middle of the state processing.
1296 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1298 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1299 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1301 unsigned long *elrsr_ptr;
1305 level_pending = vgic_process_maintenance(vcpu);
1306 elrsr = vgic_get_elrsr(vcpu);
1307 elrsr_ptr = (unsigned long *)&elrsr;
1309 /* Clear mappings for empty LRs */
1310 for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) {
1313 if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
1316 vlr = vgic_get_lr(vcpu, lr);
1318 BUG_ON(vlr.irq >= VGIC_NR_IRQS);
1319 vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY;
1322 /* Check if we still have something up our sleeve... */
1323 pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr);
1324 if (level_pending || pending < vgic->nr_lr)
1325 set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1328 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1330 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1332 if (!irqchip_in_kernel(vcpu->kvm))
1335 spin_lock(&dist->lock);
1336 __kvm_vgic_flush_hwstate(vcpu);
1337 spin_unlock(&dist->lock);
1340 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1342 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1344 if (!irqchip_in_kernel(vcpu->kvm))
1347 spin_lock(&dist->lock);
1348 __kvm_vgic_sync_hwstate(vcpu);
1349 spin_unlock(&dist->lock);
1352 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1354 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1356 if (!irqchip_in_kernel(vcpu->kvm))
1359 return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
1362 static void vgic_kick_vcpus(struct kvm *kvm)
1364 struct kvm_vcpu *vcpu;
1368 * We've injected an interrupt, time to find out who deserves
1371 kvm_for_each_vcpu(c, vcpu, kvm) {
1372 if (kvm_vgic_vcpu_pending_irq(vcpu))
1373 kvm_vcpu_kick(vcpu);
1377 static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1379 int is_edge = vgic_irq_is_edge(vcpu, irq);
1380 int state = vgic_dist_irq_is_pending(vcpu, irq);
1383 * Only inject an interrupt if:
1384 * - edge triggered and we have a rising edge
1385 * - level triggered and we change level
1388 return level > state;
1390 return level != state;
1393 static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
1394 unsigned int irq_num, bool level)
1396 struct vgic_dist *dist = &kvm->arch.vgic;
1397 struct kvm_vcpu *vcpu;
1398 int is_edge, is_level;
1402 spin_lock(&dist->lock);
1404 vcpu = kvm_get_vcpu(kvm, cpuid);
1405 is_edge = vgic_irq_is_edge(vcpu, irq_num);
1406 is_level = !is_edge;
1408 if (!vgic_validate_injection(vcpu, irq_num, level)) {
1413 if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1414 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1415 vcpu = kvm_get_vcpu(kvm, cpuid);
1418 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1421 vgic_dist_irq_set(vcpu, irq_num);
1423 vgic_dist_irq_clear(vcpu, irq_num);
1425 enabled = vgic_irq_is_enabled(vcpu, irq_num);
1432 if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
1434 * Level interrupt in progress, will be picked up
1442 vgic_cpu_irq_set(vcpu, irq_num);
1443 set_bit(cpuid, &dist->irq_pending_on_cpu);
1447 spin_unlock(&dist->lock);
1453 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1454 * @kvm: The VM structure pointer
1455 * @cpuid: The CPU for PPIs
1456 * @irq_num: The IRQ number that is assigned to the device
1457 * @level: Edge-triggered: true: to trigger the interrupt
1458 * false: to ignore the call
1459 * Level-sensitive true: activates an interrupt
1460 * false: deactivates an interrupt
1462 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1463 * level-sensitive interrupts. You can think of the level parameter as 1
1464 * being HIGH and 0 being LOW and all devices being active-HIGH.
1466 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1469 if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
1470 vgic_kick_vcpus(kvm);
1475 static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1478 * We cannot rely on the vgic maintenance interrupt to be
1479 * delivered synchronously. This means we can only use it to
1480 * exit the VM, and we perform the handling of EOIed
1481 * interrupts on the exit path (see vgic_process_maintenance).
1487 * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
1488 * @vcpu: pointer to the vcpu struct
1490 * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
1491 * this vcpu and enable the VGIC for this VCPU
1493 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
1495 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1496 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1499 if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
1502 for (i = 0; i < VGIC_NR_IRQS; i++) {
1503 if (i < VGIC_NR_PPIS)
1504 vgic_bitmap_set_irq_val(&dist->irq_enabled,
1505 vcpu->vcpu_id, i, 1);
1506 if (i < VGIC_NR_PRIVATE_IRQS)
1507 vgic_bitmap_set_irq_val(&dist->irq_cfg,
1508 vcpu->vcpu_id, i, VGIC_CFG_EDGE);
1510 vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
1514 * Store the number of LRs per vcpu, so we don't have to go
1515 * all the way to the distributor structure to find out. Only
1516 * assembly code should use this one.
1518 vgic_cpu->nr_lr = vgic->nr_lr;
1525 static void vgic_init_maintenance_interrupt(void *info)
1527 enable_percpu_irq(vgic->maint_irq, 0);
1530 static int vgic_cpu_notify(struct notifier_block *self,
1531 unsigned long action, void *cpu)
1535 case CPU_STARTING_FROZEN:
1536 vgic_init_maintenance_interrupt(NULL);
1539 case CPU_DYING_FROZEN:
1540 disable_percpu_irq(vgic->maint_irq);
1547 static struct notifier_block vgic_cpu_nb = {
1548 .notifier_call = vgic_cpu_notify,
1551 static const struct of_device_id vgic_ids[] = {
1552 { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, },
1553 { .compatible = "arm,gic-v3", .data = vgic_v3_probe, },
1557 int kvm_vgic_hyp_init(void)
1559 const struct of_device_id *matched_id;
1560 int (*vgic_probe)(struct device_node *,const struct vgic_ops **,
1561 const struct vgic_params **);
1562 struct device_node *vgic_node;
1565 vgic_node = of_find_matching_node_and_match(NULL,
1566 vgic_ids, &matched_id);
1568 kvm_err("error: no compatible GIC node found\n");
1572 vgic_probe = matched_id->data;
1573 ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
1577 ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler,
1578 "vgic", kvm_get_running_vcpus());
1580 kvm_err("Cannot register interrupt %d\n", vgic->maint_irq);
1584 ret = __register_cpu_notifier(&vgic_cpu_nb);
1586 kvm_err("Cannot register vgic CPU notifier\n");
1590 /* Callback into for arch code for setup */
1591 vgic_arch_setup(vgic);
1593 on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
1598 free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus());
1603 * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
1604 * @kvm: pointer to the kvm struct
1606 * Map the virtual CPU interface into the VM before running any VCPUs. We
1607 * can't do this at creation time, because user space must first set the
1608 * virtual CPU interface address in the guest physical address space. Also
1609 * initialize the ITARGETSRn regs to 0 on the emulated distributor.
1611 int kvm_vgic_init(struct kvm *kvm)
1615 if (!irqchip_in_kernel(kvm))
1618 mutex_lock(&kvm->lock);
1620 if (vgic_initialized(kvm))
1623 if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
1624 IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
1625 kvm_err("Need to set vgic cpu and dist addresses first\n");
1630 ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
1631 vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE);
1633 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1637 for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
1638 vgic_set_target_reg(kvm, 0, i);
1640 kvm->arch.vgic.ready = true;
1642 mutex_unlock(&kvm->lock);
1646 int kvm_vgic_create(struct kvm *kvm)
1648 int i, vcpu_lock_idx = -1, ret = 0;
1649 struct kvm_vcpu *vcpu;
1651 mutex_lock(&kvm->lock);
1653 if (kvm->arch.vgic.vctrl_base) {
1659 * Any time a vcpu is run, vcpu_load is called which tries to grab the
1660 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
1661 * that no other VCPUs are run while we create the vgic.
1663 kvm_for_each_vcpu(i, vcpu, kvm) {
1664 if (!mutex_trylock(&vcpu->mutex))
1669 kvm_for_each_vcpu(i, vcpu, kvm) {
1670 if (vcpu->arch.has_run_once) {
1676 spin_lock_init(&kvm->arch.vgic.lock);
1677 kvm->arch.vgic.in_kernel = true;
1678 kvm->arch.vgic.vctrl_base = vgic->vctrl_base;
1679 kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
1680 kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
1683 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
1684 vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
1685 mutex_unlock(&vcpu->mutex);
1689 mutex_unlock(&kvm->lock);
1693 static bool vgic_ioaddr_overlap(struct kvm *kvm)
1695 phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
1696 phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
1698 if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
1700 if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
1701 (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
1706 static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
1707 phys_addr_t addr, phys_addr_t size)
1711 if (addr & ~KVM_PHYS_MASK)
1714 if (addr & (SZ_4K - 1))
1717 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
1719 if (addr + size < addr)
1723 ret = vgic_ioaddr_overlap(kvm);
1725 *ioaddr = VGIC_ADDR_UNDEF;
1731 * kvm_vgic_addr - set or get vgic VM base addresses
1732 * @kvm: pointer to the vm struct
1733 * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
1734 * @addr: pointer to address value
1735 * @write: if true set the address in the VM address space, if false read the
1738 * Set or get the vgic base addresses for the distributor and the virtual CPU
1739 * interface in the VM physical address space. These addresses are properties
1740 * of the emulated core/SoC and therefore user space initially knows this
1743 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
1746 struct vgic_dist *vgic = &kvm->arch.vgic;
1748 mutex_lock(&kvm->lock);
1750 case KVM_VGIC_V2_ADDR_TYPE_DIST:
1752 r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
1753 *addr, KVM_VGIC_V2_DIST_SIZE);
1755 *addr = vgic->vgic_dist_base;
1758 case KVM_VGIC_V2_ADDR_TYPE_CPU:
1760 r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
1761 *addr, KVM_VGIC_V2_CPU_SIZE);
1763 *addr = vgic->vgic_cpu_base;
1770 mutex_unlock(&kvm->lock);
1774 static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu,
1775 struct kvm_exit_mmio *mmio, phys_addr_t offset)
1777 bool updated = false;
1778 struct vgic_vmcr vmcr;
1782 vgic_get_vmcr(vcpu, &vmcr);
1784 switch (offset & ~0x3) {
1786 vmcr_field = &vmcr.ctlr;
1788 case GIC_CPU_PRIMASK:
1789 vmcr_field = &vmcr.pmr;
1791 case GIC_CPU_BINPOINT:
1792 vmcr_field = &vmcr.bpr;
1794 case GIC_CPU_ALIAS_BINPOINT:
1795 vmcr_field = &vmcr.abpr;
1801 if (!mmio->is_write) {
1803 mmio_data_write(mmio, ~0, reg);
1805 reg = mmio_data_read(mmio, ~0);
1806 if (reg != *vmcr_field) {
1808 vgic_set_vmcr(vcpu, &vmcr);
1815 static bool handle_mmio_abpr(struct kvm_vcpu *vcpu,
1816 struct kvm_exit_mmio *mmio, phys_addr_t offset)
1818 return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT);
1821 static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu,
1822 struct kvm_exit_mmio *mmio,
1831 reg = (PRODUCT_ID_KVM << 20) |
1832 (GICC_ARCH_VERSION_V2 << 16) |
1833 (IMPLEMENTER_ARM << 0);
1834 mmio_data_write(mmio, ~0, reg);
1839 * CPU Interface Register accesses - these are not accessed by the VM, but by
1840 * user space for saving and restoring VGIC state.
1842 static const struct mmio_range vgic_cpu_ranges[] = {
1844 .base = GIC_CPU_CTRL,
1846 .handle_mmio = handle_cpu_mmio_misc,
1849 .base = GIC_CPU_ALIAS_BINPOINT,
1851 .handle_mmio = handle_mmio_abpr,
1854 .base = GIC_CPU_ACTIVEPRIO,
1856 .handle_mmio = handle_mmio_raz_wi,
1859 .base = GIC_CPU_IDENT,
1861 .handle_mmio = handle_cpu_mmio_ident,
1865 static int vgic_attr_regs_access(struct kvm_device *dev,
1866 struct kvm_device_attr *attr,
1867 u32 *reg, bool is_write)
1869 const struct mmio_range *r = NULL, *ranges;
1872 struct kvm_vcpu *vcpu, *tmp_vcpu;
1873 struct vgic_dist *vgic;
1874 struct kvm_exit_mmio mmio;
1876 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
1877 cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
1878 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
1880 mutex_lock(&dev->kvm->lock);
1882 if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) {
1887 vcpu = kvm_get_vcpu(dev->kvm, cpuid);
1888 vgic = &dev->kvm->arch.vgic;
1891 mmio.is_write = is_write;
1893 mmio_data_write(&mmio, ~0, *reg);
1894 switch (attr->group) {
1895 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
1896 mmio.phys_addr = vgic->vgic_dist_base + offset;
1897 ranges = vgic_dist_ranges;
1899 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
1900 mmio.phys_addr = vgic->vgic_cpu_base + offset;
1901 ranges = vgic_cpu_ranges;
1906 r = find_matching_range(ranges, &mmio, offset);
1908 if (unlikely(!r || !r->handle_mmio)) {
1914 spin_lock(&vgic->lock);
1917 * Ensure that no other VCPU is running by checking the vcpu->cpu
1918 * field. If no other VPCUs are running we can safely access the VGIC
1919 * state, because even if another VPU is run after this point, that
1920 * VCPU will not touch the vgic state, because it will block on
1921 * getting the vgic->lock in kvm_vgic_sync_hwstate().
1923 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) {
1924 if (unlikely(tmp_vcpu->cpu != -1)) {
1926 goto out_vgic_unlock;
1931 * Move all pending IRQs from the LRs on all VCPUs so the pending
1932 * state can be properly represented in the register state accessible
1935 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm)
1936 vgic_unqueue_irqs(tmp_vcpu);
1939 r->handle_mmio(vcpu, &mmio, offset);
1942 *reg = mmio_data_read(&mmio, ~0);
1946 spin_unlock(&vgic->lock);
1948 mutex_unlock(&dev->kvm->lock);
1952 static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
1956 switch (attr->group) {
1957 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
1958 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
1960 unsigned long type = (unsigned long)attr->attr;
1962 if (copy_from_user(&addr, uaddr, sizeof(addr)))
1965 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
1966 return (r == -ENODEV) ? -ENXIO : r;
1969 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
1970 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
1971 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
1974 if (get_user(reg, uaddr))
1977 return vgic_attr_regs_access(dev, attr, ®, true);
1985 static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
1989 switch (attr->group) {
1990 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
1991 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
1993 unsigned long type = (unsigned long)attr->attr;
1995 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
1997 return (r == -ENODEV) ? -ENXIO : r;
1999 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2004 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2005 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2006 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2009 r = vgic_attr_regs_access(dev, attr, ®, false);
2012 r = put_user(reg, uaddr);
2021 static int vgic_has_attr_regs(const struct mmio_range *ranges,
2024 struct kvm_exit_mmio dev_attr_mmio;
2026 dev_attr_mmio.len = 4;
2027 if (find_matching_range(ranges, &dev_attr_mmio, offset))
2033 static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2037 switch (attr->group) {
2038 case KVM_DEV_ARM_VGIC_GRP_ADDR:
2039 switch (attr->attr) {
2040 case KVM_VGIC_V2_ADDR_TYPE_DIST:
2041 case KVM_VGIC_V2_ADDR_TYPE_CPU:
2045 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2046 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2047 return vgic_has_attr_regs(vgic_dist_ranges, offset);
2048 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
2049 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2050 return vgic_has_attr_regs(vgic_cpu_ranges, offset);
2055 static void vgic_destroy(struct kvm_device *dev)
2060 static int vgic_create(struct kvm_device *dev, u32 type)
2062 return kvm_vgic_create(dev->kvm);
2065 struct kvm_device_ops kvm_arm_vgic_v2_ops = {
2066 .name = "kvm-arm-vgic",
2067 .create = vgic_create,
2068 .destroy = vgic_destroy,
2069 .set_attr = vgic_set_attr,
2070 .get_attr = vgic_get_attr,
2071 .has_attr = vgic_has_attr,