2 * Copyright (C) 2001 MandrakeSoft S.A.
7 * http://www.linux-mandrake.com/
8 * http://www.mandrakesoft.com/
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * Yunhong Jiang <yunhong.jiang@intel.com>
25 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
26 * Based on Xen 3.1 code.
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
36 #include <asm/processor.h>
38 #include <asm/current.h>
39 #include <trace/events/kvm.h>
46 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
48 #define ioapic_debug(fmt, arg...)
50 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
52 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
56 unsigned long result = 0;
58 switch (ioapic->ioregsel) {
59 case IOAPIC_REG_VERSION:
60 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
61 | (IOAPIC_VERSION_ID & 0xff));
64 case IOAPIC_REG_APIC_ID:
65 case IOAPIC_REG_ARB_ID:
66 result = ((ioapic->id & 0xf) << 24);
71 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
74 ASSERT(redir_index < IOAPIC_NUM_PINS);
76 redir_content = ioapic->redirtbl[redir_index].bits;
77 result = (ioapic->ioregsel & 0x1) ?
78 (redir_content >> 32) & 0xffffffff :
79 redir_content & 0xffffffff;
87 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
89 union kvm_ioapic_redirect_entry *pent;
92 pent = &ioapic->redirtbl[idx];
94 if (!pent->fields.mask) {
95 injected = ioapic_deliver(ioapic, idx);
96 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
97 pent->fields.remote_irr = 1;
103 static void update_handled_vectors(struct kvm_ioapic *ioapic)
105 DECLARE_BITMAP(handled_vectors, 256);
108 memset(handled_vectors, 0, sizeof(handled_vectors));
109 for (i = 0; i < IOAPIC_NUM_PINS; ++i)
110 __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
111 memcpy(ioapic->handled_vectors, handled_vectors,
112 sizeof(handled_vectors));
116 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
119 bool mask_before, mask_after;
120 union kvm_ioapic_redirect_entry *e;
122 switch (ioapic->ioregsel) {
123 case IOAPIC_REG_VERSION:
124 /* Writes are ignored. */
127 case IOAPIC_REG_APIC_ID:
128 ioapic->id = (val >> 24) & 0xf;
131 case IOAPIC_REG_ARB_ID:
135 index = (ioapic->ioregsel - 0x10) >> 1;
137 ioapic_debug("change redir index %x val %x\n", index, val);
138 if (index >= IOAPIC_NUM_PINS)
140 e = &ioapic->redirtbl[index];
141 mask_before = e->fields.mask;
142 if (ioapic->ioregsel & 1) {
143 e->bits &= 0xffffffff;
144 e->bits |= (u64) val << 32;
146 e->bits &= ~0xffffffffULL;
147 e->bits |= (u32) val;
148 e->fields.remote_irr = 0;
150 update_handled_vectors(ioapic);
151 mask_after = e->fields.mask;
152 if (mask_before != mask_after)
153 kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
154 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
155 && ioapic->irr & (1 << index))
156 ioapic_service(ioapic, index);
161 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
163 union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
164 struct kvm_lapic_irq irqe;
166 ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
167 "vector=%x trig_mode=%x\n",
168 entry->fields.dest, entry->fields.dest_mode,
169 entry->fields.delivery_mode, entry->fields.vector,
170 entry->fields.trig_mode);
172 irqe.dest_id = entry->fields.dest_id;
173 irqe.vector = entry->fields.vector;
174 irqe.dest_mode = entry->fields.dest_mode;
175 irqe.trig_mode = entry->fields.trig_mode;
176 irqe.delivery_mode = entry->fields.delivery_mode << 8;
181 /* Always delivery PIT interrupt to vcpu 0 */
183 irqe.dest_mode = 0; /* Physical mode. */
184 /* need to read apic_id from apic regiest since
185 * it can be rewritten */
186 irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id;
189 return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
192 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
194 u32 old_irr = ioapic->irr;
196 union kvm_ioapic_redirect_entry entry;
199 mutex_lock(&ioapic->lock);
200 if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
201 entry = ioapic->redirtbl[irq];
202 level ^= entry.fields.polarity;
204 ioapic->irr &= ~mask;
206 int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
208 if ((edge && old_irr != ioapic->irr) ||
209 (!edge && !entry.fields.remote_irr))
210 ret = ioapic_service(ioapic, irq);
212 ret = 0; /* report coalesced interrupt */
214 trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
216 mutex_unlock(&ioapic->lock);
221 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
226 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
227 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
229 if (ent->fields.vector != vector)
233 * We are dropping lock while calling ack notifiers because ack
234 * notifier callbacks for assigned devices call into IOAPIC
235 * recursively. Since remote_irr is cleared only after call
236 * to notifiers if the same vector will be delivered while lock
237 * is dropped it will be put into irr and will be delivered
238 * after ack notifier returns.
240 mutex_unlock(&ioapic->lock);
241 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
242 mutex_lock(&ioapic->lock);
244 if (trigger_mode != IOAPIC_LEVEL_TRIG)
247 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
248 ent->fields.remote_irr = 0;
249 if (!ent->fields.mask && (ioapic->irr & (1 << i)))
250 ioapic_service(ioapic, i);
254 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
256 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
259 if (!test_bit(vector, ioapic->handled_vectors))
261 mutex_lock(&ioapic->lock);
262 __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
263 mutex_unlock(&ioapic->lock);
266 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
268 return container_of(dev, struct kvm_ioapic, dev);
271 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
273 return ((addr >= ioapic->base_address &&
274 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
277 static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
280 struct kvm_ioapic *ioapic = to_ioapic(this);
282 if (!ioapic_in_range(ioapic, addr))
285 ioapic_debug("addr %lx\n", (unsigned long)addr);
286 ASSERT(!(addr & 0xf)); /* check alignment */
289 mutex_lock(&ioapic->lock);
291 case IOAPIC_REG_SELECT:
292 result = ioapic->ioregsel;
295 case IOAPIC_REG_WINDOW:
296 result = ioapic_read_indirect(ioapic, addr, len);
303 mutex_unlock(&ioapic->lock);
307 *(u64 *) val = result;
312 memcpy(val, (char *)&result, len);
315 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
320 static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
323 struct kvm_ioapic *ioapic = to_ioapic(this);
325 if (!ioapic_in_range(ioapic, addr))
328 ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
329 (void*)addr, len, val);
330 ASSERT(!(addr & 0xf)); /* check alignment */
332 if (len == 4 || len == 8)
335 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
340 mutex_lock(&ioapic->lock);
342 case IOAPIC_REG_SELECT:
343 ioapic->ioregsel = data;
346 case IOAPIC_REG_WINDOW:
347 ioapic_write_indirect(ioapic, data);
351 __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
358 mutex_unlock(&ioapic->lock);
362 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
366 for (i = 0; i < IOAPIC_NUM_PINS; i++)
367 ioapic->redirtbl[i].fields.mask = 1;
368 ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
369 ioapic->ioregsel = 0;
372 update_handled_vectors(ioapic);
375 static const struct kvm_io_device_ops ioapic_mmio_ops = {
376 .read = ioapic_mmio_read,
377 .write = ioapic_mmio_write,
380 int kvm_ioapic_init(struct kvm *kvm)
382 struct kvm_ioapic *ioapic;
385 ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
388 mutex_init(&ioapic->lock);
389 kvm->arch.vioapic = ioapic;
390 kvm_ioapic_reset(ioapic);
391 kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
393 mutex_lock(&kvm->slots_lock);
394 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
395 mutex_unlock(&kvm->slots_lock);
397 kvm->arch.vioapic = NULL;
404 void kvm_ioapic_destroy(struct kvm *kvm)
406 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
409 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
410 kvm->arch.vioapic = NULL;
415 int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
417 struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
421 mutex_lock(&ioapic->lock);
422 memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
423 mutex_unlock(&ioapic->lock);
427 int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
429 struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
433 mutex_lock(&ioapic->lock);
434 memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
435 update_handled_vectors(ioapic);
436 mutex_unlock(&ioapic->lock);