#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>

#include "skeleton.dtsi"

/ {
	compatible = "rockchip,rk3188";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
		};
	};

	twd-wdt@1013c620 {
		compatible = "arm,cortex-a9-twd-wdt";
		reg = <0x1013c620 0x20>;
		interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	gic: interrupt-controller@1013d000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x1013d000 0x1000>,
		      <0x1013c100 0x0100>;
	};

	L2: cache-controller@10138000 {
		compatible = "arm,pl310-cache";
		reg = <0x10138000 0x1000>;
		cache-unified;
		cache-level = <2>;
		arm,tag-latency = <1 1 1>;
		arm,data-latency = <2 3 1>;
		prefetch-ctrl = <0x70000003>;
		/* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
		power-ctrl = <0x3>;
/*
		(0x1 << 0) |	// Full line of write zero behavior Enabled
		(0x1 << 25) | 	// Round-robin replacement
		(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
		(0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
		(0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
*/
		aux-ctrl = <0x72000001 (~0x72000001)>;
	};

	cpu_axi_bus: cpu_axi_bus@10128000 {
		compatible = "rockchip,cpu_axi_bus";
		reg = <0x10128000 0x8000>;
		qos {
			dmac {
				offset = <0x1000>;
				priority = <0 0>;
			};
			cpu0 {
				offset = <0x2000>;
				priority = <0 0>;
			};
			cpu1r {
				offset = <0x2080>;
				priority = <0 0>;
			};
			cpu1w {
				offset = <0x2100>;
				priority = <0 0>;
			};
			peri {
				offset = <0x4000>;
				priority = <2 2>;
			};
			gpu {
				offset = <0x5000>;
				priority = <2 1>;
			};
			vpu {
				offset = <0x6000>;
			};
			vop0 {
				offset = <0x7000>;
				priority = <3 3>;
			};
			cif0 {
				offset = <0x7080>;
			};
			ipp {
				offset = <0x7100>;
			};
			vop1 {
				offset = <0x7180>;
				priority = <3 3>;
			};
			cif1 {
				offset = <0x7200>;
			};
			rga {
				offset = <0x7280>;
			};
		};
	};

	bootrom@10120000 {
		compatible = "rockchip,bootrom";
		reg = <0x10120000 0x4000>;
	};

	bootram@10080000 {
		compatible = "rockchip,bootram";
		reg = <0x10080000 0x20>; /* 32 bytes */
	};

	sram@10080020 {
		compatible = "mmio-sram";
		reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
		map-exec;
	};

	pmu@20004000 {
		compatible = "rockchip,pmu";
		reg = <0x20004000 0x4000>;
	};

	timer@200380a0 {
		compatible = "rockchip,timer";
		reg = <0x200380a0 0x20>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer@20038000 {
		compatible = "rockchip,timer";
		reg = <0x20038000 0x20>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer@20038020 {
		compatible = "rockchip,timer";
		reg = <0x20038020 0x20>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer@20038060 {
		compatible = "rockchip,timer";
		reg = <0x20038060 0x20>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer@20038080 {
		compatible = "rockchip,timer";
		reg = <0x20038080 0x20>;
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	};

	pinctrl@20008000 {
			compatible = "rockchip,rk3188-pinctrl";
			reg = <0x20008000 0xa0>,
			      <0x20008164 0x1a0>;
			reg-names = "base", "pull";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gpio0: gpio0@0x2000a000 {
				compatible = "rockchip,rk3188-gpio-bank0";
				reg = <0x2000a000 0x100>,
				      <0x20004064 0x8>;
				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
				/*clocks = <&clk_gates8 9>;*/

				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio1: gpio1@0x2003c000 {
				compatible = "rockchip,gpio-bank";
				reg = <0x2003c000 0x100>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				/*clocks = <&clk_gates8 10>;*/

				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio2@2003e000 {
				compatible = "rockchip,gpio-bank";
				reg = <0x2003e000 0x100>;
				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
				/*clocks = <&clk_gates8 11>;*/

				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio3@20080000 {
				compatible = "rockchip,gpio-bank";
				reg = <0x20080000 0x100>;
				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
				/*clocks = <&clk_gates8 12>;*/

				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;
			};

			pcfg_pull_up: pcfg_pull_up {
				bias-pull-up;
			};

			pcfg_pull_down: pcfg_pull_down {
				bias-pull-down;
			};

			pcfg_pull_none: pcfg_pull_none {
				bias-disable;
			};

			uart0 {
				uart0_xfer: uart0-xfer {
					rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart0_cts: uart0-cts {
					rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart0_rts: uart0-rts {
					rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
				};
			};

			uart1 {
				uart1_xfer: uart1-xfer {
					rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart1_cts: uart1-cts {
					rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart1_rts: uart1-rts {
					rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
				};
			};

			uart2 {
				uart2_xfer: uart2-xfer {
					rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
				};
				/* no rts / cts for uart2 */
			};

			uart3 {
				uart3_xfer: uart3-xfer {
					rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart3_cts: uart3-cts {
					rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart3_rts: uart3-rts {
					rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
				};
			};

			sd0 {
				sd0_clk: sd0-clk {
					rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_cmd: sd0-cmd {
					rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_cd: sd0-cd {
					rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_wp: sd0-wp {
					rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_pwr: sd0-pwr {
					rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_bus1: sd0-bus-width1 {
					rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_bus4: sd0-bus-width4 {
					rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
				};
			};

			sd1 {
				sd1_clk: sd1-clk {
					rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_cmd: sd1-cmd {
					rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_cd: sd1-cd {
					rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_wp: sd1-wp {
					rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_bus1: sd1-bus-width1 {
					rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_bus4: sd1-bus-width4 {
					rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
				};
			};
		};


	uart0: serial@10124000 {
		compatible = "rockchip,serial";
		reg = <0x10124000 0x100>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		reg-shift = <2>;
		reg-io-width = <4>;
		id = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
		status = "disabled";
	};

	uart1: serial@10126000 {
		compatible = "rockchip,serial";
		reg = <0x10126000 0x100>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		reg-shift = <2>;
		reg-io-width = <4>;
		id = <1>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
		status = "disabled";
	};

	uart2: serial@20064000 {
		compatible = "rockchip,serial";
		reg = <0x20064000 0x100>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		current-speed = <115200>;
		reg-shift = <2>;
		reg-io-width = <4>;
		id = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		status = "disabled";
	};

	uart3: serial@20068000 {
		compatible = "rockchip,serial";
		reg = <0x20068000 0x100>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		reg-shift = <2>;
		reg-io-width = <4>;
		id = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
		status = "disabled";
	};
};