#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"
#include "rk3228-clocks.dtsi"

/ {
	compatible = "rockchip,rk3228";
	interrupt-parent = <&gic>;

	aliases {
		serial2 = &uart_dbg;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf02>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf03>;
		};
	};

	gic: interrupt-controller@32010000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;
		reg = <0x32011000 0x1000>,
		      <0x32012000 0x1000>;
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	uart_dbg: serial@11030000 {
		compatible = "rockchip,serial";
		reg = <0x11030000 0x100>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&xin24m>, <&xin24m>;
		clock-names = "sclk_uart", "pclk_uart";
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,signal-irq = <159>;
		rockchip,wake-irq = <0>;
		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
		status = "disabled";
	};

	rockchip_clocks_init: clocks-init{
		compatible = "rockchip,clocks-init";
		rockchip,clocks-init-parent =
			<&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
			<&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
			<&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
			<&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
			<&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
			<&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
			<&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
		rockchip,clocks-init-rate =
			<&clk_gpll 600000000>, <&clk_core 700000000>,
			<&clk_cpll 500000000>, <&aclk_bus 250000000>,
			<&hclk_bus 125000000>, <&pclk_bus 62500000>,
			<&aclk_peri 250000000>, <&hclk_peri 125000000>,
			<&pclk_peri 62500000>, <&clk_mac 125000000>,
			<&aclk_iep 250000000>, <&hclk_vio 125000000>,
			<&aclk_rga 250000000>, <&aclk_gpu 250000000>,
			<&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
			<&clk_vdec_cabac 250000000>;
/*
		rockchip,clocks-uboot-has-init =
			<&aclk_vio0>;
*/
	};

	rockchip_clocks_enable: clocks-enable {
		compatible = "rockchip,clocks-enable";
		clocks =
			/*PLL*/
			<&clk_apll>,
			<&clk_dpll>,
			<&clk_gpll>,
			<&clk_cpll>,

			/*PD_CORE*/
			<&clk_core>,
			<&pclk_dbg>,
			<&aclk_core>,
			<&clk_gates4 2>,

			/*PD_BUS*/
			<&aclk_bus>,
			<&hclk_bus>,
			<&pclk_bus>,
			<&clk_gates8 0>,/*aclk_intmem*/
			<&clk_gates8 1>,/*clk_intmem_mbist*/
			<&clk_gates8 2>,/*aclk_dmac_bus*/
			<&clk_gates10 1>,/*g_aclk_bus*/
			<&clk_gates13 9>,/*aclk_gic400*/
			<&clk_gates8 3>,/*hclk_rom*/
			<&clk_gates8 4>,/*pclk_ddrupctl*/
			<&clk_gates8 6>,/*pclk_ddrmon*/
			<&clk_gates9 4>,/*pclk_timer0*/
			<&clk_gates9 5>,/*pclk_stimer*/
			<&clk_gates10 0>,/*pclk_grf*/
			<&clk_gates10 4>,/*pclk_cru*/
			<&clk_gates10 6>,/*pclk_sgrf*/
			<&clk_gates10 3>,/*pclk_ddrphy*/
			<&clk_gates10 9>,/*pclk_phy_noc*/

			/*PD_PERI*/
			<&aclk_peri>,
			<&hclk_peri>,
			<&pclk_peri>,
			<&clk_gates12 0>,/*aclk_peri_noc*/
			<&clk_gates12 1>,/*hclk_peri_noc*/
			<&clk_gates12 2>,/*pclk_peri_noc*/

			<&clk_gates6 5>, /* g_clk_timer0 */
			<&clk_gates6 6>, /* g_clk_timer1 */

			<&clk_gates7 14>, /* g_aclk_gpu */
			<&clk_gates7 15>, /* g_aclk_gpu_noc */

			<&clk_gates1 3>;/*clk_jtag*/
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus";
		interrupt-parent = <&gic>;
		ranges;

		pdma: pdma@110f0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x110f0000 0x4000>;
			clocks = <&clk_gates8 2>;
			clock-names = "apb_pclk";
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
		};
	};
};