; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'b' ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_bclr_b_RES = global <16 x i8> , align 16 define void @llvm_mips_bclr_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_bclr_b_ARG1 %1 = load <16 x i8>* @llvm_mips_bclr_b_ARG2 %2 = tail call <16 x i8> @llvm.mips.bclr.b(<16 x i8> %0, <16 x i8> %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_bclr_b_RES ret void } declare <16 x i8> @llvm.mips.bclr.b(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_bclr_b_test: ; CHECK: ld.b ; CHECK: ld.b ; CHECK: bclr.b ; CHECK: st.b ; CHECK: .size llvm_mips_bclr_b_test ; @llvm_mips_bclr_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_bclr_h_ARG2 = global <8 x i16> , align 16 @llvm_mips_bclr_h_RES = global <8 x i16> , align 16 define void @llvm_mips_bclr_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_bclr_h_ARG1 %1 = load <8 x i16>* @llvm_mips_bclr_h_ARG2 %2 = tail call <8 x i16> @llvm.mips.bclr.h(<8 x i16> %0, <8 x i16> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_bclr_h_RES ret void } declare <8 x i16> @llvm.mips.bclr.h(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_bclr_h_test: ; CHECK: ld.h ; CHECK: ld.h ; CHECK: bclr.h ; CHECK: st.h ; CHECK: .size llvm_mips_bclr_h_test ; @llvm_mips_bclr_w_ARG1 = global <4 x i32> , align 16 @llvm_mips_bclr_w_ARG2 = global <4 x i32> , align 16 @llvm_mips_bclr_w_RES = global <4 x i32> , align 16 define void @llvm_mips_bclr_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_bclr_w_ARG1 %1 = load <4 x i32>* @llvm_mips_bclr_w_ARG2 %2 = tail call <4 x i32> @llvm.mips.bclr.w(<4 x i32> %0, <4 x i32> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_bclr_w_RES ret void } declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_bclr_w_test: ; CHECK: ld.w ; CHECK: ld.w ; CHECK: bclr.w ; CHECK: st.w ; CHECK: .size llvm_mips_bclr_w_test ; @llvm_mips_bclr_d_ARG1 = global <2 x i64> , align 16 @llvm_mips_bclr_d_ARG2 = global <2 x i64> , align 16 @llvm_mips_bclr_d_RES = global <2 x i64> , align 16 define void @llvm_mips_bclr_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_bclr_d_ARG1 %1 = load <2 x i64>* @llvm_mips_bclr_d_ARG2 %2 = tail call <2 x i64> @llvm.mips.bclr.d(<2 x i64> %0, <2 x i64> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_bclr_d_RES ret void } declare <2 x i64> @llvm.mips.bclr.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_bclr_d_test: ; CHECK: ld.d ; CHECK: ld.d ; CHECK: bclr.d ; CHECK: st.d ; CHECK: .size llvm_mips_bclr_d_test ; @llvm_mips_binsl_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_binsl_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_binsl_b_RES = global <16 x i8> , align 16 define void @llvm_mips_binsl_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_binsl_b_ARG1 %1 = load <16 x i8>* @llvm_mips_binsl_b_ARG2 %2 = tail call <16 x i8> @llvm.mips.binsl.b(<16 x i8> %0, <16 x i8> %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_binsl_b_RES ret void } declare <16 x i8> @llvm.mips.binsl.b(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_binsl_b_test: ; CHECK: ld.b ; CHECK: ld.b ; CHECK: binsl.b ; CHECK: st.b ; CHECK: .size llvm_mips_binsl_b_test ; @llvm_mips_binsl_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_binsl_h_ARG2 = global <8 x i16> , align 16 @llvm_mips_binsl_h_RES = global <8 x i16> , align 16 define void @llvm_mips_binsl_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_binsl_h_ARG1 %1 = load <8 x i16>* @llvm_mips_binsl_h_ARG2 %2 = tail call <8 x i16> @llvm.mips.binsl.h(<8 x i16> %0, <8 x i16> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_binsl_h_RES ret void } declare <8 x i16> @llvm.mips.binsl.h(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_binsl_h_test: ; CHECK: ld.h ; CHECK: ld.h ; CHECK: binsl.h ; CHECK: st.h ; CHECK: .size llvm_mips_binsl_h_test ; @llvm_mips_binsl_w_ARG1 = global <4 x i32> , align 16 @llvm_mips_binsl_w_ARG2 = global <4 x i32> , align 16 @llvm_mips_binsl_w_RES = global <4 x i32> , align 16 define void @llvm_mips_binsl_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_binsl_w_ARG1 %1 = load <4 x i32>* @llvm_mips_binsl_w_ARG2 %2 = tail call <4 x i32> @llvm.mips.binsl.w(<4 x i32> %0, <4 x i32> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_binsl_w_RES ret void } declare <4 x i32> @llvm.mips.binsl.w(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_binsl_w_test: ; CHECK: ld.w ; CHECK: ld.w ; CHECK: binsl.w ; CHECK: st.w ; CHECK: .size llvm_mips_binsl_w_test ; @llvm_mips_binsl_d_ARG1 = global <2 x i64> , align 16 @llvm_mips_binsl_d_ARG2 = global <2 x i64> , align 16 @llvm_mips_binsl_d_RES = global <2 x i64> , align 16 define void @llvm_mips_binsl_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_binsl_d_ARG1 %1 = load <2 x i64>* @llvm_mips_binsl_d_ARG2 %2 = tail call <2 x i64> @llvm.mips.binsl.d(<2 x i64> %0, <2 x i64> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_binsl_d_RES ret void } declare <2 x i64> @llvm.mips.binsl.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_binsl_d_test: ; CHECK: ld.d ; CHECK: ld.d ; CHECK: binsl.d ; CHECK: st.d ; CHECK: .size llvm_mips_binsl_d_test ; @llvm_mips_binsr_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_binsr_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_binsr_b_RES = global <16 x i8> , align 16 define void @llvm_mips_binsr_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_binsr_b_ARG1 %1 = load <16 x i8>* @llvm_mips_binsr_b_ARG2 %2 = tail call <16 x i8> @llvm.mips.binsr.b(<16 x i8> %0, <16 x i8> %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_binsr_b_RES ret void } declare <16 x i8> @llvm.mips.binsr.b(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_binsr_b_test: ; CHECK: ld.b ; CHECK: ld.b ; CHECK: binsr.b ; CHECK: st.b ; CHECK: .size llvm_mips_binsr_b_test ; @llvm_mips_binsr_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_binsr_h_ARG2 = global <8 x i16> , align 16 @llvm_mips_binsr_h_RES = global <8 x i16> , align 16 define void @llvm_mips_binsr_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_binsr_h_ARG1 %1 = load <8 x i16>* @llvm_mips_binsr_h_ARG2 %2 = tail call <8 x i16> @llvm.mips.binsr.h(<8 x i16> %0, <8 x i16> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_binsr_h_RES ret void } declare <8 x i16> @llvm.mips.binsr.h(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_binsr_h_test: ; CHECK: ld.h ; CHECK: ld.h ; CHECK: binsr.h ; CHECK: st.h ; CHECK: .size llvm_mips_binsr_h_test ; @llvm_mips_binsr_w_ARG1 = global <4 x i32> , align 16 @llvm_mips_binsr_w_ARG2 = global <4 x i32> , align 16 @llvm_mips_binsr_w_RES = global <4 x i32> , align 16 define void @llvm_mips_binsr_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_binsr_w_ARG1 %1 = load <4 x i32>* @llvm_mips_binsr_w_ARG2 %2 = tail call <4 x i32> @llvm.mips.binsr.w(<4 x i32> %0, <4 x i32> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_binsr_w_RES ret void } declare <4 x i32> @llvm.mips.binsr.w(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_binsr_w_test: ; CHECK: ld.w ; CHECK: ld.w ; CHECK: binsr.w ; CHECK: st.w ; CHECK: .size llvm_mips_binsr_w_test ; @llvm_mips_binsr_d_ARG1 = global <2 x i64> , align 16 @llvm_mips_binsr_d_ARG2 = global <2 x i64> , align 16 @llvm_mips_binsr_d_RES = global <2 x i64> , align 16 define void @llvm_mips_binsr_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_binsr_d_ARG1 %1 = load <2 x i64>* @llvm_mips_binsr_d_ARG2 %2 = tail call <2 x i64> @llvm.mips.binsr.d(<2 x i64> %0, <2 x i64> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_binsr_d_RES ret void } declare <2 x i64> @llvm.mips.binsr.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_binsr_d_test: ; CHECK: ld.d ; CHECK: ld.d ; CHECK: binsr.d ; CHECK: st.d ; CHECK: .size llvm_mips_binsr_d_test ; @llvm_mips_bneg_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bneg_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_bneg_b_RES = global <16 x i8> , align 16 define void @llvm_mips_bneg_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_bneg_b_ARG1 %1 = load <16 x i8>* @llvm_mips_bneg_b_ARG2 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_bneg_b_RES ret void } declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_bneg_b_test: ; CHECK: ld.b ; CHECK: ld.b ; CHECK: bneg.b ; CHECK: st.b ; CHECK: .size llvm_mips_bneg_b_test ; @llvm_mips_bneg_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_bneg_h_ARG2 = global <8 x i16> , align 16 @llvm_mips_bneg_h_RES = global <8 x i16> , align 16 define void @llvm_mips_bneg_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_bneg_h_ARG1 %1 = load <8 x i16>* @llvm_mips_bneg_h_ARG2 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_bneg_h_RES ret void } declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_bneg_h_test: ; CHECK: ld.h ; CHECK: ld.h ; CHECK: bneg.h ; CHECK: st.h ; CHECK: .size llvm_mips_bneg_h_test ; @llvm_mips_bneg_w_ARG1 = global <4 x i32> , align 16 @llvm_mips_bneg_w_ARG2 = global <4 x i32> , align 16 @llvm_mips_bneg_w_RES = global <4 x i32> , align 16 define void @llvm_mips_bneg_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_bneg_w_ARG1 %1 = load <4 x i32>* @llvm_mips_bneg_w_ARG2 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_bneg_w_RES ret void } declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_bneg_w_test: ; CHECK: ld.w ; CHECK: ld.w ; CHECK: bneg.w ; CHECK: st.w ; CHECK: .size llvm_mips_bneg_w_test ; @llvm_mips_bneg_d_ARG1 = global <2 x i64> , align 16 @llvm_mips_bneg_d_ARG2 = global <2 x i64> , align 16 @llvm_mips_bneg_d_RES = global <2 x i64> , align 16 define void @llvm_mips_bneg_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_bneg_d_ARG1 %1 = load <2 x i64>* @llvm_mips_bneg_d_ARG2 %2 = tail call <2 x i64> @llvm.mips.bneg.d(<2 x i64> %0, <2 x i64> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_bneg_d_RES ret void } declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_bneg_d_test: ; CHECK: ld.d ; CHECK: ld.d ; CHECK: bneg.d ; CHECK: st.d ; CHECK: .size llvm_mips_bneg_d_test ; @llvm_mips_bset_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bset_b_ARG2 = global <16 x i8> , align 16 @llvm_mips_bset_b_RES = global <16 x i8> , align 16 define void @llvm_mips_bset_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_bset_b_ARG1 %1 = load <16 x i8>* @llvm_mips_bset_b_ARG2 %2 = tail call <16 x i8> @llvm.mips.bset.b(<16 x i8> %0, <16 x i8> %1) store <16 x i8> %2, <16 x i8>* @llvm_mips_bset_b_RES ret void } declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind ; CHECK: llvm_mips_bset_b_test: ; CHECK: ld.b ; CHECK: ld.b ; CHECK: bset.b ; CHECK: st.b ; CHECK: .size llvm_mips_bset_b_test ; @llvm_mips_bset_h_ARG1 = global <8 x i16> , align 16 @llvm_mips_bset_h_ARG2 = global <8 x i16> , align 16 @llvm_mips_bset_h_RES = global <8 x i16> , align 16 define void @llvm_mips_bset_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_bset_h_ARG1 %1 = load <8 x i16>* @llvm_mips_bset_h_ARG2 %2 = tail call <8 x i16> @llvm.mips.bset.h(<8 x i16> %0, <8 x i16> %1) store <8 x i16> %2, <8 x i16>* @llvm_mips_bset_h_RES ret void } declare <8 x i16> @llvm.mips.bset.h(<8 x i16>, <8 x i16>) nounwind ; CHECK: llvm_mips_bset_h_test: ; CHECK: ld.h ; CHECK: ld.h ; CHECK: bset.h ; CHECK: st.h ; CHECK: .size llvm_mips_bset_h_test ; @llvm_mips_bset_w_ARG1 = global <4 x i32> , align 16 @llvm_mips_bset_w_ARG2 = global <4 x i32> , align 16 @llvm_mips_bset_w_RES = global <4 x i32> , align 16 define void @llvm_mips_bset_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_bset_w_ARG1 %1 = load <4 x i32>* @llvm_mips_bset_w_ARG2 %2 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> %0, <4 x i32> %1) store <4 x i32> %2, <4 x i32>* @llvm_mips_bset_w_RES ret void } declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind ; CHECK: llvm_mips_bset_w_test: ; CHECK: ld.w ; CHECK: ld.w ; CHECK: bset.w ; CHECK: st.w ; CHECK: .size llvm_mips_bset_w_test ; @llvm_mips_bset_d_ARG1 = global <2 x i64> , align 16 @llvm_mips_bset_d_ARG2 = global <2 x i64> , align 16 @llvm_mips_bset_d_RES = global <2 x i64> , align 16 define void @llvm_mips_bset_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_bset_d_ARG1 %1 = load <2 x i64>* @llvm_mips_bset_d_ARG2 %2 = tail call <2 x i64> @llvm.mips.bset.d(<2 x i64> %0, <2 x i64> %1) store <2 x i64> %2, <2 x i64>* @llvm_mips_bset_d_RES ret void } declare <2 x i64> @llvm.mips.bset.d(<2 x i64>, <2 x i64>) nounwind ; CHECK: llvm_mips_bset_d_test: ; CHECK: ld.d ; CHECK: ld.d ; CHECK: bset.d ; CHECK: st.d ; CHECK: .size llvm_mips_bset_d_test ;