Analysing live variables ...
 For BB 0x4c6560(L1Done) :
  Defs: 0x4c65a8(recurse) 0x726cf8 
  In: 0x4c6438(j3) 
  Out: 
 For BB 0x4c63f0(L2Done) :
  Defs: 0x4c6438(j3) 0x4d8120 0x4ddf98 0x727280(PhiCp:) 
  In: 0x4d6478(i3) 0x5ab290(j2) 
  Out: 
 For BB 0x5ab450(L2Body) :
  Defs: 0x4d6398(i2) 0x4d6478(i3) 0x5ab498(wl) 0x726f20 0x726ff8 0x7271c0 
  In: 0x727388(PhiCp:) 0x727490(PhiCp:) 
  Out: 
 For BB 0x4d82a0(L1Header) :
  Defs: 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:) 0x727490(PhiCp:) 
  In: 0x5414e0(j) 0x727280(PhiCp:) 
  Out: 
 For BB 0x501700(Start) :
  Defs: 0x501748(j1) 0x727280(PhiCp:) 
  In: 
  Out: 

 After Backward Pass 0...
 For BB L1Done:
  In: 0x4c6438(j3) 
  Out: 
 For BB L2Done:
  In: 0x4d6478(i3) 0x5ab290(j2) 
  Out: 0x4c6438(j3) 
 For BB L2Body:
  In: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
  Out: 0x4d6478(i3) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
 For BB L1Header:
  In: 0x5414e0(j) 0x727280(PhiCp:) 
  Out: 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
 For BB Start:
  In: 0x5414e0(j) 
  Out: 0x5414e0(j) 0x727280(PhiCp:) 

 After Backward Pass 1...
 For BB L1Done:
  In: 0x4c6438(j3) 
  Out: 
 For BB L2Done:
  In: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 
  Out: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) 
 For BB L2Body:
  In: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
  Out: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
 For BB L1Header:
  In: 0x5414e0(j) 0x727280(PhiCp:) 
  Out: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
 For BB Start:
  In: 0x5414e0(j) 
  Out: 0x5414e0(j) 0x727280(PhiCp:) 
Live Variable Analysis complete!

======For BB Start: Live var sets for instructions======

Live var sets before/after instruction nop
  Before: 0x5414e0(j) 0x727280(PhiCp:) 
  After : 0x5414e0(j) 0x727280(PhiCp:) 

Live var sets before/after instruction ba	%ccreg(val 0x0)	%disp(label L1Header)
  Before: 0x5414e0(j) 0x727280(PhiCp:) 
  After : 0x5414e0(j) 0x727280(PhiCp:) 

Live var sets before/after instruction add	%reg(val j1)	%reg(23)	%reg(val PhiCp:)*
  Before: 0x501748(j1) 0x5414e0(j) 
  After : 0x5414e0(j) 0x727280(PhiCp:) 

Live var sets before/after instruction add	%reg(23)	%reg(23)	%reg(val j1)*
  Before: 0x5414e0(j) 
  After : 0x501748(j1) 0x5414e0(j) 

======For BB L1Header: Live var sets for instructions======

Live var sets before/after instruction nop
  Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
  After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 

Live var sets before/after instruction ba	%ccreg(val 0x0)	%disp(label L2Body)
  Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
  After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 

Live var sets before/after instruction add	%reg(val i1)	%reg(23)	%reg(val PhiCp:)*
  Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:) 
  After : 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 

Live var sets before/after instruction add	%reg(val j)	%reg(23)	%reg(val PhiCp:)*
  Before: 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 
  After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 0x727388(PhiCp:) 

Live var sets before/after instruction add	%reg(23)	%reg(23)	%reg(val i1)*
  Before: 0x5414e0(j) 0x5ab290(j2) 
  After : 0x5414e0(j) 0x5ab290(j2) 0x5ab370(i1) 

Live var sets before/after instruction add	%reg(val PhiCp:)	%reg(23)	%reg(val j2)*
  Before: 0x5414e0(j) 0x727280(PhiCp:) 
  After : 0x5414e0(j) 0x5ab290(j2) 

======For BB L2Body: Live var sets for instructions======

Live var sets before/after instruction nop
  Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
  After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 

Live var sets before/after instruction ba	%ccreg(val 0x0)	%disp(label L2Body)
  Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
  After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 

Live var sets before/after instruction nop
  Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
  After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 

Live var sets before/after instruction be	%ccreg(val 0x726ff8)	%disp(label L2Done)
  Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:) 
  After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 

Live var sets before/after instruction add	%reg(val i3)	%reg(23)	%reg(val PhiCp:)*
  Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 
  After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 0x727490(PhiCp:) 

Live var sets before/after instruction add	%reg(val wl)	%reg(23)	%reg(val PhiCp:)*
  Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8 
  After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x726ff8 0x727388(PhiCp:) 

Live var sets before/after instruction subcc	%reg(val i3)	%reg(val 0x7271c0)	%reg(23)*	%ccreg(val 0x726ff8)*
  Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0 
  After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726ff8 

Live var sets before/after instruction setsw	10	%reg(val 0x7271c0)*
  Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 
  After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x7271c0 

Live var sets before/after instruction add	%reg(val i2)	%reg(val 0x726f20)	%reg(val i3)*
  Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20 
  After : 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 

Live var sets before/after instruction setsw	1	%reg(val 0x726f20)*
  Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 
  After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 0x726f20 

Live var sets before/after instruction add	%reg(val PhiCp:)	%reg(23)	%reg(val wl)*
  Before: 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 
  After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x5ab498(wl) 

Live var sets before/after instruction add	%reg(val PhiCp:)	%reg(23)	%reg(val i2)*
  Before: 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 0x727490(PhiCp:) 
  After : 0x4d6398(i2) 0x5414e0(j) 0x5ab290(j2) 0x727388(PhiCp:) 

======For BB L2Done: Live var sets for instructions======

Live var sets before/after instruction nop
  Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) 
  After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) 

Live var sets before/after instruction ba	%ccreg(val 0x0)	%disp(label L1Header)
  Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) 
  After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) 

Live var sets before/after instruction nop
  Before: 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) 
  After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) 

Live var sets before/after instruction be	%ccreg(val 0x4ddf98)	%disp(label L1Done)
  Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:) 
  After : 0x4c6438(j3) 0x5414e0(j) 0x727280(PhiCp:) 

Live var sets before/after instruction add	%reg(val j3)	%reg(23)	%reg(val PhiCp:)*
  Before: 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 
  After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 0x727280(PhiCp:) 

Live var sets before/after instruction subcc	%reg(val j3)	%reg(val 0x4d8120)	%reg(23)*	%ccreg(val 0x4ddf98)*
  Before: 0x4c6438(j3) 0x4d8120 0x5414e0(j) 
  After : 0x4c6438(j3) 0x4ddf98 0x5414e0(j) 

Live var sets before/after instruction setsw	100	%reg(val 0x4d8120)*
  Before: 0x4c6438(j3) 0x5414e0(j) 
  After : 0x4c6438(j3) 0x4d8120 0x5414e0(j) 

Live var sets before/after instruction add	%reg(val j2)	%reg(val i3)	%reg(val j3)*
  Before: 0x4d6478(i3) 0x5414e0(j) 0x5ab290(j2) 
  After : 0x4c6438(j3) 0x5414e0(j) 

======For BB L1Done: Live var sets for instructions======

Live var sets before/after instruction nop
  Before: 
  After : 

Live var sets before/after instruction jmpl	%reg(22)*	8	%reg(23)	Implicit:0x4c65a8	
  Before: 0x4c65a8(recurse) 
  After : 

Live var sets before/after instruction nop
  Before: 0x4c65a8(recurse) 
  After : 0x4c65a8(recurse) 

Live var sets before/after instruction call	%disp(label LoopTest)	Implicit:0x4c6438	0x4c6438	0x4c65a8*	0x726cf8*	
  Before: 0x4c6438(j3) 
  After : 0x4c65a8(recurse)