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Fix register printing in disassembling of push/pop of segment registers and in/out...
[oota-llvm.git]
/
CREDITS.TXT
diff --git
a/CREDITS.TXT
b/CREDITS.TXT
index 70616202015ea4540e9d51c2fe34f2674909c9c6..f20152796ae1399bdb199bd82e946d00b564dea6 100644
(file)
--- a/
CREDITS.TXT
+++ b/
CREDITS.TXT
@@
-8,6
+8,7
@@
beautification by scripts. The fields are: name (N), email (E), web-address
(W), PGP key ID and fingerprint (P), description (D), and snail-mail address
(S).
(W), PGP key ID and fingerprint (P), description (D), and snail-mail address
(S).
+
N: Vikram Adve
E: vadve@cs.uiuc.edu
W: http://www.cs.uiuc.edu/~vadve/
N: Vikram Adve
E: vadve@cs.uiuc.edu
W: http://www.cs.uiuc.edu/~vadve/
@@
-31,6
+32,10
@@
E: dberlin@dberlin.org
D: ET-Forest implementation.
D: Sparse bitmap
D: ET-Forest implementation.
D: Sparse bitmap
+N: David Blaikie
+E: dblaikie@gmail.com
+D: General bug fixing/fit & finish, mostly in Clang
+
N: Neil Booth
E: neil@daikokuya.co.uk
D: APFloat implementation.
N: Neil Booth
E: neil@daikokuya.co.uk
D: APFloat implementation.
@@
-39,7
+44,7
@@
N: Misha Brukman
E: brukman+llvm@uiuc.edu
W: http://misha.brukman.net
D: Portions of X86 and Sparc JIT compilers, PowerPC backend
E: brukman+llvm@uiuc.edu
W: http://misha.brukman.net
D: Portions of X86 and Sparc JIT compilers, PowerPC backend
-D: Incremental b
yte
code loader
+D: Incremental b
it
code loader
N: Cameron Buschardt
E: buschard@uiuc.edu
N: Cameron Buschardt
E: buschard@uiuc.edu
@@
-240,6
+245,10
@@
E: duraid@octopus.com.au
W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
D: IA64 backend, BigBlock register allocator
W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
D: IA64 backend, BigBlock register allocator
+N: John McCall
+E: rjmccall@apple.com
+D: Clang semantic analysis and IR generation
+
N: Michael McCracken
E: michael.mccracken@gmail.com
D: Line number support for llvmgcc
N: Michael McCracken
E: michael.mccracken@gmail.com
D: Line number support for llvmgcc
@@
-252,6
+261,12
@@
N: Scott Michel
E: scottm@aero.org
D: Added STI Cell SPU backend.
E: scottm@aero.org
D: Added STI Cell SPU backend.
+N: Takumi Nakamura
+E: geek4civic@gmail.com
+E: chapuni@hf.rim.or.jp
+D: Cygwin and MinGW support.
+S: Yokohama, Japan
+
N: Edward O'Callaghan
E: eocallaghan@auroraux.org
W: http://www.auroraux.org
N: Edward O'Callaghan
E: eocallaghan@auroraux.org
W: http://www.auroraux.org
@@
-267,6
+282,8
@@
N: Jakob Stoklund Olesen
E: stoklund@2pi.dk
D: Machine code verifier
D: Blackfin backend
E: stoklund@2pi.dk
D: Machine code verifier
D: Blackfin backend
+D: Fast register allocator
+D: Greedy register allocator
N: Richard Osborne
E: richard@xmos.com
N: Richard Osborne
E: richard@xmos.com
@@
-287,6
+304,10
@@
E: peckw@wesleypeck.com
W: http://wesleypeck.com/
D: MicroBlaze backend
W: http://wesleypeck.com/
D: MicroBlaze backend
+N: Francois Pichet
+E: pichet2000@gmail.com
+D: MSVC support
+
N: Vladimir Prus
W: http://vladimir_prus.blogspot.com
E: ghost@cs.msu.su
N: Vladimir Prus
W: http://vladimir_prus.blogspot.com
E: ghost@cs.msu.su
@@
-298,7
+319,10
@@
D: MSIL backend
N: Duncan Sands
E: baldrick@free.fr
N: Duncan Sands
E: baldrick@free.fr
-D: Ada front-end, exception handling improvements
+D: Ada support in llvm-gcc
+D: Dragonegg plugin
+D: Exception handling improvements
+D: Type legalizer rewrite
N: Ruchira Sasanka
E: sasanka@uiuc.edu
N: Ruchira Sasanka
E: sasanka@uiuc.edu
@@
-319,6
+343,7
@@
D: The `paths' pass
N: Michael J. Spencer
E: bigcheesegs@gmail.com
D: Shepherding Windows COFF support into MC.
N: Michael J. Spencer
E: bigcheesegs@gmail.com
D: Shepherding Windows COFF support into MC.
+D: Lots of Windows stuff.
N: Reid Spencer
E: rspencer@reidspencer.com
N: Reid Spencer
E: rspencer@reidspencer.com