+ bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M";
+ };
+
+ cpuinfo {
+ compatible = "rockchip,cpuinfo";
+ nvmem-cells = <&efuse_id>;
+ nvmem-cell-names = "id";
+ };
+
+ /delete-node/ dmc@ff610000;
+
+ dfi: dfi {
+ compatible = "rockchip,rk3288-dfi";
+ rockchip,pmu = <&pmu>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3288-dmc";
+ devfreq-events = <&dfi>;
+ clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>,
+ <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>,
+ <&cru PCLK_DDRUPCTL1>;
+ clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0",
+ "pclk_phy1", "pclk_upctl1";
+ upthreshold = <55>;
+ downdifferential = <10>;
+ operating-points-v2 = <&dmc_opp_table>;
+ vop-dclk-mode = <0>;
+ min-cpu-freq = <600000>;
+ rockchip,ddr_timing = <&ddr_timing>;
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 396000
+ SYS_STATUS_REBOOT 396000
+ SYS_STATUS_SUSPEND 192000
+ SYS_STATUS_VIDEO_1080P 300000
+ SYS_STATUS_VIDEO_4K 396000
+ SYS_STATUS_PERFORMANCE 528000
+ SYS_STATUS_BOOST 396000
+ SYS_STATUS_DUALVIEW 396000
+ SYS_STATUS_ISP 396000
+ >;
+ auto-min-freq = <396000>;
+ auto-freq-en = <1>;
+ status = "diasbled";
+ };
+
+ dmc_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp-396000000 {
+ opp-hz = /bits/ 64 <396000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp-528000000 {
+ opp-hz = /bits/ 64 <528000000>;
+ opp-microvolt = <1150000>;
+ };
+ };
+
+ reserved-memory {
+ ramoops_mem: ramoops@00000000 {
+ reg = <0x0 0x8000000 0x0 0xF0000>;
+ };
+
+ drm_logo: drm-logo@00000000 {
+ compatible = "rockchip,drm-logo";
+ reg = <0x0 0x0 0x0 0x0>;
+ };
+ };
+
+ ramoops {
+ compatible = "ramoops";
+ record-size = <0x0 0x20000>;
+ console-size = <0x0 0x80000>;
+ ftrace-size = <0x0 0x00000>;
+ pmsg-size = <0x0 0x50000>;
+ memory-region = <&ramoops_mem>;
+ };
+
+ fiq-debugger {
+ compatible = "rockchip,fiq-debugger";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
+ rockchip,serial-id = <2>;
+ rockchip,wake-irq = <0>;
+ rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
+ rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;