+static int pm_pll_pwr_up(u8 pll_id)
+{
+ u32 pllcon0,pllcon1,pllcon2;
+ //enter slowmode
+ cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
+ cru_writel( CRU_W_MSK(PLL_PWR_DN_SHIFT, 0x01), PLL_CONS(pll_id, 1));
+
+ sram_udelay(100);
+
+ pm_pll_wait_lock(pll_id);
+ //return form slow
+ //cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
+ return 0;
+}
+