<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ACLK_BUS>, <&cru ACLK_PERI>,
<&cru HCLK_BUS>, <&cru HCLK_PERI>,
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ACLK_BUS>, <&cru ACLK_PERI>,
<&cru HCLK_BUS>, <&cru HCLK_PERI>,
assigned-clock-rates =
<576000000>, <400000000>,
<300000000>, <300000000>,
<150000000>, <150000000>,
assigned-clock-rates =
<576000000>, <400000000>,
<300000000>, <300000000>,
<150000000>, <150000000>,