+ rkvdec: rkvdec@ff660000 {
+ compatible = "rockchip,rkvdec";
+ rockchip,grf = <&grf>;
+ iommus = <&vdec_mmu>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff660000 0x0 0x400>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
+ <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec",
+ "clk_cabac", "clk_core";
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
+ reset-names = "video_h", "video_a";
+ power-domains = <&power RK3399_PD_VDU>;
+ dev_mode = <2>;
+ name = "rkvdec";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
+
+ vdec_mmu: iommu@ff660480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdec_mmu";
+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_VDU>;
+ #iommu-cells = <0>;
+ };
+
+ iep: iep@ff670000 {
+ compatible = "rockchip,iep";
+ iommu_enabled = <1>;
+ iommus = <&iep_mmu>;
+ reg = <0x0 0xff670000 0x0 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk_iep", "hclk_iep";
+ power-domains = <&power RK3399_PD_IEP>;
+ allocator = <1>;
+ version = <2>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@ff670800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff670800 0x0 0x40>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";