-/* SH7780 PCI Local Registers */
-#define SH7780_PCICR 0x100 /* PCI Control Register */
- #define SH7780_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
- #define SH7780_PCICR_PFCS 0x00000800 /* TRDY/IRDY Enable */
- #define SH7780_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */
- #define SH7780_PCICR_PFE 0x00000200 /* Target Read Single */
- #define SH7780_PCICR_TBS 0x00000100 /* Target Byte Swap */
- #define SH7780_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
- #define SH7780_PCICR_IOCS 0x00000004 /* INTA output assert */
- #define SH7780_PCICR_PRST 0x00000002 /* PCI Reset Assert */
- #define SH7780_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
-#define SH7780_PCILSR0 0x104 /* PCI Local Space Register0 */
-#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
-#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
-#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
-#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
-#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
-#define SH7780_PCIAIR 0x11C /* Error Address Register */
-#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
-#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
-#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
-#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
-#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
-#define SH7780_PCIPINT 0x1CC /* Power Management Int. Register */
-#define SH7780_PCIPINTM 0x1D0 /* Power Management Mask Register */
-#define SH7780_PCIMBR0 0x1E0 /* Memory Bank0 Register */
-#define SH7780_PCIMBMR0 0x1E4 /* Memory Bank0 Mask Register */
-#define SH7780_PCIMBR1 0x1E8 /* Memory Bank1 Register */
-#define SH7780_PCIMBMR1 0x1EC /* Memory Bank1 Mask Register */
-#define SH7780_PCIMBR2 0x1F0 /* Memory Bank2 Register */
-#define SH7780_PCIMBMR2 0x1F4 /* Memory Bank2 Mask Register */
-#define SH7780_PCIIOBR 0x1F8 /* Bank Register */
-#define SH7780_PCIIOBMR 0x1FC /* Bank Mask Register */
+#define SH7780_PCIMBR0 0x1E0
+#define SH7780_PCIMBMR0 0x1E4
+#define SH7780_PCIMBR2 0x1F0
+#define SH7780_PCIMBMR2 0x1F4
+#define SH7780_PCIIOBR 0x1F8
+#define SH7780_PCIIOBMR 0x1FC