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datarace: don't export unrealized race vector
[model-checker.git]
/
cmodelint.cc
diff --git
a/cmodelint.cc
b/cmodelint.cc
index 8919041be4589670d228ad3e3e7b00b7132a5f2b..1632581101e0c5801f8ba14c05d3d12e1fa4c94c 100644
(file)
--- a/
cmodelint.cc
+++ b/
cmodelint.cc
@@
-1,10
+1,11
@@
#include "model.h"
#include "model.h"
+#include "action.h"
#include "cmodelint.h"
#include "cmodelint.h"
+#include "threads-model.h"
/** Performs a read action.*/
uint64_t model_read_action(void * obj, memory_order ord) {
/** Performs a read action.*/
uint64_t model_read_action(void * obj, memory_order ord) {
- model->switch_to_master(new ModelAction(ATOMIC_READ, ord, obj));
- return thread_current()->get_return_value();
+ return model->switch_to_master(new ModelAction(ATOMIC_READ, ord, obj));
}
/** Performs a write action.*/
}
/** Performs a write action.*/
@@
-23,8
+24,7
@@
void model_init_action(void * obj, uint64_t val) {
* a write.
*/
uint64_t model_rmwr_action(void *obj, memory_order ord) {
* a write.
*/
uint64_t model_rmwr_action(void *obj, memory_order ord) {
- model->switch_to_master(new ModelAction(ATOMIC_RMWR, ord, obj));
- return thread_current()->get_return_value();
+ return model->switch_to_master(new ModelAction(ATOMIC_RMWR, ord, obj));
}
/** Performs the write part of a RMW action. */
}
/** Performs the write part of a RMW action. */
@@
-36,3
+36,8
@@
void model_rmw_action(void *obj, memory_order ord, uint64_t val) {
void model_rmwc_action(void *obj, memory_order ord) {
model->switch_to_master(new ModelAction(ATOMIC_RMWC, ord, obj));
}
void model_rmwc_action(void *obj, memory_order ord) {
model->switch_to_master(new ModelAction(ATOMIC_RMWC, ord, obj));
}
+
+/** Issues a fence operation. */
+void model_fence_action(memory_order ord) {
+ model->switch_to_master(new ModelAction(ATOMIC_FENCE, ord, FENCE_LOCATION));
+}