-infrastructure, release 2.0. Here we describe the status of LLVM, including any
-known problems and major improvements from the previous release. All LLVM
+infrastructure, release 2.0. Here we describe the status of LLVM, including
+major improvements from the previous release and any known problems. All LLVM
<p>For more information about LLVM, including information about the latest
release, please check out the <a href="http://llvm.org/">main LLVM
<p>For more information about LLVM, including information about the latest
release, please check out the <a href="http://llvm.org/">main LLVM
href="http://mail.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVM developer's mailing
list</a> is a good place to send them.</p>
href="http://mail.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVM developer's mailing
list</a> is a good place to send them.</p>
this document applies to the <i>next</i> release, not the current one. To see
the release notes for the current or previous releases, see the <a
href="http://llvm.org/releases/">releases page</a>.</p>
this document applies to the <i>next</i> release, not the current one. To see
the release notes for the current or previous releases, see the <a
href="http://llvm.org/releases/">releases page</a>.</p>
configure llvm-gcc on linux are no longer needed, and special hacks to build
large C++ libraries like Qt are not needed.</li>
configure llvm-gcc on linux are no longer needed, and special hacks to build
large C++ libraries like Qt are not needed.</li>
into MSIL (".net") bytecode. This is still fairly early development
with a number of limitations.</li>
into MSIL (".net") bytecode. This is still fairly early development
with a number of limitations.</li>
<ul>
<li>The <a href="WritingAnLLVMPass.html">pass manager</a> has been entirely
rewritten, making it significantly smaller, simpler, and more extensible.
<ul>
<li>The <a href="WritingAnLLVMPass.html">pass manager</a> has been entirely
rewritten, making it significantly smaller, simpler, and more extensible.
- Support has been added to run FunctionPasses interlaced with
- CallGraphSCCPasses, and we now support loop transformations explicitly with
- LoopPass.</li>
-
-<li>The <tt>-scalarrepl</tt> pass can now promote unions containing FP values
- into a register, it can also handle unions of vectors of the same
- size.</li>
+ Support has been added to run <tt>FunctionPass</tt>es interlaced with
+ <tt>CallGraphSCCPass</tt>es, we now support loop transformations
+ explicitly with <tt>LoopPass</tt>, and <tt>ModulePass</tt>es may now use the
+ result of <tt>FunctionPass</tt>es.</li>
<li>LLVM 2.0 includes a new loop rotation pass, which converts "for loops" into
"do/while loops", where the condition is at the bottom of the loop.</li>
<li>LLVM 2.0 includes a new loop rotation pass, which converts "for loops" into
"do/while loops", where the condition is at the bottom of the loop.</li>
-<li>The Loop Strength Reduction pass has been improved, and support added
- for sinking expressions across blocks to reduce register pressure.</li>
+<li>The Loop Strength Reduction pass has been improved, and we now support
+ sinking expressions across blocks to reduce register pressure.</li>
<li>The ImmediateDominator class has also been removed, and clients have been
switched to use DominatorTree instead.</li>
<li>The predicate simplifier pass has been improved, making it able to do
<li>The ImmediateDominator class has also been removed, and clients have been
switched to use DominatorTree instead.</li>
<li>The predicate simplifier pass has been improved, making it able to do
chips that don't have hardware FPUs (e.g. ARM thumb mode).</li>
<li>A new register scavenger has been implemented, which is useful for
chips that don't have hardware FPUs (e.g. ARM thumb mode).</li>
<li>A new register scavenger has been implemented, which is useful for
sparse switches that have dense subregions, and implemented support
for the shift/and trick.</li>
sparse switches that have dense subregions, and implemented support
for the shift/and trick.</li>
-<li>Added support for tracking physreg sub-registers and super-registers
- in the code generator, as well as extensive register
+<li>LLVM now supports tracking physreg sub-registers and super-registers
+ in the code generator, and includes extensive register
the .ll/.bc files, eliminating the 'pointersize/endianness' attributes
in the files (<a href="http://llvm.org/PR761">PR761</a>).</li>
the .ll/.bc files, eliminating the 'pointersize/endianness' attributes
in the files (<a href="http://llvm.org/PR761">PR761</a>).</li>
<li>PIC support for linux/x86 has been added.</li>
<li>The X86 backend now supports the GCC regparm attribute.</li>
<li>LLVM now supports inline asm with multiple constraint letters per operand
<li>PIC support for linux/x86 has been added.</li>
<li>The X86 backend now supports the GCC regparm attribute.</li>
<li>LLVM now supports inline asm with multiple constraint letters per operand
<li>There are major new features, including support for ARM
v4-v6 chips, vfp support, soft float point support, pre/postinc support,
load/store multiple generation, constant pool entry motion (to support
<li>There are major new features, including support for ARM
v4-v6 chips, vfp support, soft float point support, pre/postinc support,
load/store multiple generation, constant pool entry motion (to support
- large functions), and inline asm support, weak linkage support, static
+ large functions), inline asm support, weak linkage support, static
<li>Added support for Thumb code generation (<tt>llc -march=thumb</tt>).</li>
<li>The ARM backend now supports the ARM AAPCS/EABI ABI and PIC codegen on
arm/linux.</li>
<li>Several bugs were fixed for DWARF debug info generation on arm/linux.</li>
<li>Added support for Thumb code generation (<tt>llc -march=thumb</tt>).</li>
<li>The ARM backend now supports the ARM AAPCS/EABI ABI and PIC codegen on
arm/linux.</li>
<li>Several bugs were fixed for DWARF debug info generation on arm/linux.</li>
replaced by <tt>Type::Int8Ty</tt>, <tt>Type::Int16Ty</tt>, etc. LLVM types
have always corresponded to fixed size types
(e.g. long was always 64-bits), but the type system no longer includes
replaced by <tt>Type::Int8Ty</tt>, <tt>Type::Int16Ty</tt>, etc. LLVM types
have always corresponded to fixed size types
(e.g. long was always 64-bits), but the type system no longer includes
<li>Several classes (<tt>CallInst</tt>, <tt>GetElementPtrInst</tt>,
<tt>ConstantArray</tt>, etc), that once took <tt>std::vector</tt> as
<li>Several classes (<tt>CallInst</tt>, <tt>GetElementPtrInst</tt>,
<tt>ConstantArray</tt>, etc), that once took <tt>std::vector</tt> as
<pre>
std::vector<Value*> Ops = ...;
GEP = new GetElementPtrInst(BasePtr, &Ops[0], Ops.size());
<pre>
std::vector<Value*> Ops = ...;
GEP = new GetElementPtrInst(BasePtr, &Ops[0], Ops.size());
-<li>CastInst is now abstract and its functionality is split into several parts,
- one for each of the <a href="LangRef.html#convertops">new cast
- instructions</a>.</li>
+<li><tt>CastInst</tt> is now abstract and its functionality is split into
+ several parts, one for each of the <a href="LangRef.html#convertops">new
+ cast instructions</a>.</li>
<li><tt>Instruction::getNext()/getPrev()</tt> are now private (along with
<tt>BasicBlock::getNext</tt>, etc), for efficiency reasons (they are now no
<li><tt>Instruction::getNext()/getPrev()</tt> are now private (along with
<tt>BasicBlock::getNext</tt>, etc), for efficiency reasons (they are now no
<li>Intel and AMD machines running on Win32 with the Cygwin libraries (limited
support is available for native builds with Visual C++).</li>
<li>Intel and AMD machines running on Win32 with the Cygwin libraries (limited
support is available for native builds with Visual C++).</li>
<li>Alpha-based machines running Debian GNU/Linux.</li>
<li>Itanium-based machines running Linux and HP-UX.</li>
</ul>
<li>Alpha-based machines running Debian GNU/Linux.</li>
<li>Itanium-based machines running Linux and HP-UX.</li>
</ul>
<li>The IA64 code generator is experimental.</li>
<li>The Alpha JIT is experimental.</li>
<li>"<tt>-filetype=asm</tt>" (the default) is the only supported value for the
<li>The IA64 code generator is experimental.</li>
<li>The Alpha JIT is experimental.</li>
<li>"<tt>-filetype=asm</tt>" (the default) is the only supported value for the
<li><a href="http://llvm.org/PR642">PowerPC backend does not correctly
implement ordered FP comparisons</a>.</li>
<li>The Linux PPC32/ABI support needs testing for the interpreter and static
<li><a href="http://llvm.org/PR642">PowerPC backend does not correctly
implement ordered FP comparisons</a>.</li>
<li>The Linux PPC32/ABI support needs testing for the interpreter and static
-<li>The Thumb mode works only on ARMv6 or higher processors. On sub-ARMv6
-processors, any thumb program compiled with LLVM crashes or produces wrong
-results. (<a href="http://llvm.org/PR1388">PR1388</a>)</li>
+<li>Thumb mode works only on ARMv6 or higher processors. On sub-ARMv6
+processors, thumb program can crash or produces wrong
+results (<a href="http://llvm.org/PR1388">PR1388</a>).</li>
-<li>QEMU-ARM (<= 0.9.0) wrongly executes programs compiled with LLVM. A non-affected QEMU version must be used or this
-<a href="http://cvs.savannah.nongnu.org/viewcvs/qemu/target-arm/translate.c?root=qemu&r1=1.46&r2=1.47&makepatch=1&diff_format=h">
-patch</a> must be applied on QEMU.</li>
+<li>There is a bug in QEMU-ARM (<= 0.9.0) which causes it to incorrectly execute
+programs compiled with LLVM. Please use more recent versions of QEMU.</li>
<p>A wide variety of additional information is available on the <a
href="http://llvm.org">LLVM web page</a>, in particular in the <a
href="http://llvm.org/docs/">documentation</a> section. The web page also
<p>A wide variety of additional information is available on the <a
href="http://llvm.org">LLVM web page</a>, in particular in the <a
href="http://llvm.org/docs/">documentation</a> section. The web page also
-contains versions of the API documentation which is up-to-date with the CVS
-version of the source code.
+contains versions of the API documentation which is up-to-date with the
+Subversion version of the source code.
You can access versions of these documents specific to this release by going
into the "<tt>llvm/doc/</tt>" directory in the LLVM tree.</p>
You can access versions of these documents specific to this release by going
into the "<tt>llvm/doc/</tt>" directory in the LLVM tree.</p>