+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="newsparc">New SPARC backend</a></div>
+
+<div class="doc_text">
+
+<p>LLVM 1.7 includes a new, fully functional, SPARC backend built in the
+target-independent code generator. This SPARC backend includes support for
+SPARC V8 and SPARC V9 subtargets (controlling whether V9 features can be used),
+and targets the 32-bit SPARC ABI.</p>
+
+<p>The LLVM 1.7 release is the last release that will include the LLVM "SparcV9"
+backend, which was the very first LLVM native code generator. It will
+be removed in LLVM 1.8, being replaced with the new SPARC backend.</p>
+
+</div>
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="genvector">Generic Vector Support
+</a></div>
+
+<div class="doc_text">
+
+<p>LLVM now includes significantly extended support for SIMD vectors in its
+core instruction set. It now includes three new instructions for manipulating
+vectors: <a href="LangRef.html#i_extractelement"><tt>extractelement</tt></a>,
+<a href="LangRef.html#i_insertelement"><tt>insertelement</tt></a>, and
+<a href="LangRef.html#i_shufflevector"><tt>shufflevector</tt></a>. Further,
+many bugs in vector handling have been fixed, and vectors are now supported by
+the target-independent code generator. For example, if a vector operation is
+not supported by a particular target, it will be correctly broken down and
+executed as scalar operations.</p>
+
+<p>Because llvm-gcc3 does not support GCC generic vectors or vector intrinsics,
+llvm-gcc4 must be used.</p>
+</div>
+
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="ssealtivec">Intel SSE and PowerPC
+Altivec support
+</a></div>
+
+<div class="doc_text">
+
+<p>The LLVM X86 backend now supports Intel SSE 1, 2, and 3, and now uses scalar
+SSE operations to implement scalar floating point math when the target supports
+SSE1 (for floats) or SSE2 (for doubles). Vector SSE instructions are generated
+by llvm-gcc4 when the generic vector mechanism or specific SSE intrinsics are
+used.
+</p>
+
+<p>The LLVM PowerPC backend now supports the Altivec instruction set, including
+both GCC -maltivec and -faltivec modes. Altivec instructions are generated
+by llvm-gcc4 when the generic vector mechanism or specific Altivec intrinsics
+are used.
+</p>
+
+</div>
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="optimizernew">Optimizer
+Improvements</a></div>
+
+<div class="doc_text">
+<ul>
+<li>The Loop Unswitching pass (<tt>-loop-unswitch</tt>) has had several bugs
+ fixed, has several new features, and is enabled by default in llvmgcc3
+ now.</li>
+<li>The Loop Strength Reduction pass (<tt>-loop-reduce</tt>) is now enabled for
+ the X86 and Alpha backends.</li>
+<li>The Instruction Combining pass (<tt>-instcombine</tt>) now includes a
+ framework and implementation for simplifying code based on whether computed
+ bits are demanded or not.</li>
+<li>The Scalar Replacement of Aggregates pass (<tt>-scalarrepl</tt>) can now
+ promote simple unions to registers.</li>
+<li>The Reassociation pass (<tt>-reassociate</tt>) can now
+ factor expressions, e.g. turning "A*A+A*B" into "A*(A+B)".</li>
+<li>Several LLVM passes are <a href="http://llvm.org/PR681">significantly
+faster</a>.</li>
+</ul>
+</div>
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="codgennew">Code Generator
+Improvements</a></div>
+
+<div class="doc_text">
+<ul>
+<li>LLVM has a new prepass (before register allocation) list scheduler, which
+ supports bottom-up and top-down scheduling, pluggable priority functions and
+ pluggable hazard recognizers. The X86 backend uses this to reduce register
+ pressure and RISC targets schedule based on operation latency.</li>
+<li>The tblgen-based target description framework introduced in LLVM 1.6 has
+ several new features, useful for targets that can fold loads and stores into
+ operations, and features that make the .td files more expressive.</li>
+<li>The instruction selector is significantly faster in 1.7 than in 1.6.</li>
+<li>The X86, Alpha and Itanium backends use new DAG-DAG instruction selectors,
+ making them easier to maintain and generate slightly better code.</li>
+<li>The X86 backend now supports generation of Scalar SSE code for scalar FP
+ expressions. LLVM provides significantly better performance with Scalar SSE
+ instructions than it does with the Intel floating point stack
+ instructions.</li>
+<li>The Itanium backend now has a bundling pass, which improves performance
+ by ~10% and reduces code size (previously it unconditionally inserted a stop
+ bit after every instruction).</li>
+</ul>
+</div>
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="othernew">Other New Features</a></div>
+
+<div class="doc_text">
+<ul>
+<li>The Mac OS/X PowerPC and X86 backends now have initial support for
+ Darwin DWARF
+ debugging information, however, debug info generation has been disabled for
+ the 1.7 release in llvmgcc4.</li>
+<li>LLVM includes the new <a href="docs/CommandGuide/html/llvm-config.html">
+ llvm-config</a> utility, which makes it easier to build and link programs
+ against the LLVM libraries when not using the LLVM makefiles.</li>
+<li>LLVM now supports first class global ctor/dtor initialization lists, no
+ longer forcing targets to use "__main".</li>
+<li>LLVM supports assigning globals and functions to a particular section
+ in the result executable using the GCC section attribute.</li>
+<li><a href="ExtendingLLVM.html">Adding intrinsics to LLVM</a> is now
+ significantly easier.</li>
+<li>llvmgcc4 now fully supports C99 Variable Length Arrays, including dynamic
+ stack deallocation.</li>
+
+</ul>
projects / oota-llvm.git / blobdiff