+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="llvmgcc4">GCC4.0-based llvm-gcc
+front-end</a></div>
+
+<div class="doc_text">
+
+<p>LLVM 1.7 includes a brand new llvm-gcc, based on GCC 4.0.1. This version
+of llvm-gcc solves many serious long-standing problems with llvm-gcc, including
+all of those blocked by the <a href="http://llvm.org/PR498">llvm-gcc 4 meta
+bug</a>. In addition, llvm-gcc4 implements support for many new features,
+including GCC inline assembly, generic vector support, SSE and Altivec
+intrinsics, and several new GCC attributes. Finally, llvm-gcc4 is
+significantly faster than llvm-gcc3, respects -O options, its -c/-S options
+correspond to GCC's (they emit native code), supports Objective C/C++, and
+it has debugging support well underway.</p>
+
+<p>If you can use it, llvm-gcc4 offers significant new functionality, and we
+hope that it will replace llvm-gcc3 completely in a future release.
+Unfortunately, it does not currently support C++ exception handling at all, and
+it only works on Apple Mac OS/X machines with X86 or PowerPC processors.
+</p>
+
+</div>
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="inlineasm">Inline Assembly
+Support</a></div>
+
+<div class="doc_text">
+
+<p>The LLVM IR and llvm-gcc4 front-end now fully support arbitrary GCC <a
+href="LangRef.html#inlineasm">inline assembly</a>. The LLVM X86 and PowerPC
+code generators have initial support for it,
+being able to compile basic statements, but are missing some features. Please
+report any inline asm statements that crash the compiler or that are miscompiled
+as bugs.</p>
+
+</div>
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="newsparc">New SPARC backend</a></div>
+
+<div class="doc_text">
+
+<p>LLVM 1.7 includes a new, fully functional, SPARC backend built in the
+target-independent code generator. This SPARC backend includes support for
+SPARC V8 and SPARC V9 subtargets (controlling whether V9 features can be used),
+and targets the 32-bit SPARC ABI.</p>
+
+<p>The LLVM 1.7 release is the last release that will include the LLVM "SparcV9"
+backend, which was the very first LLVM native code generator. It will
+be removed in LLVM 1.8, being replaced with the new SPARC backend.</p>
+
+</div>
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="genvector">Generic Vector Support
+</a></div>
+
+<div class="doc_text">
+
+<p>LLVM now includes significantly extended support for SIMD vectors in its
+core instruction set. It now includes three new instructions for manipulating
+vectors: <a href="LangRef.html#i_extractelement"><tt>extractelement</tt></a>,
+<a href="LangRef.html#i_insertelement"><tt>insertelement</tt></a>, and
+<a href="LangRef.html#i_shufflevector"><tt>shufflevector</tt></a>. Further,
+many bugs in vector handling have been fixed, and vectors are now supported by
+the target-independent code generator. For example, if a vector operation is
+not supported by a particular target, it will be correctly broken down and
+executed as scalar operations.</p>
+
+<p>Because llvm-gcc3 does not support GCC generic vectors or vector intrinsics,
+llvm-gcc4 must be used.</p>
+</div>
+
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="ssealtivec">Intel SSE and PowerPC
+Altivec support
+</a></div>
+
+<div class="doc_text">
+
+<p>The LLVM X86 backend now supports Intel SSE 1, 2, and 3, and now uses scalar
+SSE operations to implement scalar floating point math when the target supports
+SSE1 (for floats) or SSE2 (for doubles). Vector SSE instructions are generated
+by llvm-gcc4 when the generic vector mechanism or specific SSE intrinsics are
+used.
+</p>
+
+<p>The LLVM PowerPC backend now supports the Altivec instruction set, including
+both GCC -maltivec and -faltivec modes. Altivec instructions are generated
+by llvm-gcc4 when the generic vector mechanism or specific Altivec intrinsics
+are used.
+</p>
+
+</div>
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="optimizernew">Optimizer
+Improvements</a></div>
+
+<div class="doc_text">
+<ul>
+<li>The Loop Unswitching pass (<tt>-loop-unswitch</tt>) has had several bugs
+ fixed, has several new features, and is enabled by default in llvmgcc3
+ now.</li>
+<li>The Loop Strength Reduction pass (<tt>-loop-reduce</tt>) is now enabled for
+ the X86 and Alpha backends.</li>
+<li>The Instruction Combining pass (<tt>-instcombine</tt>) now includes a
+ framework and implementation for simplifying code based on whether computed
+ bits are demanded or not.</li>
+<li>The Scalar Replacement of Aggregates pass (<tt>-scalarrepl</tt>) can now
+ promote simple unions to registers.</li>
+<li>The Reassociation pass (<tt>-reassociate</tt>) can now
+ factor expressions, e.g. turning "A*A+A*B" into "A*(A+B)".</li>
+<li>Several LLVM passes are <a href="http://llvm.org/PR681">significantly
+faster</a>.</li>
+</ul>
+</div>
+
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="codgennew">Code Generator
+Improvements</a></div>
+