-During this release the MIPS target has reached a few major milestones. It has
-gained support for MIPS-II and MIPS-III, become ABI-compatible with GCC for big
-and little endian O32, N32, and N64, and it is now able to compile the Linux
-kernel for 32-bit targets.
-
-ABI
-^^^
-
-A large number of bugs have been fixed for big-endian MIPS targets using the
-N32 and N64 ABI's as well as a small number of bugs affecting other ABI's.
-Please note that some of these bugs will still affect LLVM-IR generated by
-LLVM 3.5 since correct code generation depends on appropriate usage of the
-``inreg``, ``signext``, and ``zeroext`` attributes on all function arguments
-and returns.
-
-There are far too many corrections to provide a complete list but here are a
-few notable ones:
-
-* Big-endian N32 and N64 now interlinks successfully with GCC compiled code.
- Previously this didn't work for the majority of cases.
-
-* The registers used to return a structure containing a single 128-bit floating
- point member on the N32/N64 ABI's have been changed from those specified by
- the ABI documentation to match those used by GCC. The documentation specifies
- that ``$f0`` and ``$f2`` should be used but GCC has used ``$f0`` and ``$f1``
- for many years.
-
-* Returning a zero-byte struct no longer causes arguments to be read from the
- wrong registers when using the O32 ABI.
-
-* The exception personality has been changed for 64-bit MIPS targets to
- eliminate warnings about relocations in a read-only section.
-
-* Incorrect usage of odd-numbered single-precision floating point registers
- has been fixed when the fastcc calling convention is used with 64-bit FPU's
- and -mno-odd-spreg.
-
-LLVMLinux
-^^^^^^^^^
-
-It is now possible to compile the Linux kernel. This currently requires a small
-number of kernel patches. See the `LLVMLinux project
-<http://llvm.linuxfoundation.org/index.php/Main_Page>`_ for details.
-
-* Added -mabicalls and -mno-abicalls. The implementation may not be complete
- but works sufficiently well for the Linux kernel.
-
-* Fixed multiple compatibility issues between LLVM's inline assembly support
- and GCC's.
-
-* Added support for a number of directives used by Linux to the Integrated
- Assembler.
-
-Miscellaneous
-^^^^^^^^^^^^^
-
-* Attempting to disassemble l[wd]c[23], s[wd]c[23], cache, and pref no longer
- triggers an assertion.
-
-* Added -muclibc and -mglibc to support toolchains that provide both uClibC and
- GLibC.
-
-* __SIZEOF_INT128__ is no longer defined for 64-bit targets since 128-bit
- integers do not work at this time for this target.
-
-* Using $t4-$t7 with the N32 and N64 ABI is deprecated when ``-fintegrated-as``
- is in use and will be removed in LLVM 3.7. These names have never been
- supported by the GNU Assembler for these ABI's.
+During this release the MIPS target has:
+
+* Significantly extended support for the Integrated Assembler. See below for
+ more information
+* Added support for the ``P5600`` processor.
+* Added support for the ``interrupt`` attribute for MIPS32R2 and later. This
+ attribute will generate a function which can be used as a interrupt handler
+ on bare metal MIPS targets using the static relocation model.
+* Added support for the ``ERETNC`` instruction found in MIPS32R5 and later.
+* Added support for OpenCL. See http://portablecl.org/.
+
+ * Address spaces 1 to 255 are now reserved for software use and conversions
+ between them are no-op casts.
+
+* Removed the ``mips16`` value for the -mcpu option since it is an :abbr:`ASE
+ (Application Specific Extension)` and not a processor. If you were using this,
+ please specify another CPU and use ``-mips16`` to enable MIPS16.
+* Removed ``copy_u.w`` from 32-bit MSA and ``copy_u.d`` from 64-bit MSA since
+ they have been removed from the MSA specification due to forward compatibility
+ issues. For example, 32-bit MSA code containing ``copy_u.w`` would behave
+ differently on a 64-bit processor supporting MSA. The corresponding intrinsics
+ are still available and may expand to ``copy_s.[wd]`` where this is
+ appropriate for forward compatibility purposes.
+* Relaxed the ``-mnan`` option to allow ``-mnan=2008`` on MIPS32R2/MIPS64R2 for
+ compatibility with GCC.
+* Made MIPS64R6 the default CPU for 64-bit Android triples.
+
+The MIPS target has also fixed various bugs including the following notable
+fixes:
+
+* Fixed reversed operands on ``mthi``/``mtlo`` in the DSP :abbr:`ASE
+ (Application Specific Extension)`.
+* The code generator no longer uses ``jal`` for calls to absolute immediate
+ addresses.
+* Disabled fast instruction selection on MIPS32R6 and MIPS64R6 since this is not
+ yet supported.
+* Corrected addend for ``R_MIPS_HI16`` and ``R_MIPS_PCHI16`` in MCJIT
+* The code generator no longer crashes when handling subregisters of an 64-bit
+ FPU register with undefined value.
+* The code generator no longer attempts to use ``$zero`` for operands that do
+ not permit ``$zero``.
+* Corrected the opcode used for ``ll``/``sc`` when using MIPS32R6/MIPS64R6 and
+ the Integrated Assembler.
+* Added support for atomic load and atomic store.
+* Corrected debug info when dynamically re-aligning the stack.
+
+Integrated Assembler
+^^^^^^^^^^^^^^^^^^^^
+We have made a large number of improvements to the integrated assembler for
+MIPS. In this release, the integrated assembler isn't quite production-ready
+since there are a few known issues related to bare-metal support, checking
+immediates on instructions, and the N32/N64 ABI's. However, the current support
+should be sufficient for many users of the O32 ABI, particularly those targeting
+MIPS32 on Linux or bare-metal MIPS32.
+
+If you would like to try the integrated assembler, please use
+``-fintegrated-as``.