+static void exynos5440_gpio_irq_unmask(struct irq_data *irqd)
+{
+ struct exynos5440_pinctrl_priv_data *d;
+ unsigned long gpio_int;
+
+ d = irq_data_get_irq_chip_data(irqd);
+ gpio_int = readl(d->reg_base + GPIO_INT);
+ gpio_int |= 1 << irqd->hwirq;
+ writel(gpio_int, d->reg_base + GPIO_INT);
+}
+
+static void exynos5440_gpio_irq_mask(struct irq_data *irqd)
+{
+ struct exynos5440_pinctrl_priv_data *d;
+ unsigned long gpio_int;
+
+ d = irq_data_get_irq_chip_data(irqd);
+ gpio_int = readl(d->reg_base + GPIO_INT);
+ gpio_int &= ~(1 << irqd->hwirq);
+ writel(gpio_int, d->reg_base + GPIO_INT);
+}
+
+/* irq_chip for gpio interrupts */
+static struct irq_chip exynos5440_gpio_irq_chip = {
+ .name = "exynos5440_gpio_irq_chip",
+ .irq_unmask = exynos5440_gpio_irq_unmask,
+ .irq_mask = exynos5440_gpio_irq_mask,
+};
+
+/* interrupt handler for GPIO interrupts 0..7 */
+static irqreturn_t exynos5440_gpio_irq(int irq, void *data)
+{
+ struct exynos5440_gpio_intr_data *intd = data;
+ struct exynos5440_pinctrl_priv_data *d = intd->priv;
+ int virq;
+
+ virq = irq_linear_revmap(d->irq_domain, intd->gpio_int);
+ if (!virq)
+ return IRQ_NONE;
+ generic_handle_irq(virq);
+ return IRQ_HANDLED;
+}
+
+static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ struct exynos5440_pinctrl_priv_data *d = h->host_data;
+
+ irq_set_chip_data(virq, d);
+ irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
+ handle_level_irq);
+ set_irq_flags(virq, IRQF_VALID);
+ return 0;
+}
+
+/* irq domain callbacks for gpio interrupt controller */
+static const struct irq_domain_ops exynos5440_gpio_irqd_ops = {
+ .map = exynos5440_gpio_irq_map,
+ .xlate = irq_domain_xlate_twocell,
+};
+
+/* setup handling of gpio interrupts */
+static int exynos5440_gpio_irq_init(struct platform_device *pdev,
+ struct exynos5440_pinctrl_priv_data *priv)
+{
+ struct device *dev = &pdev->dev;
+ struct exynos5440_gpio_intr_data *intd;
+ int i, irq, ret;
+
+ intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
+ GFP_KERNEL);
+ if (!intd) {
+ dev_err(dev, "failed to allocate memory for gpio intr data\n");
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
+ irq = irq_of_parse_and_map(dev->of_node, i);
+ if (irq <= 0) {
+ dev_err(dev, "irq parsing failed\n");
+ return -EINVAL;
+ }
+
+ intd->gpio_int = i;
+ intd->priv = priv;
+ ret = devm_request_irq(dev, irq, exynos5440_gpio_irq,
+ 0, dev_name(dev), intd++);
+ if (ret) {
+ dev_err(dev, "irq request failed\n");
+ return -ENXIO;
+ }
+ }
+
+ priv->irq_domain = irq_domain_add_linear(dev->of_node,
+ EXYNOS5440_MAX_GPIO_INT,
+ &exynos5440_gpio_irqd_ops, priv);
+ if (!priv->irq_domain) {
+ dev_err(dev, "failed to create irq domain\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+