+
+ return DRV_TYPE_IO_DEFAULT;
+}
+
+#define RK3228_PULL_OFFSET 0x100
+
+static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ *reg = RK3228_PULL_OFFSET;
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+}
+
+#define RK3228_DRV_GRF_OFFSET 0x200
+
+static enum rockchip_pin_drv_type rk3228_calc_drv_reg_and_bit(
+ struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ *reg = RK3228_DRV_GRF_OFFSET;
+ *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
+ *bit *= RK3288_DRV_BITS_PER_PIN;
+
+ return DRV_TYPE_IO_DEFAULT;
+}
+
+#define RK3366_PULL_GRF_OFFSET 0x110
+#define RK3366_PULL_PMU_OFFSET 0x10
+
+static void rk3366_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The bank0:32 and bank1:16 pins are located in PMU */
+ if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3366_PULL_PMU_OFFSET + bank->bank_num * 0x30;
+
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3188_PULL_PINS_PER_REG;
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3366_PULL_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x20;
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ }
+}
+
+#define RK3366_DRV_PMU_OFFSET 0x20
+#define RK3366_DRV_GRF_OFFSET 0x210
+
+#define RK3366_DRV_GPIO2B3_OFFSET 0x378
+#define RK3366_DRV_GPIO2B3_BITS 4
+
+#define RK3366_DRV_GPIO3A4_OFFSET 0x37c
+#define RK3366_DRV_GPIO3A4_BITS 4
+
+static enum rockchip_pin_drv_type rk3366_calc_drv_reg_and_bit(
+ struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The bank0:32 and bank1:16 pins are located in PMU */
+ if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3366_DRV_PMU_OFFSET + bank->bank_num * 0x30;
+
+ *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3288_DRV_PINS_PER_REG;
+ *bit *= RK3288_DRV_BITS_PER_PIN;
+
+ return DRV_TYPE_IO_DEFAULT;
+ } else if ((bank->bank_num == 2) && (pin_num == 11)) {
+ /* GPIO2B3 is a special case in bank2 */
+ *regmap = info->regmap_base;
+ *reg = RK3366_DRV_GPIO2B3_OFFSET;
+ *bit = RK3366_DRV_GPIO2B3_BITS;
+
+ return DRV_TYPE_IO_WIDE_LEVEL;
+ } else if ((bank->bank_num == 3) && (pin_num == 4)) {
+ /* GPIO3A4 is a special case in bank3 */
+ *regmap = info->regmap_base;
+ *reg = RK3366_DRV_GPIO3A4_OFFSET;
+ *bit = RK3366_DRV_GPIO3A4_BITS;
+
+ return DRV_TYPE_IO_WIDE_LEVEL;
+ }
+
+ *regmap = info->regmap_base;
+ *reg = RK3366_DRV_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x20;
+ *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
+ *bit *= RK3288_DRV_BITS_PER_PIN;
+
+ /* special cases need special handle */
+ if ((bank->bank_num == 2) && (pin_num == 14))
+ return DRV_TYPE_IO_WIDE_LEVEL;
+ else if ((bank->bank_num == 2) && (pin_num == 16))
+ return DRV_TYPE_IO_NARROW_LEVEL;
+ else if ((bank->bank_num == 2) && (pin_num >= 24) && (pin_num <= 26))
+ return DRV_TYPE_IO_WIDE_LEVEL;
+
+ return DRV_TYPE_IO_DEFAULT;
+}
+
+#define RK3366_DRV_GPIO2A_EN_OFFSET 0x360
+#define RK3366_DRV_GPIO2A_EP_OFFSET 0x364
+
+#define RK3366_DRV_GPIO2C_EN_OFFSET 0x368
+#define RK3366_DRV_GPIO2C_EP_OFFSET 0x36C
+
+#define RK3366_DRV_GPIO2D_EN_OFFSET 0x370
+#define RK3366_DRV_GPIO2D_EP_OFFSET 0x374
+
+#define RK3366_DRV_GPIO2B3_E_OFFSET 0x378
+#define RK3366_DRV_GPIO2B3_EN_BIT 0
+#define RK3366_DRV_GPIO2B3_EP_BIT 2
+
+#define RK3366_DRV_GPIO3A4_E_OFFSET 0x37c
+#define RK3366_DRV_GPIO3A4_EN_BIT 0
+#define RK3366_DRV_GPIO3A4_EP_BIT 2
+
+#define RK3366_DRV_GPIO2B6_E_OFFSET 0x404
+#define RK3366_DRV_GPIO2B6_EN_BIT 12
+#define RK3366_DRV_GPIO2B6_EP_BIT 14
+
+static enum rockchip_pin_extra_drv_type rk3366_calc_drv_extra_reg_and_bit(
+ struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+ if (bank->bank_num == 2) {
+ switch (pin_num / 8) {
+ case 0:
+ *reg = RK3366_DRV_GPIO2A_EN_OFFSET;
+ break;
+ case 1:
+ /* special cases need special handle */
+ if (pin_num == 11) {
+ *reg = RK3366_DRV_GPIO2B3_E_OFFSET;
+ *bit = RK3366_DRV_GPIO2B3_EN_BIT;
+ } else if (pin_num == 14) {
+ *reg = RK3366_DRV_GPIO2B6_E_OFFSET;
+ *bit = RK3366_DRV_GPIO2B6_EN_BIT;
+ } else {
+ return -1;
+ }
+
+ return DRV_TYPE_EXTRA_SAME_OFFSET;
+ case 2:
+ *reg = RK3366_DRV_GPIO2C_EN_OFFSET;
+ break;
+ case 3:
+ *reg = RK3366_DRV_GPIO2D_EN_OFFSET;
+ break;
+ default:
+ return -1;
+ }
+
+ *bit = pin_num % RK3288_DRV_PINS_PER_REG;
+ *bit *= RK3288_DRV_BITS_PER_PIN;
+
+ return DRV_TYPE_EXTRA_SAME_BITS;
+ }
+
+ /* GPIO3A4 is a special case */
+ if ((pin_num != 4) && (bank->bank_num != 3))
+ return -1;
+
+ *reg = RK3366_DRV_GPIO3A4_E_OFFSET;
+ *bit = RK3366_DRV_GPIO3A4_EN_BIT;
+
+ return DRV_TYPE_EXTRA_SAME_OFFSET;