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Staging: dt3155: Cleanup memory mapped i/o access
[firefly-linux-kernel-4.4.55.git]
/
drivers
/
staging
/
dt3155
/
dt3155_io.c
diff --git
a/drivers/staging/dt3155/dt3155_io.c
b/drivers/staging/dt3155/dt3155_io.c
index 7792e712d16eee851acc992bd3275c760272740a..485cc5e7b16b0e85d62e4c3da70c4631f19b4270 100644
(file)
--- a/
drivers/staging/dt3155/dt3155_io.c
+++ b/
drivers/staging/dt3155/dt3155_io.c
@@
-21,6
+21,8
@@
*/
#include <linux/delay.h>
*/
#include <linux/delay.h>
+#include <linux/io.h>
+
#include "dt3155.h"
#include "dt3155_io.h"
#include "dt3155_drv.h"
#include "dt3155.h"
#include "dt3155_io.h"
#include "dt3155_drv.h"
@@
-75,13
+77,13
@@
u8 i2c_pm_lut_data;
*
* This function handles read/write timing and r/w timeout error
*/
*
* This function handles read/write timing and r/w timeout error
*/
-static int wait_ibsyclr(
u8 *lpReg
)
+static int wait_ibsyclr(
void __iomem *mmio
)
{
/* wait 100 microseconds */
udelay(100L);
/* __delay(loops_per_sec/10000); */
{
/* wait 100 microseconds */
udelay(100L);
/* __delay(loops_per_sec/10000); */
-
ReadMReg(lpReg + IIC_CSR2, iic_csr2_r.reg
);
+
iic_csr2_r.reg = readl(mmio + IIC_CSR2
);
if (iic_csr2_r.fld.NEW_CYCLE) {
/* if NEW_CYCLE didn't clear */
/* TIMEOUT ERROR */
if (iic_csr2_r.fld.NEW_CYCLE) {
/* if NEW_CYCLE didn't clear */
/* TIMEOUT ERROR */
@@
-101,11
+103,11
@@
static int wait_ibsyclr(u8 *lpReg)
* 2nd parameter is reg. index;
* 3rd is value to be written
*/
* 2nd parameter is reg. index;
* 3rd is value to be written
*/
-int WriteI2C(
u8 *lpReg
, u_short wIregIndex, u8 byVal)
+int WriteI2C(
void __iomem *mmio
, u_short wIregIndex, u8 byVal)
{
/* read 32 bit IIC_CSR2 register data into union */
{
/* read 32 bit IIC_CSR2 register data into union */
-
ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg
);
+
iic_csr2_r.reg = readl(mmio + IIC_CSR2
);
/* for write operation */
iic_csr2_r.fld.DIR_RD = 0;
/* for write operation */
iic_csr2_r.fld.DIR_RD = 0;
@@
-117,10
+119,10
@@
int WriteI2C(u8 *lpReg, u_short wIregIndex, u8 byVal)
iic_csr2_r.fld.NEW_CYCLE = 1;
/* xfer union data into 32 bit IIC_CSR2 register */
iic_csr2_r.fld.NEW_CYCLE = 1;
/* xfer union data into 32 bit IIC_CSR2 register */
-
WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg
);
+
writel(iic_csr2_r.reg, mmio + IIC_CSR2
);
/* wait for IIC cycle to finish */
/* wait for IIC cycle to finish */
- return wait_ibsyclr(
lpReg
);
+ return wait_ibsyclr(
mmio
);
}
/*
}
/*
@@
-132,12
+134,12
@@
int WriteI2C(u8 *lpReg, u_short wIregIndex, u8 byVal)
* 2nd parameter is reg. index;
* 3rd is adrs of value to be read
*/
* 2nd parameter is reg. index;
* 3rd is adrs of value to be read
*/
-int ReadI2C(
u8 *lpReg
, u_short wIregIndex, u8 *byVal)
+int ReadI2C(
void __iomem *mmio
, u_short wIregIndex, u8 *byVal)
{
int writestat; /* status for return */
/* read 32 bit IIC_CSR2 register data into union */
{
int writestat; /* status for return */
/* read 32 bit IIC_CSR2 register data into union */
-
ReadMReg((lpReg + IIC_CSR2), iic_csr2_r.reg
);
+
iic_csr2_r.reg = readl(mmio + IIC_CSR2
);
/* for read operation */
iic_csr2_r.fld.DIR_RD = 1;
/* for read operation */
iic_csr2_r.fld.DIR_RD = 1;
@@
-149,14
+151,14
@@
int ReadI2C(u8 *lpReg, u_short wIregIndex, u8 *byVal)
iic_csr2_r.fld.NEW_CYCLE = 1;
/* xfer union's data into 32 bit IIC_CSR2 register */
iic_csr2_r.fld.NEW_CYCLE = 1;
/* xfer union's data into 32 bit IIC_CSR2 register */
-
WriteMReg((lpReg + IIC_CSR2), iic_csr2_r.reg
);
+
writel(iic_csr2_r.reg, mmio + IIC_CSR2
);
/* wait for IIC cycle to finish */
/* wait for IIC cycle to finish */
- writestat = wait_ibsyclr(
lpReg
);
+ writestat = wait_ibsyclr(
mmio
);
/* Next 2 commands read 32 bit IIC_CSR1 register's data into union */
/* first read data is in IIC_CSR1 */
/* Next 2 commands read 32 bit IIC_CSR1 register's data into union */
/* first read data is in IIC_CSR1 */
-
ReadMReg((lpReg + IIC_CSR1), iic_csr1_r.reg
);
+
iic_csr1_r.reg = readl(mmio + IIC_CSR1
);
/* now get data u8 out of register */
*byVal = (u8) iic_csr1_r.fld.RD_DATA;
/* now get data u8 out of register */
*byVal = (u8) iic_csr1_r.fld.RD_DATA;