-\r
- rga_write(0x0, RGA_SYS_CTRL); \r
- rga_write(0, RGA_MMU_CTRL);\r
-\r
- /* CMD buff */\r
- rga_write(virt_to_phys(rga_service.cmd_buff), RGA_CMD_ADDR);\r
-\r
-#if RGA_TEST\r
- {\r
- //printk(KERN_DEBUG "cmd_addr = %.8x\n", rga_read(RGA_CMD_ADDR));\r
- uint32_t i;\r
- uint32_t *p;\r
- p = rga_service.cmd_buff;\r
- printk("CMD_REG\n");\r
- for (i=0; i<7; i++)\r
- printk("%.8x %.8x %.8x %.8x\n", p[0 + i*4], p[1+i*4], p[2 + i*4], p[3 + i*4]);\r
- }\r
-#endif\r
-\r
- /* master mode */\r
- rga_write((0x1<<2)|(0x1<<3), RGA_SYS_CTRL);\r
-\r
- /* All CMD finish int */\r
- rga_write(rga_read(RGA_INT)|(0x1<<10)|(0x1<<8), RGA_INT);\r
-\r
- /* Start proc */\r
- atomic_set(®->session->done, 0);\r
- rga_write(0x1, RGA_CMD_CTRL);\r
-\r
-#if RGA_TEST\r
- {\r
- uint32_t i;\r
- printk("CMD_READ_BACK_REG\n");\r
- for (i=0; i<7; i++)\r
- printk("%.8x %.8x %.8x %.8x\n", rga_read(0x100 + i*16 + 0),\r
- rga_read(0x100 + i*16 + 4), rga_read(0x100 + i*16 + 8), rga_read(0x100 + i*16 + 12));\r
- }\r
-#endif\r
- }\r
- }\r
-}\r
-\r
-\r
-\r
-\r
-/* Caller must hold rga_service.lock */\r
-static void rga_del_running_list(void)\r
-{\r
- struct rga_reg *reg;\r
-\r
- while(!list_empty(&rga_service.running))\r
- {\r
- reg = list_entry(rga_service.running.next, struct rga_reg, status_link);\r
- \r
- if(reg->MMU_base != NULL)\r
- {\r
- kfree(reg->MMU_base);\r
- reg->MMU_base = NULL;\r
- }\r
- atomic_sub(1, ®->session->task_running);\r
- atomic_sub(1, &rga_service.total_running);\r
-\r
- if(list_empty(®->session->waiting))\r
- {\r
- atomic_set(®->session->done, 1);\r
- wake_up_interruptible_sync(®->session->wait);\r
- }\r
-\r
- rga_reg_deinit(reg);\r
- }\r
-}\r
-\r
-/* Caller must hold rga_service.lock */\r
-static void rga_del_running_list_timeout(void)\r
-{\r
- struct rga_reg *reg;\r
-\r
- while(!list_empty(&rga_service.running))\r
- {\r
- reg = list_entry(rga_service.running.next, struct rga_reg, status_link);\r
-\r
- if(reg->MMU_base != NULL)\r
- {\r
- kfree(reg->MMU_base);\r
- }\r
-\r
- atomic_sub(1, ®->session->task_running);\r
- atomic_sub(1, &rga_service.total_running);\r
-\r
- printk("RGA soft reset for timeout process\n");\r
- rga_soft_reset();\r
- \r
-\r
- #if 0\r
- printk("RGA_INT is %.8x\n", rga_read(RGA_INT));\r
- printk("reg->session->task_running = %d\n", atomic_read(®->session->task_running));\r
- printk("rga_service.total_running = %d\n", atomic_read(&rga_service.total_running));\r
-\r
- print_info(®->req);\r
-\r
- {\r
- uint32_t *p, i;\r
- p = reg->cmd_reg;\r
- for (i=0; i<7; i++)\r
- printk("%.8x %.8x %.8x %.8x\n", p[0 + i*4], p[1+i*4], p[2 + i*4], p[3 + i*4]);\r
-\r
- }\r
- #endif\r
-\r
- if(list_empty(®->session->waiting))\r
- {\r
- atomic_set(®->session->done, 1);\r
- wake_up_interruptible_sync(®->session->wait);\r
- }\r
-\r
- rga_reg_deinit(reg);\r
- }\r
-}\r
-\r
-\r
-static void rga_mem_addr_sel(struct rga_req *req)\r
-{\r
- switch(req->src.format)\r
- {\r
- case RK_FORMAT_YCbCr_422_SP:\r
- break;\r
- case RK_FORMAT_YCbCr_422_P :\r
- break;\r
- case RK_FORMAT_YCbCr_420_SP :\r
- if((req->src.yrgb_addr > 0xc0000000) && (req->src.uv_addr > 0xc0000000)\r
- && (req->dst.yrgb_addr > 0xc0000000))\r
- {\r
- req->src.yrgb_addr = req->src.yrgb_addr - 0x60000000;\r
- req->src.uv_addr = req->src.uv_addr - 0x60000000;\r
- req->dst.yrgb_addr = req->dst.yrgb_addr - 0x60000000;\r
- req->mmu_info.mmu_en = 0;\r
- req->mmu_info.mmu_flag &= 0xfffe;\r
- }\r
- break;\r
- case RK_FORMAT_YCbCr_420_P :\r
- break;\r
- case RK_FORMAT_YCrCb_422_SP :\r
- break;\r
- case RK_FORMAT_YCrCb_422_P :\r
- break;\r
- case RK_FORMAT_YCrCb_420_SP :\r
- break;\r
- case RK_FORMAT_YCrCb_420_P :\r
- break;\r
- default :\r
- break;\r
- }\r
-\r
-}\r
-\r
-\r
-static int rga_blit(rga_session *session, struct rga_req *req)\r
-{\r
- int ret = -1;\r
- int num = 0;\r
- struct rga_reg *reg;\r
- struct rga_req req2;\r
-\r
- uint32_t saw, sah, daw, dah;\r
-\r
- saw = req->src.act_w;\r
- sah = req->src.act_h;\r
- daw = req->dst.act_w;\r
- dah = req->dst.act_h;\r
- \r
- do\r
- {\r
- if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah)))\r
- {\r
- /* generate 2 cmd for pre scale */ \r
-\r
- ret = rga_check_param(req);\r
- if(ret == -EINVAL) {\r
- printk("req 0 argument is inval\n");\r
- break;\r
- }\r
-\r
- ret = RGA_gen_two_pro(req, &req2);\r
- if(ret == -EINVAL) {\r
- break;\r
- }\r
-\r
- ret = rga_check_param(req);\r
- if(ret == -EINVAL) {\r
- printk("req 1 argument is inval\n");\r
- break;\r
- }\r
-\r
- ret = rga_check_param(&req2);\r
- if(ret == -EINVAL) {\r
- printk("req 2 argument is inval\n");\r
- break;\r
- }\r
-\r
- reg = rga_reg_init_2(session, req, &req2);\r
- if(reg == NULL) {\r
- break;\r
- }\r
- num = 2;\r
- \r
- }\r
- else\r
- {\r
- /* check value if legal */\r
- ret = rga_check_param(req);\r
- if(ret == -EINVAL) {\r
- printk("req argument is inval\n");\r
- break;\r
- }\r
-\r
- if(req->render_mode == bitblt_mode)\r
- {\r
- rga_mem_addr_sel(req);\r
- }\r
-\r
- reg = rga_reg_init(session, req);\r
- if(reg == NULL) {\r
- break;\r
- }\r
- num = 1;\r
- }\r
-\r
- mutex_lock(&rga_service.lock);\r
- atomic_add(num, &rga_service.total_running);\r
- rga_try_set_reg();\r
- mutex_unlock(&rga_service.lock);\r
-\r
- return 0;\r
- }\r
- while(0);\r
-\r
- return -EFAULT;\r
-}\r
-\r
-static int rga_blit_async(rga_session *session, struct rga_req *req)\r
-{\r
- int ret = -1;\r
-\r
- #if RGA_TEST\r
- printk("*** rga_blit_async proc ***\n");\r
- print_info(req);\r
+
+ #if 1
+ rga_soft_reset();
+ #endif
+
+ rga_write(0x0, RGA_SYS_CTRL);
+ rga_write(0, RGA_MMU_CTRL);
+
+ /* CMD buff */
+ rga_write(virt_to_phys(rga_service.cmd_buff), RGA_CMD_ADDR);
+
+#if RGA_TEST
+ {
+ //printk(KERN_DEBUG "cmd_addr = %.8x\n", rga_read(RGA_CMD_ADDR));
+ uint32_t i;
+ uint32_t *p;
+ p = rga_service.cmd_buff;
+ printk("CMD_REG\n");
+ for (i=0; i<7; i++)
+ printk("%.8x %.8x %.8x %.8x\n", p[0 + i*4], p[1+i*4], p[2 + i*4], p[3 + i*4]);
+ printk("%.8x %.8x\n", p[0 + i*4], p[1+i*4]);
+ }
+#endif
+
+ /* master mode */
+ rga_write((0x1<<2)|(0x1<<3), RGA_SYS_CTRL);
+
+ /* All CMD finish int */
+ rga_write(rga_read(RGA_INT)|(0x1<<10)|(0x1<<8), RGA_INT);
+
+ #if RGA_TEST_TIME
+ rga_start = ktime_get();
+ #endif
+
+ /* Start proc */
+ atomic_set(®->session->done, 0);
+ rga_write(0x1, RGA_CMD_CTRL);
+
+#if RGA_TEST
+ {
+ uint32_t i;
+ printk("CMD_READ_BACK_REG\n");
+ for (i=0; i<7; i++)
+ printk("%.8x %.8x %.8x %.8x\n", rga_read(0x100 + i*16 + 0),
+ rga_read(0x100 + i*16 + 4), rga_read(0x100 + i*16 + 8), rga_read(0x100 + i*16 + 12));
+ printk("%.8x %.8x\n", rga_read(0x100 + i*16 + 0), rga_read(0x100 + i*16 + 4));
+ }
+#endif
+ }
+ }
+}
+
+
+
+
+/* Caller must hold rga_service.lock */
+static void rga_del_running_list(void)
+{
+ struct rga_reg *reg;
+
+ while(!list_empty(&rga_service.running))
+ {
+ reg = list_entry(rga_service.running.next, struct rga_reg, status_link);
+
+ if(reg->MMU_len != 0)
+ {
+ if (rga_mmu_buf.back + reg->MMU_len > 2*rga_mmu_buf.size)
+ rga_mmu_buf.back = reg->MMU_len + rga_mmu_buf.size;
+ else
+ rga_mmu_buf.back += reg->MMU_len;
+ }
+
+ atomic_sub(1, ®->session->task_running);
+ atomic_sub(1, &rga_service.total_running);
+
+ if(list_empty(®->session->waiting))
+ {
+ atomic_set(®->session->done, 1);
+ wake_up(®->session->wait);
+ }
+
+ rga_reg_deinit(reg);
+ }
+}
+
+/* Caller must hold rga_service.lock */
+static void rga_del_running_list_timeout(void)
+{
+ struct rga_reg *reg;
+
+ while(!list_empty(&rga_service.running))
+ {
+ reg = list_entry(rga_service.running.next, struct rga_reg, status_link);
+
+ if(reg->MMU_len != 0)
+ {
+ if (rga_mmu_buf.back + reg->MMU_len > 2*rga_mmu_buf.size)
+ rga_mmu_buf.back = reg->MMU_len + rga_mmu_buf.size;
+ else
+ rga_mmu_buf.back += reg->MMU_len;
+ }
+
+ atomic_sub(1, ®->session->task_running);
+ atomic_sub(1, &rga_service.total_running);
+
+ //printk("RGA soft reset for timeout process\n");
+ rga_soft_reset();
+
+
+ #if 0
+ printk("RGA_INT is %.8x\n", rga_read(RGA_INT));
+ printk("reg->session->task_running = %d\n", atomic_read(®->session->task_running));
+ printk("rga_service.total_running = %d\n", atomic_read(&rga_service.total_running));
+
+ print_info(®->req);
+
+ {
+ uint32_t *p, i;
+ p = reg->cmd_reg;
+ for (i=0; i<7; i++)
+ printk("%.8x %.8x %.8x %.8x\n", p[0 + i*4], p[1+i*4], p[2 + i*4], p[3 + i*4]);
+
+ }
+ #endif
+
+ if(list_empty(®->session->waiting))
+ {
+ atomic_set(®->session->done, 1);
+ wake_up(®->session->wait);
+ }
+
+ rga_reg_deinit(reg);
+ }
+}
+
+
+static void rga_mem_addr_sel(struct rga_req *req)
+{
+ switch(req->src.format)
+ {
+ case RK_FORMAT_YCbCr_422_SP:
+ break;
+ case RK_FORMAT_YCbCr_422_P :
+ break;
+ case RK_FORMAT_YCbCr_420_SP :
+ if((req->src.yrgb_addr > 0xc0000000) && (req->src.uv_addr > 0xc0000000)
+ && (req->dst.yrgb_addr > 0xc0000000))
+ {
+ req->src.yrgb_addr = req->src.yrgb_addr - 0x60000000;
+ req->src.uv_addr = req->src.uv_addr - 0x60000000;
+ req->dst.yrgb_addr = req->dst.yrgb_addr - 0x60000000;
+ req->mmu_info.mmu_en = 0;
+ req->mmu_info.mmu_flag &= 0xfffe;
+ }
+ break;
+ case RK_FORMAT_YCbCr_420_P :
+ break;
+ case RK_FORMAT_YCrCb_422_SP :
+ break;
+ case RK_FORMAT_YCrCb_422_P :
+ break;
+ case RK_FORMAT_YCrCb_420_SP :
+ break;
+ case RK_FORMAT_YCrCb_420_P :
+ break;
+ default :
+ break;
+ }
+
+}
+
+static int rga_convert_dma_buf(struct rga_req *req)
+{
+ struct ion_handle *hdl;
+ ion_phys_addr_t phy_addr;
+ size_t len;
+ int ret;
+ uint32_t src_offset, dst_offset;
+
+ req->sg_src = NULL;
+ req->sg_dst = NULL;
+\r
+ src_offset = req->line_draw_info.flag;
+ dst_offset = req->line_draw_info.line_width;
+
+ if(req->src.yrgb_addr) {
+ hdl = ion_import_dma_buf(drvdata->ion_client, req->src.yrgb_addr);
+ if (IS_ERR(hdl)) {
+ ret = PTR_ERR(hdl);
+ printk("RGA2 ERROR ion buf handle\n");
+ return ret;
+ }
+ if ((req->mmu_info.mmu_flag >> 8) & 1) {
+ req->sg_src = ion_sg_table(drvdata->ion_client, hdl);
+ req->src.yrgb_addr = req->src.uv_addr;
+ req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h);
+ req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4;
+ }
+ else {
+ ion_phys(drvdata->ion_client, hdl, &phy_addr, &len);
+ req->src.yrgb_addr = phy_addr + src_offset;
+ req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h);
+ req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4;
+ }
+ ion_free(drvdata->ion_client, hdl);
+ }
+ else {
+ req->src.yrgb_addr = req->src.uv_addr;
+ req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h);
+ req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4;
+ }
+
+ if(req->dst.yrgb_addr) {
+ hdl = ion_import_dma_buf(drvdata->ion_client, req->dst.yrgb_addr);
+ if (IS_ERR(hdl)) {
+ ret = PTR_ERR(hdl);
+ printk("RGA2 ERROR ion buf handle\n");
+ return ret;
+ }
+ if ((req->mmu_info.mmu_flag >> 10) & 1) {
+ req->sg_dst = ion_sg_table(drvdata->ion_client, hdl);
+ req->dst.yrgb_addr = req->dst.uv_addr;
+ req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h);
+ req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4;
+ }
+ else {
+ ion_phys(drvdata->ion_client, hdl, &phy_addr, &len);
+ req->dst.yrgb_addr = phy_addr + dst_offset;
+ req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h);
+ req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4;
+ }
+ ion_free(drvdata->ion_client, hdl);
+ }
+ else {
+ req->dst.yrgb_addr = req->dst.uv_addr;
+ req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h);
+ req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4;
+ }
+
+ return 0;
+}
+
+
+static int rga_blit(rga_session *session, struct rga_req *req)
+{
+ int ret = -1;
+ int num = 0;
+ struct rga_reg *reg;
+ struct rga_req req2;
+
+ uint32_t saw, sah, daw, dah;
+
+ saw = req->src.act_w;
+ sah = req->src.act_h;
+ daw = req->dst.act_w;
+ dah = req->dst.act_h;
+
+ #if RGA_TEST
+ print_info(req);
+ #endif
+
+ if(rga_convert_dma_buf(req)) {
+ printk("RGA : DMA buf copy error\n");
+ return -EFAULT;
+ }
+
+ do {
+ if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah))) {
+ /* generate 2 cmd for pre scale */
+
+ ret = rga_check_param(req);
+ if(ret == -EINVAL) {
+ printk("req 0 argument is inval\n");
+ break;
+ }
+
+ ret = RGA_gen_two_pro(req, &req2);
+ if(ret == -EINVAL) {
+ break;
+ }
+
+ ret = rga_check_param(req);
+ if(ret == -EINVAL) {
+ printk("req 1 argument is inval\n");
+ break;
+ }
+
+ ret = rga_check_param(&req2);
+ if(ret == -EINVAL) {
+ printk("req 2 argument is inval\n");
+ break;
+ }
+
+ reg = rga_reg_init_2(session, req, &req2);
+ if(reg == NULL) {
+ break;
+ }
+ num = 2;
+
+ }
+ else {
+ /* check value if legal */
+ ret = rga_check_param(req);
+ if(ret == -EINVAL) {
+ printk("req argument is inval\n");
+ break;
+ }
+
+ if(req->render_mode == bitblt_mode)
+ rga_mem_addr_sel(req);
+
+ reg = rga_reg_init(session, req);
+ if(reg == NULL) {
+ break;
+ }
+ num = 1;
+ }
+
+ mutex_lock(&rga_service.lock);
+ atomic_add(num, &rga_service.total_running);
+ rga_try_set_reg();
+ mutex_unlock(&rga_service.lock);
+
+ return 0;
+ }
+ while(0);
+
+ return -EFAULT;
+}
+
+static int rga_blit_async(rga_session *session, struct rga_req *req)
+{
+ int ret = -1;
+
+ #if RGA_TEST
+ printk("*** rga_blit_async proc ***\n");
+ #endif
+
+ atomic_set(&session->done, 0);
+ ret = rga_blit(session, req);
+ return ret;
+}
+
+static int rga_blit_sync(rga_session *session, struct rga_req *req)
+{
+ int ret = -1;
+ int ret_timeout = 0;
+
+ #if RGA_TEST
+ printk("*** rga_blit_sync proc ***\n");
+ #endif
+
+ atomic_set(&session->done, 0);
+ ret = rga_blit(session, req);
+ if(ret < 0)
+ return ret;
+
+ ret_timeout = wait_event_timeout(session->wait, atomic_read(&session->done), RGA_TIMEOUT_DELAY);
+
+ if (unlikely(ret_timeout< 0)) {
+ mutex_lock(&rga_service.lock);
+ rga_del_running_list();
+ mutex_unlock(&rga_service.lock);
+ ret = ret_timeout;
+ }
+ else if (0 == ret_timeout) {
+ mutex_lock(&rga_service.lock);
+ rga_del_running_list_timeout();
+ rga_try_set_reg();
+ mutex_unlock(&rga_service.lock);
+ ret = -ETIMEDOUT;
+ }
+
+ #if RGA_TEST_TIME
+ rga_end = ktime_get();
+ rga_end = ktime_sub(rga_end, rga_start);
+ printk("sync one cmd end time %d\n", (int)ktime_to_us(rga_end));
+ #endif
+
+ return ret;
+}
+
+
+static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg)
+{
+ struct rga_req req;
+ int ret = 0;
+ rga_session *session;
+
+ mutex_lock(&rga_service.mutex);
+
+ session = (rga_session *)file->private_data;
+
+ if (NULL == session) {
+ printk("%s [%d] rga thread session is null\n",__FUNCTION__,__LINE__);
+ mutex_unlock(&rga_service.mutex);
+ return -EINVAL;
+ }
+
+ memset(&req, 0x0, sizeof(req));
+
+ switch (cmd) {
+ case RGA_BLIT_SYNC:
+ if (unlikely(copy_from_user(&req, (struct rga_req*)arg, sizeof(struct rga_req))))
+ {
+ ERR("copy_from_user failed\n");
+ ret = -EFAULT;
+ break;
+ }
+ ret = rga_blit_sync(session, &req);
+ break;
+ case RGA_BLIT_ASYNC:
+ if (unlikely(copy_from_user(&req, (struct rga_req*)arg, sizeof(struct rga_req))))
+ {
+ ERR("copy_from_user failed\n");
+ ret = -EFAULT;
+ break;
+ }
+
+ if((atomic_read(&rga_service.total_running) > 16))
+ {
+ ret = rga_blit_sync(session, &req);
+ }
+ else
+ {
+ ret = rga_blit_async(session, &req);
+ }
+ break;
+ case RGA_FLUSH:
+ ret = rga_flush(session, arg);
+ break;
+ case RGA_GET_RESULT:
+ ret = rga_get_result(session, arg);
+ break;
+ case RGA_GET_VERSION:
+ ret = copy_to_user((void *)arg, RGA_VERSION, sizeof(RGA_VERSION));
+ //ret = 0;
+ break;
+ default:
+ ERR("unknown ioctl cmd!\n");
+ ret = -EINVAL;
+ break;
+ }
+
+ mutex_unlock(&rga_service.mutex);
+
+ return ret;
+}
+
+
+long rga_ioctl_kernel(struct rga_req *req)
+{
+ int ret = 0;
+ if (!rga_ioctl_kernel_p) {
+ printk("rga_ioctl_kernel_p is NULL\n");
+ return -1;
+ }
+ else {
+ ret = (*rga_ioctl_kernel_p)(req);
+ return ret;
+ }
+}
+
+
+long rga_ioctl_kernel_imp(struct rga_req *req)
+{
+ int ret = 0;
+ rga_session *session;
+
+ mutex_lock(&rga_service.mutex);
+
+ session = &rga_session_global;
+
+ if (NULL == session) {
+ printk("%s [%d] rga thread session is null\n",__FUNCTION__,__LINE__);
+ mutex_unlock(&rga_service.mutex);
+ return -EINVAL;
+ }
+
+ ret = rga_blit_sync(session, req);
+
+ mutex_unlock(&rga_service.mutex);
+
+ return ret;
+}
+
+
+static int rga_open(struct inode *inode, struct file *file)
+{
+ rga_session *session = kzalloc(sizeof(rga_session), GFP_KERNEL);
+ if (NULL == session) {
+ pr_err("unable to allocate memory for rga_session.");
+ return -ENOMEM;
+ }
+
+ session->pid = current->pid;
+ //printk(KERN_DEBUG "+");
+
+ INIT_LIST_HEAD(&session->waiting);
+ INIT_LIST_HEAD(&session->running);
+ INIT_LIST_HEAD(&session->list_session);
+ init_waitqueue_head(&session->wait);
+ mutex_lock(&rga_service.lock);
+ list_add_tail(&session->list_session, &rga_service.session);
+ mutex_unlock(&rga_service.lock);
+ atomic_set(&session->task_running, 0);
+ atomic_set(&session->num_done, 0);
+
+ file->private_data = (void *)session;
+
+ //DBG("*** rga dev opened by pid %d *** \n", session->pid);
+ return nonseekable_open(inode, file);
+
+}
+
+static int rga_release(struct inode *inode, struct file *file)
+{
+ int task_running;
+ rga_session *session = (rga_session *)file->private_data;
+ if (NULL == session)
+ return -EINVAL;
+ //printk(KERN_DEBUG "-");
+ task_running = atomic_read(&session->task_running);
+
+ if (task_running)
+ {
+ pr_err("rga_service session %d still has %d task running when closing\n", session->pid, task_running);
+ msleep(100);
+ /*ͬ²½*/
+ }
+
+ wake_up(&session->wait);
+ mutex_lock(&rga_service.lock);
+ list_del(&session->list_session);
+ rga_service_session_clear(session);
+ kfree(session);
+ mutex_unlock(&rga_service.lock);
+
+ //DBG("*** rga dev close ***\n");
+ return 0;
+}
+
+static irqreturn_t rga_irq_thread(int irq, void *dev_id)
+{
+ mutex_lock(&rga_service.lock);
+ if (rga_service.enable) {
+ rga_del_running_list();
+ rga_try_set_reg();
+ }
+ mutex_unlock(&rga_service.lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t rga_irq(int irq, void *dev_id)
+{
+ /*clear INT */
+ rga_write(rga_read(RGA_INT) | (0x1<<6) | (0x1<<7) | (0x1<<4), RGA_INT);
+
+ return IRQ_WAKE_THREAD;
+}
+
+struct file_operations rga_fops = {
+ .owner = THIS_MODULE,
+ .open = rga_open,
+ .release = rga_release,
+ .unlocked_ioctl = rga_ioctl,
+};
+
+static struct miscdevice rga_dev ={
+ .minor = RGA_MAJOR,
+ .name = "rga",
+ .fops = &rga_fops,
+};
+
+
+#if defined(CONFIG_OF)
+static const struct of_device_id rockchip_rga_dt_ids[] = {
+ { .compatible = "rockchip,rk312x-rga", },
+ {},
+};
+#endif
+
+static int rga_drv_probe(struct platform_device *pdev)
+{
+ struct rga_drvdata *data;
+ struct resource *res;
+ //struct device_node *np = pdev->dev.of_node;
+ int ret = 0;
+
+ mutex_init(&rga_service.lock);
+ mutex_init(&rga_service.mutex);
+ atomic_set(&rga_service.total_running, 0);
+ rga_service.enable = false;
+
+ rga_ioctl_kernel_p = rga_ioctl_kernel_imp;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(struct rga_drvdata), GFP_KERNEL);
+ if(! data) {
+ ERR("failed to allocate driver data.\n");
+ return -ENOMEM;
+ }
+
+ INIT_DELAYED_WORK(&data->power_off_work, rga_power_off_work);
+ wake_lock_init(&data->wake_lock, WAKE_LOCK_SUSPEND, "rga");
+
+ //data->pd_rga = devm_clk_get(&pdev->dev, "pd_rga");
+ data->aclk_rga = devm_clk_get(&pdev->dev, "aclk_rga");
+ data->hclk_rga = devm_clk_get(&pdev->dev, "hclk_rga");
+
+ /* map the registers */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->rga_base = devm_ioremap_resource(&pdev->dev, res);
+ if (!data->rga_base) {
+ ERR("rga ioremap failed\n");
+ ret = -ENOENT;
+ goto err_ioremap;
+ }
+
+ /* get the IRQ */
+ data->irq = ret = platform_get_irq(pdev, 0);
+ if (ret <= 0) {
+ ERR("failed to get rga irq resource (%d).\n", data->irq);
+ ret = data->irq;
+ goto err_irq;
+ }
+
+ /* request the IRQ */
+ //ret = request_threaded_irq(data->irq, rga_irq, rga_irq_thread, 0, "rga", pdev);
+ ret = devm_request_threaded_irq(&pdev->dev, data->irq, rga_irq, rga_irq_thread, 0, "rga", data);
+ if (ret)
+ {
+ ERR("rga request_irq failed (%d).\n", ret);
+ goto err_irq;
+ }
+
+ platform_set_drvdata(pdev, data);
+ drvdata = data;
+
+ #if defined(CONFIG_ION_ROCKCHIP)
+ data->ion_client = rockchip_ion_client_create("rga");
+ if (IS_ERR(data->ion_client)) {
+ dev_err(&pdev->dev, "failed to create ion client for rga");
+ return PTR_ERR(data->ion_client);
+ } else {
+ dev_info(&pdev->dev, "rga ion client create success!\n");
+ }