+
+ /// \brief Return a list of registers that are potentially read by any
+ /// instance of this machine instruction. For example, on X86, the "adc"
+ /// instruction adds two register operands and adds the carry bit in from the
+ /// flags register. In this case, the instruction is marked as implicitly
+ /// reading the flags. Likewise, the variable shift instruction on X86 is
+ /// marked as implicitly reading the 'CL' register, which it always does.
+ ///
+ /// This method returns null if the instruction has no implicit uses.
+ const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
+
+ /// \brief Return the number of implicit uses this instruction has.
+ unsigned getNumImplicitUses() const {
+ if (!ImplicitUses)
+ return 0;
+ unsigned i = 0;
+ for (; ImplicitUses[i]; ++i) /*empty*/
+ ;
+ return i;
+ }
+
+ /// \brief Return a list of registers that are potentially written by any
+ /// instance of this machine instruction. For example, on X86, many
+ /// instructions implicitly set the flags register. In this case, they are
+ /// marked as setting the FLAGS. Likewise, many instructions always deposit
+ /// their result in a physical register. For example, the X86 divide
+ /// instruction always deposits the quotient and remainder in the EAX/EDX
+ /// registers. For that instruction, this will return a list containing the
+ /// EAX/EDX/EFLAGS registers.
+ ///
+ /// This method returns null if the instruction has no implicit defs.
+ const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
+
+ /// \brief Return the number of implicit defs this instruct has.
+ unsigned getNumImplicitDefs() const {
+ if (!ImplicitDefs)
+ return 0;
+ unsigned i = 0;
+ for (; ImplicitDefs[i]; ++i) /*empty*/
+ ;
+ return i;
+ }
+
+ /// \brief Return true if this instruction implicitly
+ /// uses the specified physical register.
+ bool hasImplicitUseOfPhysReg(unsigned Reg) const {
+ if (const MCPhysReg *ImpUses = ImplicitUses)
+ for (; *ImpUses; ++ImpUses)
+ if (*ImpUses == Reg)
+ return true;
+ return false;
+ }
+
+ /// \brief Return true if this instruction implicitly
+ /// defines the specified physical register.
+ bool hasImplicitDefOfPhysReg(unsigned Reg,
+ const MCRegisterInfo *MRI = nullptr) const;
+
+ /// \brief Return the scheduling class for this instruction. The
+ /// scheduling class is an index into the InstrItineraryData table. This
+ /// returns zero if there is no known scheduling information for the
+ /// instruction.
+ unsigned getSchedClass() const { return SchedClass; }
+
+ /// \brief Return the number of bytes in the encoding of this instruction,
+ /// or zero if the encoding size cannot be known from the opcode.
+ unsigned getSize() const { return Size; }
+
+ /// \brief Find the index of the first operand in the
+ /// operand list that is used to represent the predicate. It returns -1 if
+ /// none is found.
+ int findFirstPredOperandIdx() const {
+ if (isPredicable()) {
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
+ if (OpInfo[i].isPredicate())
+ return i;
+ }
+ return -1;
+ }
+
+private:
+
+ /// \brief Return true if this instruction defines the specified physical
+ /// register, either explicitly or implicitly.
+ bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
+ const MCRegisterInfo &RI) const;