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Include the Target& in the TargetMachineRegisterEntry.
[oota-llvm.git]
/
include
/
llvm
/
Target
/
TargetSelectionDAG.td
diff --git
a/include/llvm/Target/TargetSelectionDAG.td
b/include/llvm/Target/TargetSelectionDAG.td
index 2586e65d3971e7221ebfbabae0a0de9864627c63..364d4d0d3cc0f439aa68afbf7da4d0d44a9609d6 100644
(file)
--- a/
include/llvm/Target/TargetSelectionDAG.td
+++ b/
include/llvm/Target/TargetSelectionDAG.td
@@
-216,8
+216,6
@@
def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
-def SDNPInI1 : SDNodeProperty; // Read an extra I1 operand
-def SDNPOutI1 : SDNodeProperty; // Write an extra I1 result
//===----------------------------------------------------------------------===//
// Selection DAG Node definitions.
//===----------------------------------------------------------------------===//
// Selection DAG Node definitions.
@@
-230,6
+228,7
@@
class SDNode<string opcode, SDTypeProfile typeprof,
SDTypeProfile TypeProfile = typeprof;
}
SDTypeProfile TypeProfile = typeprof;
}
+// Special TableGen-recognized dag nodes
def set;
def implicit;
def parallel;
def set;
def implicit;
def parallel;
@@
-291,13
+290,13
@@
def or : SDNode<"ISD::OR" , SDTIntBinOp,
def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
- [SDNPCommutative, SDNPOut
I1
]>;
+ [SDNPCommutative, SDNPOut
Flag
]>;
def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
- [SDNPCommutative, SDNP
InI1, SDNPOutI1
]>;
+ [SDNPCommutative, SDNP
OutFlag, SDNPInFlag
]>;
def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
- [SDNPOut
I1
]>;
+ [SDNPOut
Flag
]>;
def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
- [SDNP
InI1, SDNPOutI1
]>;
+ [SDNP
OutFlag, SDNPInFlag
]>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;