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[X86][Haswell][SchedModel] Add architecture specific scheduling models.
[oota-llvm.git]
/
lib
/
CodeGen
/
ExecutionDepsFix.cpp
diff --git
a/lib/CodeGen/ExecutionDepsFix.cpp
b/lib/CodeGen/ExecutionDepsFix.cpp
index 031f19c135a97df9a81c83ad9f5f73e0a6e24031..287cf55082cc753b39f60e7d2919b6148c30451d 100644
(file)
--- a/
lib/CodeGen/ExecutionDepsFix.cpp
+++ b/
lib/CodeGen/ExecutionDepsFix.cpp
@@
-20,10
+20,9
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "execution-fix"
#include "llvm/CodeGen/Passes.h"
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/ADT/PostOrderIterator.h"
-#include "llvm/CodeGen/Live
RegUnit
s.h"
+#include "llvm/CodeGen/Live
PhysReg
s.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Allocator.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Allocator.h"
@@
-31,8
+30,12
@@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+
using namespace llvm;
using namespace llvm;
+#define DEBUG_TYPE "execution-fix"
+
/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
/// of execution domains.
///
/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
/// of execution domains.
///
@@
-100,7
+103,7
@@
struct DomainValue {
// Clear this DomainValue and point to next which has all its data.
void clear() {
AvailableDomains = 0;
// Clear this DomainValue and point to next which has all its data.
void clear() {
AvailableDomains = 0;
- Next =
0
;
+ Next =
nullptr
;
Instrs.clear();
}
};
Instrs.clear();
}
};
@@
-141,7
+144,7
@@
class ExeDepsFix : public MachineFunctionPass {
std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
/// Storage for register unit liveness.
std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
/// Storage for register unit liveness.
- Live
RegUnits LiveUnits
;
+ Live
PhysRegs LiveRegSet
;
/// Current instruction number.
/// The first instruction in each basic block is 0.
/// Current instruction number.
/// The first instruction in each basic block is 0.
@@
-155,14
+158,14
@@
public:
ExeDepsFix(const TargetRegisterClass *rc)
: MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
ExeDepsFix(const TargetRegisterClass *rc)
: MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
- v
irtual void getAnalysisUsage(AnalysisUsage &AU) const
{
+ v
oid getAnalysisUsage(AnalysisUsage &AU) const override
{
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
-
virtual bool runOnMachineFunction(MachineFunction &MF)
;
+
bool runOnMachineFunction(MachineFunction &MF) override
;
-
virtual const char *getPassName() const
{
+
const char *getPassName() const override
{
return "Execution dependency fix";
}
return "Execution dependency fix";
}
@@
-275,7
+278,7
@@
void ExeDepsFix::kill(int rx) {
return;
release(LiveRegs[rx].Value);
return;
release(LiveRegs[rx].Value);
- LiveRegs[rx].Value =
0
;
+ LiveRegs[rx].Value =
nullptr
;
}
/// Force register rx into domain.
}
/// Force register rx into domain.
@@
-352,7
+355,7
@@
void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
// Set up UndefReads to track undefined register reads.
UndefReads.clear();
// Set up UndefReads to track undefined register reads.
UndefReads.clear();
- Live
Units
.clear();
+ Live
RegSet
.clear();
// Set up LiveRegs to represent registers entering MBB.
if (!LiveRegs)
// Set up LiveRegs to represent registers entering MBB.
if (!LiveRegs)
@@
-360,7
+363,7
@@
void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
// Default values are 'nothing happened a long time ago'.
for (unsigned rx = 0; rx != NumRegs; ++rx) {
// Default values are 'nothing happened a long time ago'.
for (unsigned rx = 0; rx != NumRegs; ++rx) {
- LiveRegs[rx].Value =
0
;
+ LiveRegs[rx].Value =
nullptr
;
LiveRegs[rx].Def = -(1 << 20);
}
LiveRegs[rx].Def = -(1 << 20);
}
@@
-404,7
+407,7
@@
void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
// We have a live DomainValue from more than one predecessor.
if (LiveRegs[rx].Value->isCollapsed()) {
// We have a live DomainValue from more than one predecessor.
if (LiveRegs[rx].Value->isCollapsed()) {
- // We are already collapsed, but predecessor is not. Force
him
.
+ // We are already collapsed, but predecessor is not. Force
it
.
unsigned Domain = LiveRegs[rx].Value->getFirstDomain();
if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
collapse(pdv, Domain);
unsigned Domain = LiveRegs[rx].Value->getFirstDomain();
if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
collapse(pdv, Domain);
@@
-440,7
+443,7
@@
void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
release(LiveRegs[i].Value);
delete[] LiveRegs;
}
release(LiveRegs[i].Value);
delete[] LiveRegs;
}
- LiveRegs =
0
;
+ LiveRegs =
nullptr
;
}
void ExeDepsFix::visitInstr(MachineInstr *MI) {
}
void ExeDepsFix::visitInstr(MachineInstr *MI) {
@@
-547,21
+550,19
@@
void ExeDepsFix::processUndefReads(MachineBasicBlock *MBB) {
return;
// Collect this block's live out register units.
return;
// Collect this block's live out register units.
- LiveUnits.init(TRI);
- for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
- SE = MBB->succ_end(); SI != SE; ++SI) {
- LiveUnits.addLiveIns(*SI, *TRI);
- }
+ LiveRegSet.init(TRI);
+ LiveRegSet.addLiveOuts(MBB);
+
MachineInstr *UndefMI = UndefReads.back().first;
unsigned OpIdx = UndefReads.back().second;
for (MachineBasicBlock::reverse_iterator I = MBB->rbegin(), E = MBB->rend();
I != E; ++I) {
MachineInstr *UndefMI = UndefReads.back().first;
unsigned OpIdx = UndefReads.back().second;
for (MachineBasicBlock::reverse_iterator I = MBB->rbegin(), E = MBB->rend();
I != E; ++I) {
- // Update liveness, including the current instrucion's defs.
- Live
Units.stepBackward(*I, *TR
I);
+ // Update liveness, including the current instruc
t
ion's defs.
+ Live
RegSet.stepBackward(*
I);
if (UndefMI == &*I) {
if (UndefMI == &*I) {
- if (!Live
Units.contains(UndefMI->getOperand(OpIdx).getReg(), *TRI
))
+ if (!Live
RegSet.contains(UndefMI->getOperand(OpIdx).getReg()
))
TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
UndefReads.pop_back();
TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
UndefReads.pop_back();
@@
-666,7
+667,7
@@
void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
// doms are now sorted in order of appearance. Try to merge them all, giving
// priority to the latest ones.
// doms are now sorted in order of appearance. Try to merge them all, giving
// priority to the latest ones.
- DomainValue *dv =
0
;
+ DomainValue *dv =
nullptr
;
while (!Regs.empty()) {
if (!dv) {
dv = Regs.pop_back_val().Value;
while (!Regs.empty()) {
if (!dv) {
dv = Regs.pop_back_val().Value;
@@
-714,9
+715,9
@@
void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
- TII = MF->get
T
arget().getInstrInfo();
- TRI = MF->get
T
arget().getRegisterInfo();
- LiveRegs =
0
;
+ TII = MF->get
Subt
arget().getInstrInfo();
+ TRI = MF->get
Subt
arget().getRegisterInfo();
+ LiveRegs =
nullptr
;
assert(NumRegs == RC->getNumRegs() && "Bad regclass");
DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: "
assert(NumRegs == RC->getNumRegs() && "Bad regclass");
DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: "