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inline AsmPrinter::getCurrentFunctionEHName into its only caller.
[oota-llvm.git]
/
lib
/
CodeGen
/
LLVMTargetMachine.cpp
diff --git
a/lib/CodeGen/LLVMTargetMachine.cpp
b/lib/CodeGen/LLVMTargetMachine.cpp
index c60f9c7e41062407b7a6b4d11912d32b8e3b6e55..5b6cfdc989f0f133ae660f53800f31a756273429 100644
(file)
--- a/
lib/CodeGen/LLVMTargetMachine.cpp
+++ b/
lib/CodeGen/LLVMTargetMachine.cpp
@@
-15,12
+15,12
@@
#include "llvm/PassManager.h"
#include "llvm/Pass.h"
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/PassManager.h"
#include "llvm/Pass.h"
#include "llvm/Assembly/PrintModulePass.h"
-#include "llvm/
Analysis/LoopPass
.h"
+#include "llvm/
CodeGen/AsmPrinter
.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/
Target/Target
AsmInfo.h"
+#include "llvm/
MC/MC
AsmInfo.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/CommandLine.h"
@@
-51,10
+51,19
@@
DisablePostRAScheduler("disable-post-RA-scheduler",
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
-// able to enable or disable fast-isel independently from -
fast
.
+// able to enable or disable fast-isel independently from -
O0
.
static cl::opt<cl::boolOrDefault>
EnableFastISelOption("fast-isel", cl::Hidden,
static cl::opt<cl::boolOrDefault>
EnableFastISelOption("fast-isel", cl::Hidden,
- cl::desc("Enable the experimental \"fast\" instruction selector"));
+ cl::desc("Enable the \"fast\" instruction selector"));
+
+
+LLVMTargetMachine::LLVMTargetMachine(const Target &T,
+ const std::string &TargetTriple)
+ : TargetMachine(T) {
+ AsmInfo = T.createAsmInfo(TargetTriple);
+}
+
+
FileModel::Model
LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
FileModel::Model
LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
@@
-69,10
+78,10
@@
LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
PM.add(createDebugLabelFoldingPass());
if (PrintMachineCode)
PM.add(createDebugLabelFoldingPass());
if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(
cerr
));
+ PM.add(createMachineFunctionPrinterPass(
errs()
));
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(
cerr
));
+ PM.add(createMachineFunctionPrinterPass(
errs()
));
if (OptLevel != CodeGenOpt::None)
PM.add(createCodePlacementOptPass());
if (OptLevel != CodeGenOpt::None)
PM.add(createCodePlacementOptPass());
@@
-98,7
+107,8
@@
bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
bool Verbose,
formatted_raw_ostream &Out) {
CodeGenOpt::Level OptLevel,
bool Verbose,
formatted_raw_ostream &Out) {
- FunctionPass *Printer = getTarget().createAsmPrinter(Out, *this, Verbose);
+ FunctionPass *Printer =
+ getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
if (!Printer)
return true;
if (!Printer)
return true;
@@
-168,7
+178,7
@@
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
return true;
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
return true;
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(
cerr
));
+ PM.add(createMachineFunctionPrinterPass(
errs()
));
addCodeEmitter(PM, OptLevel, MCE);
if (PrintEmittedAsm)
addCodeEmitter(PM, OptLevel, MCE);
if (PrintEmittedAsm)
@@
-193,7
+203,7
@@
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
return true;
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
return true;
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(
cerr
));
+ PM.add(createMachineFunctionPrinterPass(
errs()
));
addCodeEmitter(PM, OptLevel, JCE);
if (PrintEmittedAsm)
addCodeEmitter(PM, OptLevel, JCE);
if (PrintEmittedAsm)
@@
-207,7
+217,7
@@
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
static void printAndVerify(PassManagerBase &PM,
bool allowDoubleDefs = false) {
if (PrintMachineCode)
static void printAndVerify(PassManagerBase &PM,
bool allowDoubleDefs = false) {
if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(
cerr
));
+ PM.add(createMachineFunctionPrinterPass(
errs()
));
if (VerifyMachineCode)
PM.add(createMachineVerifierPass(allowDoubleDefs));
if (VerifyMachineCode)
PM.add(createMachineVerifierPass(allowDoubleDefs));
@@
-229,10
+239,13
@@
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
// Turn exception handling constructs into something the code generators can
// handle.
// Turn exception handling constructs into something the code generators can
// handle.
- switch (get
Target
AsmInfo()->getExceptionHandlingType())
+ switch (get
MC
AsmInfo()->getExceptionHandlingType())
{
{
- // SjLj piggy-backs on dwarf for this bit
case ExceptionHandling::SjLj:
case ExceptionHandling::SjLj:
+ // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
+ PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
+ PM.add(createSjLjEHPass(getTargetLowering()));
+ break;
case ExceptionHandling::Dwarf:
PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
break;
case ExceptionHandling::Dwarf:
PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
break;
@@
-281,7
+294,7
@@
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
// Run pre-ra passes.
if (addPreRegAlloc(PM, OptLevel))
// Run pre-ra passes.
if (addPreRegAlloc(PM, OptLevel))
- printAndVerify(PM);
+ printAndVerify(PM
, /* allowDoubleDefs= */ true
);
// Perform register allocation.
PM.add(createRegisterAllocator());
// Perform register allocation.
PM.add(createRegisterAllocator());
@@
-321,7
+334,7
@@
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
printAndVerify(PM);
if (PrintGCInfo)
printAndVerify(PM);
if (PrintGCInfo)
- PM.add(createGCInfoPrinter(
*cerr
));
+ PM.add(createGCInfoPrinter(
errs()
));
return false;
}
return false;
}