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[X86][Haswell][SchedModel] Add architecture specific scheduling models.
[oota-llvm.git]
/
lib
/
CodeGen
/
LiveRegMatrix.cpp
diff --git
a/lib/CodeGen/LiveRegMatrix.cpp
b/lib/CodeGen/LiveRegMatrix.cpp
index 7f797beec8e2564345735a5c074a8ab44d8afd33..dbe3e1ea7890f89ad98b6daef706ea00de57dbe4 100644
(file)
--- a/
lib/CodeGen/LiveRegMatrix.cpp
+++ b/
lib/CodeGen/LiveRegMatrix.cpp
@@
-11,7
+11,6
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "regalloc"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "RegisterCoalescer.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "RegisterCoalescer.h"
#include "llvm/ADT/Statistic.h"
@@
-25,6
+24,8
@@
using namespace llvm;
using namespace llvm;
+#define DEBUG_TYPE "regalloc"
+
STATISTIC(NumAssigned , "Number of registers assigned");
STATISTIC(NumUnassigned , "Number of registers unassigned");
STATISTIC(NumAssigned , "Number of registers assigned");
STATISTIC(NumUnassigned , "Number of registers unassigned");
@@
-47,7
+48,7
@@
void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const {
}
bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
}
bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
- TRI = MF.get
T
arget().getRegisterInfo();
+ TRI = MF.get
Subt
arget().getRegisterInfo();
MRI = &MF.getRegInfo();
LIS = &getAnalysis<LiveIntervals>();
VRM = &getAnalysis<VirtRegMap>();
MRI = &MF.getRegInfo();
LIS = &getAnalysis<LiveIntervals>();
VRM = &getAnalysis<VirtRegMap>();