+ // Both operands are sub registers. Check if they share a register class.
+ unsigned SrcIdx, DefIdx;
+ if (SrcSubReg && DefSubReg)
+ return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
+ SrcIdx, DefIdx) != NULL;
+ // At most one of the register is a sub register, make it Src to avoid
+ // duplicating the test.
+ if (!SrcSubReg) {
+ std::swap(DefSubReg, SrcSubReg);
+ std::swap(DefRC, SrcRC);
+ }
+
+ // One of the register is a sub register, check if we can get a superclass.
+ if (SrcSubReg)
+ return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != NULL;
+ // Plain copy.
+ return TRI.getCommonSubClass(DefRC, SrcRC) != NULL;
+}
+
+/// \brief Get the index of the definition and source for \p Copy
+/// instruction.
+/// \pre Copy.isCopy() or Copy.isBitcast().
+/// \return True if the Copy instruction has only one register source
+/// and one register definition. Otherwise, \p DefIdx and \p SrcIdx
+/// are invalid.
+static bool getCopyOrBitcastDefUseIdx(const MachineInstr &Copy,
+ unsigned &DefIdx, unsigned &SrcIdx) {
+ assert((Copy.isCopy() || Copy.isBitcast()) && "Wrong operation type.");
+ if (Copy.isCopy()) {
+ // Copy instruction are supposed to be: Def = Src.
+ if (Copy.getDesc().getNumOperands() != 2)
+ return false;
+ DefIdx = 0;
+ SrcIdx = 1;
+ assert(Copy.getOperand(DefIdx).isDef() && "Use comes before def!");
+ return true;
+ }
+ // Bitcast case.
+ // Bitcasts with more than one def are not supported.
+ if (Copy.getDesc().getNumDefs() != 1)