-#ifndef NDEBUG
-// Verify each LiveIntervalUnion.
-void RegAllocBase::verify() {
- LiveVirtRegBitSet VisitedVRegs;
- OwningArrayPtr<LiveVirtRegBitSet>
- unionVRegs(new LiveVirtRegBitSet[TRI->getNumRegs()]);
-
- // Verify disjoint unions.
- for (unsigned PhysReg = 0, NumRegs = TRI->getNumRegs(); PhysReg != NumRegs;
- ++PhysReg) {
- DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
- LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
- PhysReg2LiveUnion[PhysReg].verify(VRegs);
- // Union + intersection test could be done efficiently in one pass, but
- // don't add a method to SparseBitVector unless we really need it.
- assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
- VisitedVRegs |= VRegs;
- }
-
- // Verify vreg coverage.
- for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
- unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
- if (MRI->reg_nodbg_empty(Reg))
- continue;
- if (!VRM->hasPhys(Reg)) continue; // spilled?
- LiveInterval &LI = LIS->getInterval(Reg);
- if (LI.empty()) continue; // unionVRegs will only be filled if li is
- // non-empty
- unsigned PhysReg = VRM->getPhys(Reg);
- if (!unionVRegs[PhysReg].test(Reg)) {
- dbgs() << "LiveVirtReg " << PrintReg(Reg, TRI) << " not in union "
- << TRI->getName(PhysReg) << "\n";
- llvm_unreachable("unallocated live vreg");
- }
- }
- // FIXME: I'm not sure how to verify spilled intervals.
-}
-#endif //!NDEBUG
-