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[X86][Haswell][SchedModel] Add architecture specific scheduling models.
[oota-llvm.git]
/
lib
/
CodeGen
/
RegAllocBase.h
diff --git
a/lib/CodeGen/RegAllocBase.h
b/lib/CodeGen/RegAllocBase.h
index 597b1fcb58693b3ce7c01b8d7aa2d2fc14c951a7..bbd79cdce006b5bb7846505b26b2981813c3484e 100644
(file)
--- a/
lib/CodeGen/RegAllocBase.h
+++ b/
lib/CodeGen/RegAllocBase.h
@@
-34,10
+34,9
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_
CODEGEN_REGALLOCBASE
-#define LLVM_
CODEGEN_REGALLOCBASE
+#ifndef LLVM_
LIB_CODEGEN_REGALLOCBASE_H
+#define LLVM_
LIB_CODEGEN_REGALLOCBASE_H
-#include "llvm/ADT/OwningPtr.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
@@
-56,7
+55,8
@@
class Spiller;
/// Register allocators must override the selectOrSplit() method to implement
/// live range splitting. They must also override enqueue/dequeue to provide an
/// assignment order.
/// Register allocators must override the selectOrSplit() method to implement
/// live range splitting. They must also override enqueue/dequeue to provide an
/// assignment order.
-class LLVM_LIBRARY_VISIBILITY RegAllocBase {
+class RegAllocBase {
+ virtual void anchor();
protected:
const TargetRegisterInfo *TRI;
MachineRegisterInfo *MRI;
protected:
const TargetRegisterInfo *TRI;
MachineRegisterInfo *MRI;
@@
-65,7
+65,8
@@
protected:
LiveRegMatrix *Matrix;
RegisterClassInfo RegClassInfo;
LiveRegMatrix *Matrix;
RegisterClassInfo RegClassInfo;
- RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0), Matrix(0) {}
+ RegAllocBase()
+ : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
virtual ~RegAllocBase() {}
virtual ~RegAllocBase() {}
@@
-105,4
+106,4
@@
private:
} // end namespace llvm
} // end namespace llvm
-#endif
// !defined(LLVM_CODEGEN_REGALLOCBASE)
+#endif