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[FastISel][AArch64] Fix a few BuildMI callsites where the result register was added...
[oota-llvm.git]
/
lib
/
CodeGen
/
RegAllocBasic.cpp
diff --git
a/lib/CodeGen/RegAllocBasic.cpp
b/lib/CodeGen/RegAllocBasic.cpp
index 0c958df3c5aeaead0d86a781ea703de70763fe35..6bc678e8521190bed76f37429a18c5215abdbe42 100644
(file)
--- a/
lib/CodeGen/RegAllocBasic.cpp
+++ b/
lib/CodeGen/RegAllocBasic.cpp
@@
-12,7
+12,6
@@
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "regalloc"
#include "llvm/CodeGen/Passes.h"
#include "AllocationOrder.h"
#include "LiveDebugVariables.h"
#include "llvm/CodeGen/Passes.h"
#include "AllocationOrder.h"
#include "LiveDebugVariables.h"
@@
-41,6
+40,8
@@
using namespace llvm;
using namespace llvm;
+#define DEBUG_TYPE "regalloc"
+
static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
createBasicRegisterAllocator);
static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
createBasicRegisterAllocator);
@@
-64,7
+65,7
@@
class RABasic : public MachineFunctionPass, public RegAllocBase
MachineFunction *MF;
// state
MachineFunction *MF;
// state
-
OwningP
tr<Spiller> SpillerInstance;
+
std::unique_p
tr<Spiller> SpillerInstance;
std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
CompSpillWeight> Queue;
std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
CompSpillWeight> Queue;
@@
-76,36
+77,34
@@
public:
RABasic();
/// Return the pass name.
RABasic();
/// Return the pass name.
-
virtual const char* getPassName() const
{
+
const char* getPassName() const override
{
return "Basic Register Allocator";
}
/// RABasic analysis usage.
return "Basic Register Allocator";
}
/// RABasic analysis usage.
- v
irtual void getAnalysisUsage(AnalysisUsage &AU) const
;
+ v
oid getAnalysisUsage(AnalysisUsage &AU) const override
;
- v
irtual void releaseMemory()
;
+ v
oid releaseMemory() override
;
-
virtual Spiller &spiller()
{ return *SpillerInstance; }
+
Spiller &spiller() override
{ return *SpillerInstance; }
- virtual float getPriority(LiveInterval *LI) { return LI->weight; }
-
- virtual void enqueue(LiveInterval *LI) {
+ void enqueue(LiveInterval *LI) override {
Queue.push(LI);
}
Queue.push(LI);
}
-
virtual LiveInterval *dequeue()
{
+
LiveInterval *dequeue() override
{
if (Queue.empty())
if (Queue.empty())
- return
0
;
+ return
nullptr
;
LiveInterval *LI = Queue.top();
Queue.pop();
return LI;
}
LiveInterval *LI = Queue.top();
Queue.pop();
return LI;
}
-
virtual
unsigned selectOrSplit(LiveInterval &VirtReg,
-
SmallVectorImpl<unsigned> &SplitVRegs)
;
+ unsigned selectOrSplit(LiveInterval &VirtReg,
+
SmallVectorImpl<unsigned> &SplitVRegs) override
;
/// Perform register allocation.
/// Perform register allocation.
-
virtual bool runOnMachineFunction(MachineFunction &mf)
;
+
bool runOnMachineFunction(MachineFunction &mf) override
;
// Helper for spilling all live virtual registers currently unified under preg
// that interfere with the most recently queried lvr. Return true if spilling
// Helper for spilling all live virtual registers currently unified under preg
// that interfere with the most recently queried lvr. Return true if spilling
@@
-126,7
+125,6
@@
RABasic::RABasic(): MachineFunctionPass(ID) {
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
- initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
@@
-143,7
+141,6
@@
void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<SlotIndexes>();
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
AU.addPreserved<SlotIndexes>();
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
- AU.addRequired<CalculateSpillWeights>();
AU.addRequired<LiveStacks>();
AU.addPreserved<LiveStacks>();
AU.addRequired<MachineBlockFrequencyInfo>();
AU.addRequired<LiveStacks>();
AU.addPreserved<LiveStacks>();
AU.addRequired<MachineBlockFrequencyInfo>();
@@
-160,7
+157,7
@@
void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
}
void RABasic::releaseMemory() {
}
void RABasic::releaseMemory() {
- SpillerInstance.reset(
0
);
+ SpillerInstance.reset();
}
}
@@
-279,6
+276,11
@@
bool RABasic::runOnMachineFunction(MachineFunction &mf) {
RegAllocBase::init(getAnalysis<VirtRegMap>(),
getAnalysis<LiveIntervals>(),
getAnalysis<LiveRegMatrix>());
RegAllocBase::init(getAnalysis<VirtRegMap>(),
getAnalysis<LiveIntervals>(),
getAnalysis<LiveRegMatrix>());
+
+ calculateSpillWeightsAndHints(*LIS, *MF,
+ getAnalysis<MachineLoopInfo>(),
+ getAnalysis<MachineBlockFrequencyInfo>());
+
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
allocatePhysRegs();
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
allocatePhysRegs();