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SelectionDAGBuilder::Clusterify : main functinality was replaced with CRSBuilder...
[oota-llvm.git]
/
lib
/
CodeGen
/
RegAllocBasic.cpp
diff --git
a/lib/CodeGen/RegAllocBasic.cpp
b/lib/CodeGen/RegAllocBasic.cpp
index a659f5b7825cf334bfe15abc6cfe1a24df8dbb1b..77ee3148f31aae395d6bd48dda59336ae06042ee 100644
(file)
--- a/
lib/CodeGen/RegAllocBasic.cpp
+++ b/
lib/CodeGen/RegAllocBasic.cpp
@@
-15,7
+15,6
@@
#define DEBUG_TYPE "regalloc"
#include "RegAllocBase.h"
#include "LiveDebugVariables.h"
#define DEBUG_TYPE "regalloc"
#include "RegAllocBase.h"
#include "LiveDebugVariables.h"
-#include "LiveRangeEdit.h"
#include "RenderMachineFunction.h"
#include "Spiller.h"
#include "VirtRegMap.h"
#include "RenderMachineFunction.h"
#include "Spiller.h"
#include "VirtRegMap.h"
@@
-24,6
+23,7
@@
#include "llvm/PassAnalysisSupport.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/PassAnalysisSupport.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
@@
-72,6
+72,11
@@
class RABasic : public MachineFunctionPass, public RegAllocBase
std::auto_ptr<Spiller> SpillerInstance;
std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
CompSpillWeight> Queue;
std::auto_ptr<Spiller> SpillerInstance;
std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
CompSpillWeight> Queue;
+
+ // Scratch space. Allocated here to avoid repeated malloc calls in
+ // selectOrSplit().
+ BitVector UsableRegs;
+
public:
RABasic();
public:
RABasic();
@@
-127,8
+132,8
@@
RABasic::RABasic(): MachineFunctionPass(ID) {
initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
- initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
+ initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
@@
-145,9
+150,6
@@
void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<SlotIndexes>();
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
AU.addPreserved<SlotIndexes>();
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
- if (StrongPHIElim)
- AU.addRequiredID(StrongPHIEliminationID);
- AU.addRequiredTransitiveID(RegisterCoalescerPassID);
AU.addRequired<CalculateSpillWeights>();
AU.addRequired<LiveStacks>();
AU.addPreserved<LiveStacks>();
AU.addRequired<CalculateSpillWeights>();
AU.addRequired<LiveStacks>();
AU.addPreserved<LiveStacks>();
@@
-185,7
+187,7
@@
void RABasic::spillReg(LiveInterval& VirtReg, unsigned PhysReg,
unassign(SpilledVReg, PhysReg);
// Spill the extracted interval.
unassign(SpilledVReg, PhysReg);
// Spill the extracted interval.
- LiveRangeEdit LRE(SpilledVReg, SplitVRegs,
0, &PendingSpills
);
+ LiveRangeEdit LRE(SpilledVReg, SplitVRegs,
*MF, *LIS, VRM
);
spiller().spill(LRE);
}
// After extracting segments, the query's results are invalid. But keep the
spiller().spill(LRE);
}
// After extracting segments, the query's results are invalid. But keep the
@@
-202,7
+204,7
@@
bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
// either the union or live intervals.
unsigned NumInterferences = 0;
// Collect interferences assigned to any alias of the physical register.
// either the union or live intervals.
unsigned NumInterferences = 0;
// Collect interferences assigned to any alias of the physical register.
- for (const u
nsigned
*asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
+ for (const u
int16_t
*asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
NumInterferences += QAlias.collectInterferingVRegs();
if (QAlias.seenUnspillableVReg()) {
LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
NumInterferences += QAlias.collectInterferingVRegs();
if (QAlias.seenUnspillableVReg()) {
@@
-214,7
+216,7
@@
bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
assert(NumInterferences > 0 && "expect interference");
// Spill each interfering vreg allocated to PhysReg or an alias.
assert(NumInterferences > 0 && "expect interference");
// Spill each interfering vreg allocated to PhysReg or an alias.
- for (const u
nsigned
*AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
+ for (const u
int16_t
*AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
spillReg(VirtReg, *AliasI, SplitVRegs);
return true;
}
spillReg(VirtReg, *AliasI, SplitVRegs);
return true;
}
@@
-233,6
+235,10
@@
bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
// selectOrSplit().
unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs) {
// selectOrSplit().
unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs) {
+ // Check for register mask interference. When live ranges cross calls, the
+ // set of usable registers is reduced to the callee-saved ones.
+ bool CrossRegMasks = LIS->checkRegMaskInterference(VirtReg, UsableRegs);
+
// Populate a list of physical register spill candidates.
SmallVector<unsigned, 8> PhysRegSpillCands;
// Populate a list of physical register spill candidates.
SmallVector<unsigned, 8> PhysRegSpillCands;
@@
-243,6
+249,11
@@
unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
++I) {
unsigned PhysReg = *I;
++I) {
unsigned PhysReg = *I;
+ // If PhysReg is clobbered by a register mask, it isn't useful for
+ // allocation or spilling.
+ if (CrossRegMasks && !UsableRegs.test(PhysReg))
+ continue;
+
// Check interference and as a side effect, intialize queries for this
// VirtReg and its aliases.
unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
// Check interference and as a side effect, intialize queries for this
// VirtReg and its aliases.
unsigned interfReg = checkPhysRegInterference(VirtReg, PhysReg);
@@
-250,9
+261,9
@@
unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
// Found an available register.
return PhysReg;
}
// Found an available register.
return PhysReg;
}
-
Queries[interfReg].collectInterferingVRegs(1
);
- LiveInterval *interferingVirtReg =
-
Queries[interfReg]
.interferingVRegs().front();
+
LiveIntervalUnion::Query &IntfQ = query(VirtReg, interfReg
);
+ IntfQ.collectInterferingVRegs(1);
+
LiveInterval *interferingVirtReg = IntfQ
.interferingVRegs().front();
// The current VirtReg must either be spillable, or one of its interferences
// must have less spill weight.
// The current VirtReg must either be spillable, or one of its interferences
// must have less spill weight.
@@
-276,7
+287,7
@@
unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
if (!VirtReg.isSpillable())
return ~0u;
DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
if (!VirtReg.isSpillable())
return ~0u;
- LiveRangeEdit LRE(VirtReg, SplitVRegs);
+ LiveRangeEdit LRE(VirtReg, SplitVRegs
, *MF, *LIS, VRM
);
spiller().spill(LRE);
// The live virtual register requesting allocation was spilled, so tell
spiller().spill(LRE);
// The live virtual register requesting allocation was spilled, so tell
@@
-331,7
+342,10
@@
bool RABasic::runOnMachineFunction(MachineFunction &mf) {
// Write out new DBG_VALUE instructions.
getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
// Write out new DBG_VALUE instructions.
getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
- // The pass output is in VirtRegMap. Release all the transient data.
+ // All machine operands and other references to virtual registers have been
+ // replaced. Remove the virtual registers and release all the transient data.
+ VRM->clearAllVirt();
+ MRI->clearVirtRegs();
releaseMemory();
return true;
releaseMemory();
return true;